US9196520B1 - Tape release systems and methods for semiconductor dies - Google Patents
Tape release systems and methods for semiconductor dies Download PDFInfo
- Publication number
- US9196520B1 US9196520B1 US14/449,148 US201414449148A US9196520B1 US 9196520 B1 US9196520 B1 US 9196520B1 US 201414449148 A US201414449148 A US 201414449148A US 9196520 B1 US9196520 B1 US 9196520B1
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- adhesive tape
- semiconductor
- tape
- chuck plate
- dies
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000002390 adhesive tape Substances 0.000 claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 claims abstract description 18
- 230000001788 irregular Effects 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000003068 static effect Effects 0.000 claims description 3
- 239000002313 adhesive film Substances 0.000 abstract description 13
- 235000012431 wafers Nutrition 0.000 description 16
- 239000000758 substrate Substances 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 230000009467 reduction Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 208000034965 Nemaline Myopathies Diseases 0.000 description 1
- 239000004677 Nylon Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009189 diving Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920001778 nylon Polymers 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000012913 prioritisation Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68354—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support diced chips prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
Definitions
- This disclosure relates generally to semiconductors, and more specifically, to systems and methods for releasing semiconductor dies from an adhesive tape or film.
- pre-packaging processes may include a variety of operations including, for example, semiconductor substrate mounting, wafer sawing, die separation, die transfer, die attach, and the like. These operations involve physically manipulating chips and therefore require the utmost care, as damaged chips increase processing costs and reduce yield.
- semiconductor technology continues to evolve in such a way that chip substrates have become more and more fragile (e.g., thinner), thus making chips incorporating those substrates more susceptible to fractures.
- the adhesive tape may provide support for the wafers during singulation, die transfer, or die attach operations.
- a wafer saw or other cutting mechanism separates individual dies from the wafer while leaving them bonded onto the adhesive tape.
- a die attach operation or a sorting operation removes individual die from the adhesive tape or film and attaches them to a packaging substrate (e.g., a leadframe), or transfers them to another carrier for storage and later use.
- a conventional die bonder ejector system may include rod(s) or pin(s) configured to push each chip up and to separate it from the tape, thereby facilitating subsequent transport of the die by a pickup tool or the like. The inventors hereof have determined, however, that the use of ejector pins causes yet additional stresses on the dies, further increasing the risk of damage.
- FIG. 1 is a flowchart of a method for releasing semiconductor dies from an adhesive tape or film, according to some embodiments.
- FIG. 2 is a perspective view of a semiconductor die array and chuck plate, according to some embodiments.
- FIG. 3 is a cross-section view of an example of a tape release system, according to some embodiments.
- FIG. 4 is a perspective view of a semiconductor die array, chuck plate, and lid according to some embodiments.
- FIG. 5 is a cross-section view of another example of a tape release system, according to some embodiments.
- the systems and methods for releasing semiconductor dies from an adhesive tape or film described herein employ a tape release element (e.g., a wire mesh, a machined chuck plate, etc.) having an irregular on uneven surface (e.g., peaks and valleys) configured to facilitate detachment or peeling of one or more dies from the adhesive tape.
- a tape release element e.g., a wire mesh, a machined chuck plate, etc.
- uneven on uneven surface e.g., peaks and valleys
- semiconductor wafer refers to a slice of semiconductor material, such as a silicon crystal, for example, that may be used in the fabrication of integrated circuits (ICs) or other devices (e.g., microelectromechanical systems or “MEMs,” nanoelectromechanical systems or “NEMs,” etc.).
- the wafer serves as the substrate for the devices built upon it, and it may therefore be subject to various fabrication processes, such as, for instance, doping or ion implantation, etching, deposition, or photolithographic patterning.
- the individual dies are separated or diced as part of a singulation process, and then packaged in a casing or container.
- wafers are typically mounted on an adhesive tape or film, which has a sticky backing that holds the wafer on a frame.
- the adhesive tape or film may have different properties depending on the dicing application. For example, ultraviolet (UV) tapes may be used for smaller die sizes and non-UV tape may be used for larger die sizes.
- UV tapes ultraviolet (UV) tapes may be used for smaller die sizes and non-UV tape may be used for larger die sizes.
- the pieces left on the dicing tape are referred to as die, dice or dies.
- the size of the dies left on the adhesive tape may range from approximately 35 mm to 0.1 mm square. And although each die may have any desirable shape, they are typically rectangular or square shaped.
- die array or “array of dies” refers to a plurality of dies bonded to adhesive tape of film, whether as a result of a wafer dicing operation or not.
- individual dies may be bonded to adhesive tape or film, after or independently of a wafer diving operation, to facilitate the subsequent storage or handling of those dies.
- FIG. 1 is a flowchart of a method for releasing semiconductor dies from an adhesive tape or film, according to some embodiments.
- method 100 includes disposing a plurality of semiconductor chips, which are bonded to an adhesive tape or film, over a tape release element.
- the tape release element may be disposed on the surface of a vacuum chuck plate. As illustrated in FIGS. 2 and 3 , the tape release element may include a wire mesh or the like. Additionally or alternatively, FIG. 5 illustrates a scenario where the tape release element may be a machined surface of the vacuum chuck plate (e.g., physical protrusions or the like).
- the tape release elements described herein may be characterized as “static” insofar as they do not physically move with respect to the dies during a tape release operation.
- method 100 includes applying a negative pressure via the vacuum chuck plate and/or a positive pressure via a lid or cup to the plurality of semiconductor chips and/or adhesive tape.
- a negative pressure via the vacuum chuck plate and/or a positive pressure via a lid or cup
- the adhesive tape may be made to conform to the uneven or irregular surface of the tape release element, thus at least partially detaching from the underside of the die(s).
- heat may also be applied via the chuck plate to further facilitate the separation of the die(s) from the tape.
- the tape release element may provide die support and also a vacuum conduct that runs under the backside of the wafer/dies, such that the adhesive tape is peeled from the backside of the dies contained in the array by application of negative pressure to the bottom of the tape and/or by the application of positive pressure to the top of the tape, for instance, in connection with a pick and place operation.
- method 100 may include removing at least one of the plurality of semiconductor chips from the at least partially peeled adhesive tape using a vacuum pick up tool or the like.
- Method 100 may reduce the stress on dies and lower the risk of die crack during die pickup by eliminating the need for ejector pin to remove dies from the adhesive tape. As such, method 100 may be particularly important in the fabrication, handling, or backend assembly of very thin or fragile dies such as, for instance, dies with many Through-Silicon Vias (TSVs). It should be noted that, in various implementations of method 100 , a conventional ejector is not needed and pins may not be needed.
- TSVs Through-Silicon Vias
- FIG. 2 presents a perspective view of a semiconductor die array and chuck plate according to some embodiments.
- the die array includes a plurality of dies 200 A-N bonded to adhesive tape 201 .
- the die array is arranged in a rectangular shape, and each of dies 200 A-N is already singulated or otherwise separated from one another.
- Adhesive tape 201 is stretched or supported by frame 202 , which may be a metal frame or the like.
- Vacuum chuck plate 203 is also shown, and it includes tape release element 204 disposed on or otherwise fabricated on its surface.
- FIG. 3 is a cross-section view of an example of a tape release system according to some embodiments.
- Chuck plate 203 includes two or more vacuum lines or channels 300 A-N, via which a negative pressure is applied to the underside of adhesive tape 201 .
- the negative pressure causes tape 201 to conform to the shape of the surface of tape release element 204 and reduces physical contact between adhesive tape 201 and the bottom portion of each of the plurality of dies 200 A-N.
- vacuum pickup tool 301 may lift each of dies 200 A-N and transport them to another location to perform any suitable subsequent operation(s), for example, via a chip carrier or the like.
- tape release element 204 may be configured with an irregular or uneven surface.
- tape release element 204 may include a wire mesh or the like.
- a wire mesh may be made of a suitable material ranging from nylon to stainless steel, for example.
- the geometric pattern provided by the wire mesh or may be configured specifically for a particular type of tape (e.g., the tape's tackiness, flexibility, etc.), a particular type of semiconductor array (e.g., number of chips, spacing between chips, size of each chip, etc.), or for a given type of applied pressure (e.g., negative and/or positive pressure, amount of pressure, etc.).
- the irregular surface of tape release element 204 may include a pattern of peaks and valleys such that, when adhesive tape 201 conforms to the pattern due to the application of vacuum by chuck plate 203 , it reduces the contact surface between adhesive tape 201 and dies 200 A-N, therefore facilitating the complete removal of each of dies 200 A-N by pickup tool 301 .
- the reduction in contact surface between adhesive tape 201 and each of dies 200 A-N due to the application of vacuum may be approximately 25%. In other implementations, the reduction may be approximately 50%. In yet other implementations, the reduction may be approximately 75%.
- the peaks and valleys may be configured such that at least a predetermined number of peaks (e.g., three peaks) continue to make contact with any given chip—that is, the spacing between neighboring peaks may be directly proportional to the size or surface area of each chip in the array—and so that tape release element 204 may continue to support each individual chip after application of pressure.
- peaks and valleys may be configured such that at least a predetermined number of peaks (e.g., three peaks) continue to make contact with any given chip—that is, the spacing between neighboring peaks may be directly proportional to the size or surface area of each chip in the array—and so that tape release element 204 may continue to support each individual chip after application of pressure.
- chuck plate 203 may include a heating element configured to apply heat to adhesive tape in order to activate or soften the tape to facilitate peeling of the tape due to the vacuum application.
- vacuum pickup tool 301 is configured to pick up each individual one of the plurality of dies 200 A-N without the use of an ejector pin.
- FIG. 4 is a perspective view of a semiconductor die array, chuck plate, and lid according to some embodiments.
- singulated dies 200 A-N are bonded to adhesive tape 201 , which is stretched or supported by frame 202 .
- vacuum lid or cup 400 is provided to cover the array of semiconductor dies.
- Lid 400 includes one or more channels configured to apply a positive pressure upon adhesive tape 201 to aid in the peeling process.
- use of lid 400 may allow use of higher pressure levels inside the chamber formed between lid 400 and the chuck plate (not shown).
- FIG. 5 is a cross-section view of another example of a tape release system, according to some embodiments.
- chuck plate 203 includes two or more vacuum lines 300 A-N, via which a negative pressure is applied to the underside of adhesive tape 201 , and that in turn causes tape 201 to conform to the shape of the surface of tape release element 500 to reduce the contact area between adhesive tape 201 and the bottom portion of each of the plurality of dies 200 A-N.
- tape release element 500 is machined onto chuck plate 203 itself.
- tape release element 500 may be provided in the form of a plurality of protrusions or holes fabricated on the surface of the chuck plate.
- chuck plate 203 tape release element 500 may be a detachable surface or plate coupled to the surface of chuck plate 203 .
- tape release element 500 may include vacuum channels that match the channels of chuck plate 203 , the bottom side of tape release element 500 may be flat, and the top side may include machined protrusions or holes.
- design considerations regarding the pattern of peaks and valleys of tape release element 500 are similar to those discussed in connection with FIG. 3 .
- a semiconductor manufacturing device may include a chuck plate configured to support an array of semiconductor dies, where each die in the array has a top surface and a bottom surface, where each die's bottom surface is bonded to an adhesive tape, and where the chuck plate comprises one or more channels configured to apply a negative pressure to the adhesive tape; and a tape release element having an irregular surface, the tape release element disposed between the chuck plate and the adhesive tape.
- the array of semiconductor dies may include or otherwise be part of a semiconductor wafer.
- the tape release element may include a wire mesh. Additionally or alternatively, the tape release element may include a plurality of protrusions fabricated on a surface of the chuck plate. Moreover, the chuck plate may include a heating element configured to apply heat to the adhesive tape.
- the irregular surface may include a plurality of peaks and valleys.
- the adhesive tape may be configured to, upon application of the negative pressure, conform to at least a portion of the peaks and valleys to reduce a contact surface between the adhesive tape and the array of semiconductor dies.
- the semiconductor manufacturing may further include a vacuum pickup tool configured to pick up each individual one of the plurality of dies upon application of the negative pressure.
- the vacuum pickup tool may be configured to pick up each individual one of the plurality of dies without the use of an ejector pin.
- the semiconductor manufacturing device may further include a lid configured to cover the array of semiconductor dies and to apply a positive pressure to the adhesive tape.
- a method may include disposing a plurality of semiconductor chips over an uneven surface of a chuck plate, where the plurality of semiconductor chips are bonded to an adhesive tape; conforming at least a portion of the adhesive tape to the uneven surface by applying a pressure to the plurality of semiconductor chips; and removing at least one of the plurality of semiconductor chips from the adhesive tape.
- the uneven surface may include a wire mesh. Additionally or alternatively, the uneven surface may include a plurality of protrusions fabricated on a surface of the chuck plate.
- the method may further include applying heat to the plurality of semiconductor chips prior to removing the at least one semiconductor chip.
- the pressure may include a negative pressure applied to an underside of the plurality of semiconductor chip via one or more vacuum lines of the chuck plate prior to removing the at least one semiconductor chip.
- the pressure may include a positive pressure applied to a top side of the plurality of semiconductor chip via one or more vacuum lines of a lid prior to removing the at least one semiconductor chip.
- a tape release system may include a chuck plate configured to support an array of semiconductor dies bonded to an adhesive tape and a static tape release element disposed between the chuck plate and the adhesive tape.
- the chuck plate may include one or more vacuum lines configured to apply a negative pressure to a bottom side of the adhesive tape.
- the tape release element comprises a wire mesh having a plurality of peaks and valleys and/or a plurality of protrusions fabricated on a surface of the chuck plate.
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
Claims (18)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US14/449,148 US9196520B1 (en) | 2014-08-01 | 2014-08-01 | Tape release systems and methods for semiconductor dies |
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US14/449,148 US9196520B1 (en) | 2014-08-01 | 2014-08-01 | Tape release systems and methods for semiconductor dies |
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US9196520B1 true US9196520B1 (en) | 2015-11-24 |
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US14/449,148 Active US9196520B1 (en) | 2014-08-01 | 2014-08-01 | Tape release systems and methods for semiconductor dies |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN106128993A (en) * | 2016-07-20 | 2016-11-16 | 无锡宏纳科技有限公司 | A kind of fixture being carried out chip pickup movement by negative pressure |
CN107221510A (en) * | 2016-03-22 | 2017-09-29 | 晟碟信息科技(上海)有限公司 | The system and method for film strips separating semiconductor naked core are attached from naked core |
US20180056548A1 (en) * | 2013-11-26 | 2018-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vacuum Carrier Module, Method of Using and Process of Making the Same |
DE102018221148A1 (en) * | 2018-12-06 | 2020-06-10 | Heraeus Deutschland GmbH & Co. KG | Method for producing a substrate adapter and substrate adapter for connecting to an electronic component |
US20230317500A1 (en) * | 2022-03-31 | 2023-10-05 | Intel Corporation | Heat-assisted die ejection system |
TWI839419B (en) * | 2019-11-27 | 2024-04-21 | 日商邦德科技股份有限公司 | Component mounting system, component supply device, and component mounting method |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4667402A (en) | 1983-10-07 | 1987-05-26 | Siemens Aktiengesellschaft | Method for micro-pack production |
US4859269A (en) | 1987-08-31 | 1989-08-22 | Sumitomo Electric Industries, Ltd. | Chip mounting apparatus |
US6106222A (en) * | 1996-03-29 | 2000-08-22 | Ngk Insulators, Ltd. | Method of peeling off chips using peeling plate with integrally formed first and second protrusions |
US6582223B2 (en) * | 2000-11-24 | 2003-06-24 | Sharp Kabushiki Kaisha | Pickup apparatus for semiconductor chips |
US6869264B2 (en) * | 2002-11-11 | 2005-03-22 | Samsung Electronics Co., Ltd | Method and apparatus for picking up a semiconductor chip, method and apparatus for removing a semiconductor chip from a dicing tape, and a method of forming a perforated dicing tape |
US6889427B2 (en) | 2002-02-15 | 2005-05-10 | Freescale Semiconductor, Inc. | Process for disengaging semiconductor die from an adhesive film |
US7632374B2 (en) * | 2002-07-17 | 2009-12-15 | Panasonic Corporation | Method and apparatus for picking up semiconductor chip and suction and exfoliation tool used therefor |
US8497189B1 (en) * | 2012-01-24 | 2013-07-30 | Disco Corporation | Processing method for wafer |
US8691666B2 (en) * | 2007-04-17 | 2014-04-08 | Lintec Corporation | Method for producing chip with adhesive applied |
-
2014
- 2014-08-01 US US14/449,148 patent/US9196520B1/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4667402A (en) | 1983-10-07 | 1987-05-26 | Siemens Aktiengesellschaft | Method for micro-pack production |
US4859269A (en) | 1987-08-31 | 1989-08-22 | Sumitomo Electric Industries, Ltd. | Chip mounting apparatus |
US6106222A (en) * | 1996-03-29 | 2000-08-22 | Ngk Insulators, Ltd. | Method of peeling off chips using peeling plate with integrally formed first and second protrusions |
US6582223B2 (en) * | 2000-11-24 | 2003-06-24 | Sharp Kabushiki Kaisha | Pickup apparatus for semiconductor chips |
US6889427B2 (en) | 2002-02-15 | 2005-05-10 | Freescale Semiconductor, Inc. | Process for disengaging semiconductor die from an adhesive film |
US7632374B2 (en) * | 2002-07-17 | 2009-12-15 | Panasonic Corporation | Method and apparatus for picking up semiconductor chip and suction and exfoliation tool used therefor |
US6869264B2 (en) * | 2002-11-11 | 2005-03-22 | Samsung Electronics Co., Ltd | Method and apparatus for picking up a semiconductor chip, method and apparatus for removing a semiconductor chip from a dicing tape, and a method of forming a perforated dicing tape |
US8691666B2 (en) * | 2007-04-17 | 2014-04-08 | Lintec Corporation | Method for producing chip with adhesive applied |
US8497189B1 (en) * | 2012-01-24 | 2013-07-30 | Disco Corporation | Processing method for wafer |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20180056548A1 (en) * | 2013-11-26 | 2018-03-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vacuum Carrier Module, Method of Using and Process of Making the Same |
US10137603B2 (en) * | 2013-11-26 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Vacuum carrier module, method of using and process of making the same |
CN107221510A (en) * | 2016-03-22 | 2017-09-29 | 晟碟信息科技(上海)有限公司 | The system and method for film strips separating semiconductor naked core are attached from naked core |
CN107221510B (en) * | 2016-03-22 | 2020-09-15 | 晟碟信息科技(上海)有限公司 | System and method for separating semiconductor die from die attach film tape |
CN106128993A (en) * | 2016-07-20 | 2016-11-16 | 无锡宏纳科技有限公司 | A kind of fixture being carried out chip pickup movement by negative pressure |
DE102018221148A1 (en) * | 2018-12-06 | 2020-06-10 | Heraeus Deutschland GmbH & Co. KG | Method for producing a substrate adapter and substrate adapter for connecting to an electronic component |
US11440310B2 (en) * | 2018-12-06 | 2022-09-13 | Heraeus Deutschland GmbH & Co. KG | Method for producing a substrate adapter and substrate adapter for connecting to an electronic component |
TWI839419B (en) * | 2019-11-27 | 2024-04-21 | 日商邦德科技股份有限公司 | Component mounting system, component supply device, and component mounting method |
US20230317500A1 (en) * | 2022-03-31 | 2023-10-05 | Intel Corporation | Heat-assisted die ejection system |
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