US8666063B2 - Method and apparatus for minimizing differential power attacks on processors - Google Patents
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- US8666063B2 US8666063B2 US12/837,268 US83726810A US8666063B2 US 8666063 B2 US8666063 B2 US 8666063B2 US 83726810 A US83726810 A US 83726810A US 8666063 B2 US8666063 B2 US 8666063B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
- H04L9/3247—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials involving digital signatures
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1408—Protection against unauthorised use of memory or access to memory by using cryptography
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
- G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/724—Finite field arithmetic
- G06F7/725—Finite field arithmetic over elliptic curves
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
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- G—PHYSICS
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- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
- G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
- G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
- G06F2207/7223—Randomisation as countermeasure against side channel attacks
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
- G06F2207/7219—Countermeasures against side channel or fault attacks
- G06F2207/7223—Randomisation as countermeasure against side channel attacks
- G06F2207/7233—Masking, e.g. (A**e)+r mod n
- G06F2207/7242—Exponent masking, i.e. key masking, e.g. A**(e+r) mod n; (k+r).P
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/04—Masking or blinding
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- This invention relates to cryptographic systems and in particular to a method and apparatus for minimizing successful power analysis attacks on processors.
- Cryptographic systems generally owe their security to the fact that a particular piece of information is kept secret, without which it is almost impossible to break the scheme.
- This secret information must generally be stored within a secure boundary, making it difficult for an attacker to get at it directly however, various schemes or attacks have been attempted in order to obtain the secret information.
- portable cryptographic tokens including smart cards and the like.
- simple power analysis differential power analysis
- higher order differential power analysis and other related techniques.
- These technically sophisticated and extremely powerful analysis tools can be used by an attacker to extract secret keys from cryptographic devices. It has been shown that these attacks can be mounted quickly and can be implemented using readily available hardware. The amount of time required for these attacks depends on the type of attack and varies somewhat by device. For example it has been shown that a simple power attack (SPA) typically take a few seconds per card, while the differential power attacks (DPA) can take several hours.
- SPA simple power attack
- DPA differential power attacks
- Encryption operations are performed in a processor operating in a sequential manner by performing a sequence of fundamental operations, each of which generates a distinct timing pattern. Laborious but careful analysis of end-to-end power waveforms can decompose the order of these fundamental operations performed on each bit of a secret key and thus be, analyzed to find the entire secret key, compromising the system.
- the differential power analysis attack is a more powerful attack than the SPA and is much more difficult to prevent.
- the DPA uses statistical analysis and error correction techniques to extract information which may be correlated to secret keys, while the SPA attacks use primarily visual inspection to identify relevant power fluctuations.
- the DPA attack is performed in two steps. The first step is recording data that reflects the change in power consumed by the card during execution of cryptographic routines. In the second step, the collected data is statistically analyzed to extract information correlated to secret keys. A detailed analysis of these attacks is described in the paper entitled “Introduction to Differential Power Analysis and Related Attacks” by Paul Kocher et al.
- branches in program flow are particularly vulnerable to power analysis measurements.
- V some distinguishing value
- one of two branches of the program is executed.
- V is compared with a threshold value and a jump to one of two locations is executed as a result of the comparison.
- FIG. 1 a flow diagram showing the implementation of a typical conditional jump according to the prior art is shown generally by 10.
- a conditional jump implements an “IF condition THEN statement1 ELSE statement2” clause.
- the flow diagram indicates a scenario where a distinguishing value V varies within a range and the condition is whether a threshold value TH is crossed by the distinguishing value V or not.
- the threshold TH is a random number between an upper limit and a lower limit VMAX and VMIN, respectively.
- It is an object of this invention is to provide a method for minimizing power analysis attacks on processors.
- a method of masking a conditional jump operation in a processor wherein program execution jumps to one of two branches dependent on a first or second condition of a distinguishing value V relative to a reference value and wherein the reference is bounded by an upper limit Vmax and a lower limit Vmin, the method comprising the steps of:
- the distinguishing value is combined with a random value, thereby adding a random number of instructions on every condition evaluation.
- FIG. 1 is schematic diagram of a conditional operation
- FIG. 2 is part of a computer program according to an embodiment of the present invention.
- FIG. 3 is part of a computer program according to a further embodiment of the present invention.
- FIG. 4 is part of a computer program according to a still further embodiment of the present invention.
- FIG. 5 is a flow diagram illustrating another embodiment of the invention.
- FIG. 2 a schematic diagram of a method for masking conditional jump statements in a computer program, according to an embodiment of the present invention, is shown generally by numeral 50 .
- a distinguishing value V varies within a known range and the condition is whether a threshold value TH is crossed by the distinguishing value V or not.
- the threshold TH is a random number in the known range having an upper limit and a lower limit VMAX and VMIN, respectively.
- the method comprises the steps of identifying a location for a conditional jump operation, and inserting at the location a call 52 to a subroutine 54 , the subroutine 54 including instructions for changing the return address of the subroutine to one of two program branches to execute branch statements1 or branch statements2 in response to the result of a comparison of the distinguishing value V to the threshold value.
- the subroutine is identified as IRRITATE_ 1 ( 54 ) and includes code blocks identified as b and c.
- the code block c includes a first and second sections 56 and 58 , respectively.
- the start address of the second section 58 is predetermined and is indicated by the value KNOWN_DISPLACEMENT.
- the start address of the first section 56 is then determined by the difference between KNOWN_DISPLACEMENT and the upper limit of the distinguishing value V.
- the first section 56 consists of a series of conditional jumps to an address L 1 and the second section 58 consists of a series of unconditional jumps to an address L 2 .
- the locations L 1 and L 2 contain code for returning program flow to execute statements1 and statements2 respectively.
- the code block b included in the subroutine IRRITATE_ 1 includes code for computing a difference between the KNOWN_DISPLACEMENT address and the THRESHOLD. The resulting address is then added to the distinguishing value V to derive a target address location in one of the sections 56 or 58 .
- V is preserved while calling the subroutine, which in turn does not contain any conditional jumps.
- this subroutine we change the return address of the subroutine (which resides on the stack) depending on whether V is below or above TH in such a way that, after returning from the subroutine, the program will continue execution in the desired branch.
- extended addressing An addressing mode known as extended addressing is used to determine the target address.
- extended addressing the address at which the execution of the program has to continue is computed as the sum of the content of two registers.
- JMP @A+DPTR in the assembly language of the Intel 8051 family means that the address at which the program execution has to continue is computed by adding the content of the accumulator A and the data pointer DPTR.
- Other processors may support similar mechanisms for addressing.
- the code fragments shown in FIG. 2 illustrate the method. To refer to lines of these code fragments we use labels consisting of a letter and a number. Thus to implement this method we have to specify:
- the code fragments shown in FIG. 2 will be discussed below.
- the code fragments may be located within a loop, which sequentially changes the value of V in a given range for iterations of the loop.
- V may the value of the loop counter.
- the THRESHOLD value is a random value within the known range of Vmin and Vmax.
- the distinguishing value V is stored in the accumulator of the processor and the subroutine IRRITATE_ 1 is called at line a 2 .
- the return address from this subroutine will be line a 3 , which is automatically stored on the stack by the processor.
- KNOWN_DISPLACEMENT in line b 1 is a constant value that specifies the beginning location of the second section 58 and indicates the address of line c 9 .
- KNOWN_DISPLACEMENT ⁇ Vmax is the address of line c 1 , the beginning location of the first section 56 .
- Block b the value of KNOWN_DISPLACEMENT is stored in a register at line b 1 .
- the register is updated with the difference of KNOWN_DISPLACEMENT and THRESHOLD. This difference is moved to in DPTR at line b 3 .
- the labels L 1 and L 2 point to addresses located at lines c 17 and c 21 respectively.
- the return address of the subroutine IRRITATE_ 1 is retrieved and changed such that the program counter will point to line a 3 after returning from the subroutine.
- the return address of the subroutine IRRITATE_ 1 is also retrieved and changed such that the program counter will point to line a 4 after returning from the subroutine.
- the simple jump instructions at lines a 3 and a 4 are examples of the return address of the subroutine IRRITATE_ 1 is retrieved and changed such that the program counter will point to line a 4 after returning from the subroutine.
- jump instructions in lines a 3 and a 4 which redirect program flow to statements1 and statements2 respectively, should be placed at addresses with the same number of 1's in their binary representation. This would result in homogenous power consumption on the address bus while addressing these two different locations.
- the same precaution applies to the lines d 1 and c 1 , the beginning location of statements1 and statements2 respectively.
- special attention should be paid to the choice of values of THRESHOLD and KNOWN_DISPLACEMENT to avoid changes in flags in the processors status word while the SUB instruction is being executed.
- a second embodiment of the present invention is shown generally by numeral 100 .
- This embodiment also utilizes extended addressing as described earlier. Again, assembly language of the Intel 8051 family of processors is used to illustrate the method. For clarity the symbols op 1 through op 7 are used to represent program instructions.
- the distinguishing value V is one of two distinct values Vmax and Vmin, rather than a range of values. Thus, the condition in this case is when the distinguishing value V is one or the other of the distinct values Vmax or Vmin.
- the subroutine including instructions for changing the return address of the subroutine to one of two program branches to execute branch statements1 or branch statements2 in response to the distinguishing value V being one of the two distinct values Vmax or Vmin.
- the subroutine is identified as IRRITATE_ 2 ( 102 ) and includes code blocks identified as blocks g, h and i.
- the code block h also includes first and second sections 106 and 108 , respectively. Each of the sections contain a series of dummy operations op 1 indicated at lines h 1 through h 7 and at lines h 12 through h 18 .
- Each of the sections is terminated by a sequence of instructions for retrieving the return address of the subroutine IRRITATE_ 2 and changing it such that the program counter will point to line f 4 or f 5 after returning from the subroutine.
- the lines f 4 and f 4 include jumps to one of the two branches indicates as block i and block j which contain statements1 and statements2 respectively.
- the target destination address is comprised of two components, namely the distinguishing value V or a value derived from V and a random number MASKED_RANDOM, that are added at line g 1 .
- the beginning address of the first and second sections are chosen such that this target address is either in the range of lines h 1 through h 8 or h 12 through h 19 . Since, the second component of the target address is a random number, a random number of dummy operations will be executed before the return address of the subroutine IRRITATE_ 2 is computed at lines h 8 to h 10 (or h 19 to h 21 ).
- the ADD values at lines h 9 and h 20 may be chosen to have the same hamming weight (number of 1's), with appropriate number of NOP instructions added to block f.
- the jump instructions at lines f 4 and f 5 may be placed at addresses with the same number of one's. Additional JMP instructions may also be inserted between the lines h 1 and h 8 with a destination in the same segment.
- This embodiment thus uses unconditional jumps instead of conditional jumps and adds a random number of dummy operations to the code.
- the former property is a countermeasure against SPA and the latter makes DPA attacks more difficult.
- this embodiment adds a random mask or noise to the program execution path since the jump to a random address within a segment causes program execution of a random number of operations before one of the branches is executed. Therefore each time one of the branches is executed, the number of operations performed by the processor varies randomly making DPA attacks more difficult.
- an embodiment of a method for masking a private key or secret value used in a cryptographic operation is shown generally by numeral 200 .
- the method comprises the steps of dividing a secret value into a plurality of parts and combining with each part a random value modulo n (where n is the number of points on the elliptic curve) to derive a new part such that the new parts are combined to be equivalent to the original secret value and utilizing each of the individual parts in the operation.
- the secret value is a private key, which is used to compute a public key, and more frequently used in signatures, decryption and possible key exchange protocols, such as Diffie-Hellman key exchange.
- These initial values of b 1 and b 2 are stored instead of d.
- the d value may also be stored if so desired, however in the case of a smart card where memory is limited this may not be desirable.
- the updated values b 1 and b 2 are stored.
- Both the secret keys in the above example may be masked using the method of the present invention.
- calculation of the product e may reveal some information on some platforms in some environments.
- the components b 0 , b 1 are updated periodically as described above. This updating of the components can be made on every new signature operation.
- the secret value was divided into two components b 0 , b 1 , however this may be generalized to a plurality of components b 0 . . . b n ⁇ 1 .
- the above signature scheme is used for illustrative purposes and other schemes and operations may equally well be applied using the present invention.
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Abstract
Description
-
- a) the address at which the block of
code 56 is going to reside. That would be the address of the first JMP L1; - b) the range of the distinguishing value V; and
- c) the maximum value of the random threshold TH. This maximum value or a value derived from it will define the size of the code block containing the JMP L1 and JMP L2 instructions.
- a) the address at which the block of
b 1 =b 1+π mod n
b 2 =b 2−π mod n.
The updated values b1 and b2 are stored. Computation is then performed on the point P using the components b1 and b2 as follows:
dP mod n=b 1 P+b 2 P mod n
where, P is a point on the curve which is a predefined parameter of the system.
s=œ+k(mod n)
where:
-
- k is a random integer selected as a short term private or session key;
- R=kP is the corresponding short teem public key;
- r=Rx x component of R
- a is the long term private key of the sender;
- Q=aP is the senders corresponding public key;
- e is a secure hash, such as the SHA-1 hash function, of a message m and the short term public key R (or possibly a short message itself); and n is the order of the curve.
Claims (18)
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US12/837,268 US8666063B2 (en) | 1999-01-11 | 2010-07-15 | Method and apparatus for minimizing differential power attacks on processors |
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CA2258338 | 1999-01-11 | ||
CA002258338A CA2258338C (en) | 1999-01-11 | 1999-01-11 | Method and apparatus for minimizing differential power attacks on processors |
CA2,258,338 | 1999-01-11 | ||
CA2259089 | 1999-01-15 | ||
CA2,259,089 | 1999-01-15 | ||
CA 2259089 CA2259089C (en) | 1999-01-15 | 1999-01-15 | Method and apparatus for masking cryptographic operations |
PCT/CA2000/000021 WO2000042511A1 (en) | 1999-01-11 | 2000-01-11 | Method and apparatus for minimizing differential power attacks on processors |
PCT/CA2000/000030 WO2000042733A1 (en) | 1999-01-15 | 2000-01-14 | Method and apparatus for masking cryptographic operations |
US09/900,959 US7092523B2 (en) | 1999-01-11 | 2001-07-10 | Method and apparatus for minimizing differential power attacks on processors |
US11/483,553 US8666070B2 (en) | 1999-01-11 | 2006-07-11 | Method and apparatus for minimizing differential power attacks on processors |
US12/837,268 US8666063B2 (en) | 1999-01-11 | 2010-07-15 | Method and apparatus for minimizing differential power attacks on processors |
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US11/483,553 Continuation US8666070B2 (en) | 1999-01-11 | 2006-07-11 | Method and apparatus for minimizing differential power attacks on processors |
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US8666063B2 true US8666063B2 (en) | 2014-03-04 |
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US11/483,553 Expired - Lifetime US8666070B2 (en) | 1999-01-11 | 2006-07-11 | Method and apparatus for minimizing differential power attacks on processors |
US12/837,268 Expired - Fee Related US8666063B2 (en) | 1999-01-11 | 2010-07-15 | Method and apparatus for minimizing differential power attacks on processors |
US13/621,021 Expired - Fee Related US8660264B2 (en) | 1999-01-11 | 2012-09-15 | Method and apparatus for minimizing differential power attacks on processors |
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US9323955B2 (en) * | 2000-12-21 | 2016-04-26 | Gemalto Sa | Method for protecting a logic or mathematical operator installed in an electronic module with a microprocessor as well as the associated embedded electronic module and the system |
JP2005519527A (en) * | 2002-03-07 | 2005-06-30 | アクサルト・エス・アー | How to securely protect an electronic cryptographic assembly with a private key |
US7549059B2 (en) * | 2002-06-26 | 2009-06-16 | Arm Limited | Transferring data values via a data bus or storing data values using a selectable representation |
FR2849232B1 (en) * | 2002-12-24 | 2005-02-25 | Trusted Logic | METHOD FOR SECURING COMPUTER SYSTEMS INCORPORATING A CODE INTERPRETATION MODULE |
FR2849233B1 (en) * | 2002-12-24 | 2005-05-20 | Trusted Logic | METHOD FOR SECURING COMPUTER SYSTEMS BY SOFTWARE CONFINEMENT |
US20040162993A1 (en) * | 2003-02-13 | 2004-08-19 | Yannick Teglia | Antifraud method of an algorithm executed by an integrated circuit |
JP2005056413A (en) * | 2003-08-01 | 2005-03-03 | Stmicroelectronics Sa | Protection of multiple identical computations |
KR101061906B1 (en) | 2004-02-19 | 2011-09-02 | 삼성전자주식회사 | Basic Computing Device and Method Safe for Power Analysis Attack |
DE602005015157D1 (en) * | 2004-05-11 | 2009-08-13 | St Microelectronics Sa | Branch protection in a program |
DE102006014353B4 (en) * | 2006-03-28 | 2007-11-22 | Siemens Ag | Method for the reliable determination of data |
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Also Published As
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US20070053509A1 (en) | 2007-03-08 |
US20130101112A1 (en) | 2013-04-25 |
US7092523B2 (en) | 2006-08-15 |
US20020029346A1 (en) | 2002-03-07 |
US8660264B2 (en) | 2014-02-25 |
US20100278334A1 (en) | 2010-11-04 |
US8666070B2 (en) | 2014-03-04 |
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