WO2000042733A1 - Method and apparatus for masking cryptographic operations - Google Patents

Method and apparatus for masking cryptographic operations Download PDF

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Publication number
WO2000042733A1
WO2000042733A1 PCT/CA2000/000030 CA0000030W WO0042733A1 WO 2000042733 A1 WO2000042733 A1 WO 2000042733A1 CA 0000030 W CA0000030 W CA 0000030W WO 0042733 A1 WO0042733 A1 WO 0042733A1
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Prior art keywords
parts
method
operation
secret value
value
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Application number
PCT/CA2000/000030
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French (fr)
Inventor
Robert J. Lambert
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Certicom Corp.
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
    • G06F7/724Finite field arithmetic
    • G06F7/725Finite field arithmetic over elliptic curves
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07363Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
    • H04L9/002Countermeasures against attacks on cryptographic mechanisms
    • H04L9/003Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
    • H04L9/30Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H04L9/3006Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters
    • H04L9/3013Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy underlying computational problems or public-key parameters involving the discrete logarithm problem, e.g. ElGamal or Diffie-Hellman systems
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
    • H04L9/30Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy
    • H04L9/3066Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy involving algebraic varieties, e.g. elliptic or hyper-elliptic curves
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219Countermeasures against side channel or fault attacks
    • G06F2207/7223Randomisation as countermeasure against side channel attacks
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219Countermeasures against side channel or fault attacks
    • G06F2207/7223Randomisation as countermeasure against side channel attacks
    • G06F2207/7233Masking, e.g. (A**e)+r mod n
    • G06F2207/7242Exponent masking, i.e. key masking, e.g. A**(e+r) mod n; (k+r).P

Abstract

A method of masking a cryptographic operation using a secret value, comprising the steps of dividing the secret value into a plurality of parts; combining with each part a random value to derive a new part such that the new parts when combined are equivalent to the original secret value; and utilizing each of the individual parts in the operation.

Description

METHOD AND APPARATUS FOR MASKING CRYPTOGRAPHIC OPERATIONS

This invention relates to cryptographic systems and in particular to a method and apparatus for minimizing successful power analysis attacks on processors.

BACKGROUND OF THE INVENTION

Cryptographic systems generally owe their security to the fact that a particular piece of information is kept secret, without which it is almost impossible to break the scheme. This secret information must generally be stored within a secure boundary, making it difficult for an attacker to get at it directly however, various schemes or attacks have been attempted in order to obtain the secret information. Of particular risk are portable cryptographic tokens, including smart cards and the like. Of the more recent attacks performed on these particularly vulnerable devices are simple power analysis, differential power analysis, higher order differential power analysis and other related techniques. These technically sophisticated and extremely powerful analysis tools can be used by an attacker to extract secret keys from cryptographic devices. It has been shown that these attacks can be mounted quickly and can be implemented using readily available hardware. The amount of time required for these attacks depends on the type of attack and varies somewhat by device. For example it has been shown that a simple power attack (SPA) typically take a few seconds per card, while the differential power attacks (DP A) can take several hours.

Cryptographic operations are performed in a processor operating in a sequential manner by performing a sequence of fundamental operations, each of which generates a distinct timing pattern. Laborious but careful analysis of end-to-end power waveforms can decompose the order of these fundamental operations performed on each bit of a secret key and thus be, analyzed to find the entire secret key, compromising the system.

In the simple power analysis (SPA) attacks on smart cards and other secure tokens, an attacker directly measures the token's power consumption changes over time. The amount of power consumed varies depending on the executed microprocessor instructions. A large calculation such as elliptic curve (EC) additions in a loop and DES rounds, etc, may be identified, since the operations performed with a microprocessor vary significantly during different parts of these operations. By sampling the current and voltage at a higher rate, i.e., higher resolution, individual instructions can be differentiated.

The differential power analysis attack (DP A) is a more powerful attack than the SPA and is much more difficult to prevent. Primarily, the DPA uses statistical analysis and error correction techniques to extract information which may be correlated to secret keys, while the SPA attacks use primarily visual inspection to identify relevant power fluctuations. The DPA attack is performed in two steps. The first step is recording data that reflects the change in power consumed by the card during execution of cryptographic routines. In the second step, the collected data is statistically analyzed to extract information correlated to secret keys. A detailed analysis of these attacks is described in the paper entitled "Introduction to Differential Power Analysis and Related Attacks" by Paul Kocher et al.

Various techniques for addressing these power attacks have been attempted to date. These include hardware solutions such as providing well-filtered power supplies and physical shielding of processor elements. However, in the case of smart cards and other secure tokens, this is unfeasible. The DPA vulnerabilities result from transistor and circuit electrical behaviors that propagate to expose logic gates, microprocessor operation and ultimately the software implementations.

Accordingly, there is a need for a system for reducing the risk of a successful power analysis attacks and which is particularly applicable to current hardware environments.

SUMMARY OF THE INVENTION It is an object of this invention to provide a method for minimizing power analysis attacks on processors.

In accordance with this invention there is provided a method of masking a cryptographic operation using a secret value, comprising the steps of: (a) dividing said secret value into a plurality of parts; (b) combining with each part a random value to derive a new part such that the new parts when combined are equivalent to the original secret value; and (c) utilizing each of the individual parts in said operation. BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the preferred embodiments of the invention will become more apparent in the following detailed description in which reference is made to the appended drawings wherein: Figure 1 is a schematic diagram of a communication system; and

Figure 2 is a flow diagram illustrating an embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to figure 1, a communication system having at least a pair of corespondents is shown generally by numeral 10. It is assumed that the correspondents 12 and 14 incorporate cryptographic units 16 and 18 respectively. For convenience, the first correspondent will be referred to as the sender and the second correspondent will be referred to as the receiver. Generally, a plain text message is processed by the encryption unit of the sender and transmitted as cyphertext along a communication channel to the receiver where the encryption message is decrypted by the cryptographic unit 18 to recover the original message. The above system provides a typical environment for application of the invention as will be described below.

Referring to figure 2 a method for masking a private key or secret value used in a cryptographic operation is shown generally by numeral 200. The method comprises the steps of dividing a secret value into a plurality of parts and combining with each part a random value modulo n (where n is the number of points on the elliptic curve) to derive a new part such that the new parts are combined to be equivalent to the original secret value and utilizing each of the individual parts in the operation. Typically, the secret value is a private key, which is used to compute a public key, and more frequently used in signatures, decryption and possibly key exchange protocols, such as Diffie-Hellman key exchange.

For illustrative purposes, we will in the following discussion assume an EC scheme, where P is a point on the elliptic curve. The secret key d is normally combined with the point P to derive dP, the public key. However, the private key may also be used more frequently in various other cryptographic operations as described above. The cryptographic processor is generally initialized at manufacture time with the public key or secret value d. Initially, the value d may be divided into a number of parts, e.g. d = bι0 + b20.

In a first step the bi's are initialized to b = b10 and b2=b20 such that d = b10 + b20. These initial values of bi and b2 are stored instead of d. Alternatively the d value may also be stored if so desired, however in the case of a smart card where memory is limited this may not be desirable.

Typically when a computation using the value d is required. At a next step, a random number π is generated and the values bl and b2 are updated as follows:

Figure imgf000006_0001
b2 = b2 - π mod n

The updated values of bi and b2 are stored. Computation is then performed on the point P using the components bi and b as follows: dP mod n = b}P + b2P mod n where, P is a point on the curve which is a predefined parameter of the system. Thus assuming the value π is randomly generated for each session, then an attacker is unlikely to observe a predictable power signature.

In a typical application of the present invention a signature component s has the form:- s = ae + k (mod n) where: k is a random integer selected as a short term private or session key; R = kP is the corresponding short term public key; r=Rx x component of R a is the long term private key of the sender; Q = aP is the senders corresponding public key; e is a secure hash, such as the SHA-1 hash function, of a message m and the short term public key R( or possibly a short message itself); and n is the order of the curve.

The sender sends to the recipient a message including m, s, and r and the signature is verified by computing the value R, =: (sP-eQ) which should correspond to R. If the computed values correspond then the signature is verified. Both the secret keys in the above example may be masked using the method of the present invention. Specifically referring back to the above example, calculation of the product ae may reveal some information on some platforms in some environments. To minimise this, the present invention is applied. The product ae is computed as ae = (bo + bι)e for (bo + bi) =a; where b0, bj sum to a. The components b0 , bi are updated periodically as described above. This updating of the components can be made on every new signature operation.

In the above embodiments the secret value was divided into two components b0 , bi, however this may be generalized to a plurality of components b0....bn-ι. Furthermore the above signature scheme is used for illustrative purposes and other schemes and operations may equally well be applied using the present invention. Although the invention has been described with reference to certain specific embodiments, various modifications thereof will be apparent to those skilled in the art without departing from the spirit and scope of the invention as outlined in the claims appended hereto.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A method of masking a cryptographic operation using a secret value, comprising the steps of:
(d) dividing said secret value into a plurality of parts;
(e) combining with each part a random value to derive a new part such that the new parts when combined are equivalent to the original secret value; and
(f) utilizing each of the individual parts in said operation.
2. A method as defined in claim 1, including generating a plurality of random values.
3. A method as defined in claim 1, said operation being performed in an additive group.
4. A method as defined in claim 1, said operation being performed in a muliphcative group.
5. An article of manufacture comprising:
(a) a computer usable medium having computer readable program code embodied therein for masking a cryptographic operation using a secret value, the computer readable program code in said article of manufacture comprising;
(b) computer readable program code configured to cause a computer to divide said secret value into a plurality of parts;
(c) computer readable program code configured to cause a computer to combine with each part a random value to derive a new part such that the new parts when combined are equivalent to the original secret value; and
(d) computer readable program code configured to cause a computer to utilize each of the individual parts in said operation.
PCT/CA2000/000030 1999-01-15 2000-01-14 Method and apparatus for masking cryptographic operations WO2000042733A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CA2,259,089 1999-01-15
CA 2259089 CA2259089C (en) 1999-01-15 1999-01-15 Method and apparatus for masking cryptographic operations

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US09900959 US7092523B2 (en) 1999-01-11 2001-07-10 Method and apparatus for minimizing differential power attacks on processors
US10119803 US7599491B2 (en) 1999-01-11 2002-04-11 Method for strengthening the implementation of ECDSA against power analysis
US11483553 US8666070B2 (en) 1999-01-11 2006-07-11 Method and apparatus for minimizing differential power attacks on processors
US12495429 US8280048B2 (en) 1999-01-11 2009-06-30 Method for strengthening the implementation of ECDSA against power analysis
US12837268 US8666063B2 (en) 1999-01-11 2010-07-15 Method and apparatus for minimizing differential power attacks on processors
US13619557 US8621239B2 (en) 1999-01-11 2012-09-14 Method for strengthening the implementation of ECDSA against power analysis
US13621021 US8660264B2 (en) 1999-01-11 2012-09-15 Method and apparatus for minimizing differential power attacks on processors

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US09900959 Continuation-In-Part US7092523B2 (en) 1999-01-11 2001-07-10 Method and apparatus for minimizing differential power attacks on processors

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002008865A2 (en) * 2000-07-24 2002-01-31 David Chaum Transparent-coin electronic money system
WO2003098429A3 (en) * 2002-05-16 2004-07-15 Giesecke & Devrient Gmbh Modular inversion that is protected against espionage
EP1646976A2 (en) * 2003-06-04 2006-04-19 Mastercard International, Inc. Customer authentication in e-commerce transactions
EP1865471A2 (en) * 2002-02-28 2007-12-12 Mastercard Europe SPRL Authentication arrangement and method for use with financial transactions
US7599491B2 (en) 1999-01-11 2009-10-06 Certicom Corp. Method for strengthening the implementation of ECDSA against power analysis
US8204232B2 (en) 2005-01-18 2012-06-19 Certicom Corp. Accelerated verification of digital signatures and public keys
US8467535B2 (en) 2005-01-18 2013-06-18 Certicom Corp. Accelerated verification of digital signatures and public keys
US8660264B2 (en) 1999-01-11 2014-02-25 Certicom Corp. Method and apparatus for minimizing differential power attacks on processors
US8745376B2 (en) 2011-10-14 2014-06-03 Certicom Corp. Verifying implicit certificates and digital signatures
US8909557B2 (en) 2002-02-28 2014-12-09 Mastercard International Incorporated Authentication arrangement and method for use with financial transaction
US9123316B2 (en) 2010-12-27 2015-09-01 Microsoft Technology Licensing, Llc Interactive content creation

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WO2008106792A1 (en) * 2007-03-06 2008-09-12 Research In Motion Limited Methods and apparatus for performing an elliptic curve scalar multiplication operation using splitting
US8160245B2 (en) 2007-03-07 2012-04-17 Research In Motion Limited Methods and apparatus for performing an elliptic curve scalar multiplication operation using splitting
US8027466B2 (en) 2007-03-07 2011-09-27 Research In Motion Limited Power analysis attack countermeasure for the ECDSA

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Patent Citations (2)

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WO1998052319A1 (en) * 1997-05-12 1998-11-19 Yeda Research And Development Co. Ltd. Improved method and apparatus for protecting public key schemes from timing and fault attacks

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8666063B2 (en) 1999-01-11 2014-03-04 Certicom Corp. Method and apparatus for minimizing differential power attacks on processors
US8660264B2 (en) 1999-01-11 2014-02-25 Certicom Corp. Method and apparatus for minimizing differential power attacks on processors
US8621239B2 (en) 1999-01-11 2013-12-31 Certicom Corp. Method for strengthening the implementation of ECDSA against power analysis
US8280048B2 (en) 1999-01-11 2012-10-02 Certicom Corp. Method for strengthening the implementation of ECDSA against power analysis
US7599491B2 (en) 1999-01-11 2009-10-06 Certicom Corp. Method for strengthening the implementation of ECDSA against power analysis
US8666070B2 (en) 1999-01-11 2014-03-04 Certicom Corp. Method and apparatus for minimizing differential power attacks on processors
WO2002008865A2 (en) * 2000-07-24 2002-01-31 David Chaum Transparent-coin electronic money system
WO2002008865A3 (en) * 2000-07-24 2002-06-13 David Chaum Transparent-coin electronic money system
EP1865471A3 (en) * 2002-02-28 2008-03-05 Mastercard Europe SPRL Authentication arrangement and method for use with financial transactions
EP1850297A3 (en) * 2002-02-28 2008-03-05 Mastercard Europe SPRL Authentication arrangement and method for use with financial transactions
EP1865471A2 (en) * 2002-02-28 2007-12-12 Mastercard Europe SPRL Authentication arrangement and method for use with financial transactions
EP2309465A1 (en) * 2002-02-28 2011-04-13 Mastercard Europe SPRL Authentication arrangement and method for use with financial transactions
US8909557B2 (en) 2002-02-28 2014-12-09 Mastercard International Incorporated Authentication arrangement and method for use with financial transaction
US7474748B2 (en) 2002-05-16 2009-01-06 Giesecke & Devrient Gmbh Modular inversion that is protected against espionage
JP2005532715A (en) * 2002-05-16 2005-10-27 ギーゼッケ ウント デフリエント ゲーエムベーハーGiesecke & Devrient GmbH Conversely method calculation to be protected against the spying
JP4717437B2 (en) * 2002-05-16 2011-07-06 ギーゼッケ ウント デフリエント ゲーエムベーハーGiesecke & Devrient GmbH Conversely method calculation to be protected against the spying
WO2003098429A3 (en) * 2002-05-16 2004-07-15 Giesecke & Devrient Gmbh Modular inversion that is protected against espionage
EP1646976A2 (en) * 2003-06-04 2006-04-19 Mastercard International, Inc. Customer authentication in e-commerce transactions
EP1646976A4 (en) * 2003-06-04 2008-02-27 Mastercard International Inc Customer authentication in e-commerce transactions
US8204232B2 (en) 2005-01-18 2012-06-19 Certicom Corp. Accelerated verification of digital signatures and public keys
US8467535B2 (en) 2005-01-18 2013-06-18 Certicom Corp. Accelerated verification of digital signatures and public keys
US8788827B2 (en) 2005-01-18 2014-07-22 Certicom Corp. Accelerated verification of digital signatures and public keys
US8806197B2 (en) 2005-01-18 2014-08-12 Certicom Corp. Accelerated verification of digital signatures and public keys
US9123316B2 (en) 2010-12-27 2015-09-01 Microsoft Technology Licensing, Llc Interactive content creation
US9529566B2 (en) 2010-12-27 2016-12-27 Microsoft Technology Licensing, Llc Interactive content creation
US8745376B2 (en) 2011-10-14 2014-06-03 Certicom Corp. Verifying implicit certificates and digital signatures

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CA2259089A1 (en) 2000-07-15 application

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