US8507987B2 - Radio frequency device and method for fabricating the same - Google Patents

Radio frequency device and method for fabricating the same Download PDF

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US8507987B2
US8507987B2 US12/563,434 US56343409A US8507987B2 US 8507987 B2 US8507987 B2 US 8507987B2 US 56343409 A US56343409 A US 56343409A US 8507987 B2 US8507987 B2 US 8507987B2
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well
gate
radio frequency
frequency device
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Sheng-Yi Huang
Cheng-Chou Hung
Tzung-Lin Li
Chin-Lan Tseng
Victor-Chiang Liang
Chih-Yu Tseng
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United Microelectronics Corp
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United Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Definitions

  • the present invention generally relates to a radio frequency (RF) device and particularly to a radio frequency device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage.
  • RF radio frequency
  • a conventional high-voltage radio frequency device as illustrated in FIG. 1 primarily includes a semiconductor substrate 100 , an n-type doped well 102 , a p-type doped region 104 , a p-type buried doped region 106 , a gate 108 , an n-type source region 110 and an n-type drain region 112 .
  • the gate 108 includes a gate electrode and a gate dielectric layer (not labeled).
  • the n-type doped well 102 is formed in a surface of the semiconductor substrate 100 .
  • the buried doped region 106 is formed in the surface of the semiconductor substrate 100 and adjacent to the n-type doped well 102 .
  • the gate 108 is directly formed on the semiconductor substrate 100 and crossing over an interface of the n-type doped well 102 and the buried doped region 106 .
  • the n-type source region 110 is formed on a surface of the buried doped region 106 and at a side of the gate 108 .
  • the n-type source region 110 and the n-type doped well 102 are isolated from each other by the buried doped region 106 .
  • the p-type doped region 104 is formed on the surface of the buried doped region 106 and at a side of the n-type source region 110 far away from the gate 108 .
  • the buried doped region 104 can be connected or disconnected to the n-type source region 110 .
  • the n-type drain region 112 is formed in a surface of the n-type doped well 102 and at another side of the gate 108 .
  • the above-mentioned high-voltage radio frequency device can effectively improve the output impedance and breakdown voltage, since an area occupied by the gate is excessively large, it could not effectively improve frequency response.
  • a radio frequency device in accordance with an embodiment of the present invention includes a substrate, a gate of first type formed over the substrate, a dummy gate of first type formed on the substrate, a doped region of first type, a source region of first type and a drain region of first type.
  • the substrate includes a well of first type and a well of second type.
  • the well of second type is adjacent to the well of first type.
  • the gate of first type is formed over the well of second type.
  • the dummy gate of first type is formed over the well of first type.
  • the drain region of first type is formed in the well of first type and adjacent to the dummy gate of the first type.
  • the source region of first type is formed in the well of second type and adjacent to the gate of first type.
  • the doped region of first type is formed in the well of first type and adjacent to the well of second type.
  • a radio frequency device in accordance with another embodiment of the present invention includes a substrate, a gate of first type formed over the substrate, multiple dummy gates formed over the substrate, multiple doped regions, a source region of first type and a drain region of first type.
  • the substrate includes a well of first type and a well of second type.
  • the well of second type is adjacent to the well of first well.
  • the gate of first type is formed over the well of second type.
  • the dummy gates are formed over the well of first type.
  • the drain region of first type is formed in the well of first type and adjacent to one of the dummy gates far away from the gate of first type.
  • the source region of first type is formed in the well of second type and adjacent to the gate of first type.
  • the doped regions are formed in the well of first type and between the source region of first type and the drain region of first type.
  • a method for fabricating a radio frequency device in accordance with an embodiment of the present invention includes: providing a substrate including a well of first type and a well of second type therein, wherein the well of first type and the well of second type are formed adjacent to each other; and forming a dummy gate of first type over the well of first type, and a gate of first type over the well of second type.
  • a method for fabricating a radio frequency device in accordance with another embodiment of the present invention includes: providing a substrate including a well of first type and a well of second type therein, wherein the well of first type and the well of second type are formed adjacent to each other; and forming a plurality of dummy gates over the well of first type, and a gate of first type over the well of second type.
  • the dummy gate(s) is/are simultaneously formed with the gate in the same process.
  • a material of the dummy gate(s) can be poly-silicon or metal, but not limited to these examples.
  • a process for fabricating the dummy gate(s) can be chemical vapor deposition, metal sputtering, electroplating or other suitable process.
  • the radio frequency device can be n-type metal-oxide-semiconductor (MOS) or p-type MOS.
  • MOS metal-oxide-semiconductor
  • the first type is n-type and the second type is p-type.
  • the radio frequency device is p-type MOS
  • the first type is p-type and the second type is n-type.
  • FIG. 1 is a schematic sectional view of a conventional high-voltage radio frequency device associated with the prior art.
  • FIG. 2 is a schematic top view of a radio frequency device in accordance with a preferred embodiment of the present invention.
  • FIG. 3 illustrates a schematic sectional view of the radio frequency device taken along line A-A in FIG. 2 .
  • FIG. 4 is a schematic top view of a radio frequency device in accordance with another embodiment of the present invention.
  • FIG. 5 illustrates a schematic sectional view of the radio frequency device taken along line B-B in FIG. 4 .
  • FIG. 6 is a schematic top view of a radio frequency device in accordance with still another embodiment of the present invention.
  • FIG. 7 illustrates a schematic sectional view of the radio frequency device taken along line C-C in FIG. 6 .
  • FIGS. 8A-8D are flowcharts of a method for fabricating a radio frequency device in accordance with an embodiment of the present invention.
  • FIGS. 9A-9D are flowcharts of a method for fabricating a radio frequency device in accordance with another embodiment of the present invention.
  • FIG. 2 is a schematic top view of a radio frequency device in accordance with a preferred embodiment of the present invention.
  • the radio frequency device includes a substrate 200 , a gate of first type 206 , a dummy gate of first type 208 , a doped region of first type 210 , a source region of first type 212 and a drain region of first type 214 .
  • the substrate 200 includes a well of first type 202 and a well of second type 204 .
  • the well of second type 204 is adjacent to the well of first type 202 .
  • the gate of first type 206 includes a gate electrode and a gate dielectric layer (not labeled).
  • the dummy gate of first type 208 includes a dummy gate electrode and a gate dielectric layer (not labeled).
  • the gate of first type 206 is formed over the well of second type 204 .
  • the dummy gate of first type 208 is formed over the well of first type 202 .
  • the drain region of first type 214 is formed in the well of first type 202 and adjacent to the dummy gate of first type 208 .
  • the source region of first type 212 is formed in the well of second type 204 and adjacent to the gate of first type 206 .
  • the doped region of first type 210 is formed in the well of first type 202 and adjacent to the well of second type 204 .
  • the first type for example is n-type, and the second type for example is p-type.
  • a width of the doped region of first type 210 for example is greater than 160 nanometers (nm)
  • a width of the dummy gate of first type 208 for example is greater than 90 nm.
  • the radio frequency device for example further includes a plurality of low-doped drain (LDD) structures 209 .
  • the LDD structures 209 are formed in the substrate 200 and at two sides of the gate of first type 206 and the dummy gate of first type 208 respectively.
  • FIG. 4 is a schematic top view of a radio frequency device in accordance with another embodiment of the present invention.
  • the radio frequency device includes a substrate 200 , a gate of first type 206 , a plurality of dummy gates 208 , a plurality of doped regions 210 , 218 , a source region of first type 212 and a drain region of first type 214 .
  • the substrate 200 includes a well of first type 202 and a well of second type 204 .
  • the well of second type 204 is adjacent to the well of first type 202 .
  • the gate of first type 206 includes a gate electrode and a gate dielectric layer (not labeled), each of the dummy gates 208 includes a dummy gate electrode and a gate dielectric layer (not labeled).
  • the gate of first type 206 is formed over the well of second type 204 and between the source region of first type 212 and the doped region 210 .
  • the dummy gates 208 are formed over the well of first type 202 and between the drain region of first type 214 and the doped region 210 .
  • the doped regions 218 are formed in the well of first type 202 and between the respective dummy gates 208 .
  • the drain region of first type 214 is formed in the well of first type 202 at a side far away from the well of second type 204 .
  • the source region of first type 212 is formed in the well of second type 204 at a side far away from the well of first type 202 .
  • the doped region 210 is formed in the well of first type 202 at a side adjacent to the well of second type 204 .
  • the first type for example is n-type
  • the second type for example is p-type.
  • the doped regions 210 , 218 for example all are n-type doped regions or p-type doped regions.
  • the dummy gates 208 can be n-type dummy gates, p-type dummy gates or combinations thereof.
  • a width of each of the doped regions 210 , 218 for example is greater than 160 nm
  • a width of each of the dummy gates 208 for example is greater than 90 nm.
  • the radio frequency device for example further includes a plurality of LDD structures 209 .
  • the LDD structures 209 are formed in the substrate 200 and at two sides of the gate of first type 206 and the dummy gates 208 .
  • FIG. 6 is a schematic top view of a radio frequency device in accordance with still another embodiment of the present invention.
  • the radio frequency device includes a substrate 200 , a gate of first type 206 , a plurality of dummy gates 208 , a plurality of doped regions 210 , 216 , a source region of first type 212 and a drain region of first type 214 .
  • the substrate 200 includes a well of first type 202 and a well of second type 204 .
  • the well of second type 204 is adjacent to the well of first type 202 .
  • the gate of first type 206 includes a gate electrode and a gate dielectric layer (not labeled), each of the dummy gates 208 includes a dummy gate electrode and a gate dielectric layer (not labeled).
  • the gate of first type 206 is formed over the well of second type 204 and between the source region of first type 212 and the doped region 210 .
  • the dummy gates 208 are formed over the well of first type 202 and between the drain region of first type 214 and the doped region 210 .
  • the doped regions 216 are formed in the well of first type 202 and between the respective dummy gates 208 .
  • the drain region of first type 214 is formed in the well of first type 202 at a side far away from the well of second type 204 .
  • the source region of first type 212 is formed in the well of second type 204 at a side far away from the well of first type 202 .
  • the doped region 210 is formed in the well of first type 202 at a side adjacent to well of second type 204 .
  • the first type for example is n-type
  • the second type for example is p-type.
  • the doped regions 210 , 216 are different types of doped regions.
  • the doped region 210 is n-type doped region
  • the doped regions 216 are p-type doped regions; or the doped region 210 is p-type doped region, the doped regions 216 are n-type doped regions.
  • the dummy gates 208 can be n-type dummy gates, p-type dummy gates or combinations thereof.
  • a width of each of the doped regions 210 , 216 for example is greater than 160 nm
  • a width of each of the dummy gates 208 for example is greater than 90 nm.
  • the radio frequency device for example further includes a plurality of LDD structures 209 .
  • the LDD structures 209 are formed in the substrate 200 and at two sides of the gate of first type 206 and the dummy gates 208 .
  • FIGS. 8A through 8D shows flow charts of the method for fabricating a radio frequency device.
  • a substrate 200 is provided.
  • the substrate 200 includes a well of first type 202 and a well of second type 204 .
  • the well of first type 202 is adjacent to the well of second type 204 .
  • a dummy gate of first type 208 is formed over the well of first type 202
  • a gate of first type 206 is formed over the well of second type 204 .
  • an ion implantation process 220 is performed using the gate of first type 206 and the dummy gate of first type 208 as a mast to form a plurality of LDD structures 209 in the substrate 200 .
  • the LDD structures 209 are formed at two sides of the gate of first type 206 and the dummy gate of first type 208 respectively.
  • another ion implantation process 230 is performed to form a drain region of first type 214 in the well of first type 202 and adjacent to the dummy gate of first type 208 , to form a source region of first type 212 in the well of second type 204 and adjacent to the gate of first type 206 , and to form a doped region of first type 210 in the well of first type 202 and adjacent to the well of second type 204 .
  • the doped region of first type 210 is formed between the gate of first type 206 and the dummy gate of first type 208 .
  • spacers may be formed on the sidewalls of the gate of first type 206 and the dummy gate of first type 208 . Then a dielectric layer is formed over the substrate 200 and the gate of first type 206 and the dummy gate of first type 208 .
  • the first type for example is n-type
  • the second type for example is p-type.
  • a width of the doped region of first type 210 for example is greater than 160 nm
  • a width of the dummy gate of first type 208 for example is greater than 90 nm.
  • FIGS. 9A through 9D shows flow charts of the method for fabricating a radio frequency device.
  • a substrate 200 is provided.
  • the substrate 200 includes a well of first type 202 and a well of second type 204 .
  • the well of first type 202 is adjacent to the well of second type 204 .
  • a plurality of dummy gates 208 are formed over the well of first type 202
  • a gate of first type 206 is formed over the well of second type 204 .
  • FIG. 9A firstly, a substrate 200 is provided.
  • the substrate 200 includes a well of first type 202 and a well of second type 204 .
  • the well of first type 202 is adjacent to the well of second type 204 .
  • a plurality of dummy gates 208 are formed over the well of first type 202
  • a gate of first type 206 is formed over the well of second type 204 .
  • an ion implantation process 220 is performed using the gate of first type 206 and the dummy gates 208 as a mask to form LDD structures 209 in the substrate 200 .
  • the LDD structures 209 are formed at two sides of the gate of first type 206 and the dummy gates 208 respectively.
  • another ion implantation process 230 is performed to form a drain region of first type 214 in the doped well of first type 202 and adjacent to the dummy gates 208 , to form a source region of first type 212 in the well of second type 204 and adjacent to the gate of first type 206 , and to form doped regions 210 , 218 in the well of first type 202 and adjacent to the well of second type 204 .
  • the doped region 210 is formed in the well of first type 202 and adjacent to the well 204 of second type.
  • the doped regions 218 are formed in the well of first type 202 and between the respective dummy gates 208 .
  • spacers may be formed on the sidewalls of the gate of first type 206 and the dummy gates 208 .
  • a dielectric layer is formed over the substrate 200 , the gate of first type 206 and the dummy gates 208 .
  • the first type for example is n-type
  • the second type for example is p-type.
  • a width of the doped region 210 for example is greater than 160 nm
  • a width of each of the dummy gates 208 for example is greater than 90 nm.
  • the dummy gate(s) is/are simultaneously formed together with the gate during the same process.
  • a material of the dummy gate(s) can be poly-silicon or metal, but not limited to these samples.
  • the process for fabricating the dummy gate(s) can be chemical vapor deposition, metal sputtering, electroplating or other suitable process.
  • the radio frequency device can be n-type metal-oxide-semiconductor (MOS) device or p-type MOS device.
  • MOS metal-oxide-semiconductor
  • the first type is n-type
  • the second type is p-type
  • the first type is p-type
  • the second type is n-type.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Manufacturing & Machinery (AREA)
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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A radio frequency (RF) device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage includes a substrate, a gate, at least a dummy gate, at least a doped region, a source region and a drain region. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type.

Description

BACKGROUND
1. Field of the Invention
The present invention generally relates to a radio frequency (RF) device and particularly to a radio frequency device that can achieve high frequency response while maintaining high output impedance and high breakdown voltage.
2. Description of the Related Art
In order to meet the increasing popularity of various wireless communication applications, demands for high-voltage radio frequency devices with high frequency response have correspondingly rapidly increased. Accordingly, with regard to the demands for high-voltage radio frequency devices, achieving high frequency response while maintaining high output impedance and high breakdown voltage is very important. Although conventional asymmetric high-voltage radio frequency devices can achieve high output impedance and high breakdown voltage, the frequency response could not be effectively improved.
Referring to FIG. 1, a conventional high-voltage radio frequency device as illustrated in FIG. 1 primarily includes a semiconductor substrate 100, an n-type doped well 102, a p-type doped region 104, a p-type buried doped region 106, a gate 108, an n-type source region 110 and an n-type drain region 112. The gate 108 includes a gate electrode and a gate dielectric layer (not labeled). The n-type doped well 102 is formed in a surface of the semiconductor substrate 100. The buried doped region 106 is formed in the surface of the semiconductor substrate 100 and adjacent to the n-type doped well 102. The gate 108 is directly formed on the semiconductor substrate 100 and crossing over an interface of the n-type doped well 102 and the buried doped region 106. The n-type source region 110 is formed on a surface of the buried doped region 106 and at a side of the gate 108. The n-type source region 110 and the n-type doped well 102 are isolated from each other by the buried doped region 106. The p-type doped region 104 is formed on the surface of the buried doped region 106 and at a side of the n-type source region 110 far away from the gate 108. The buried doped region 104 can be connected or disconnected to the n-type source region 110. The n-type drain region 112 is formed in a surface of the n-type doped well 102 and at another side of the gate 108.
However, although the above-mentioned high-voltage radio frequency device can effectively improve the output impedance and breakdown voltage, since an area occupied by the gate is excessively large, it could not effectively improve frequency response.
BRIEF SUMMARY
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
A radio frequency device in accordance with an embodiment of the present invention includes a substrate, a gate of first type formed over the substrate, a dummy gate of first type formed on the substrate, a doped region of first type, a source region of first type and a drain region of first type. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first type. The gate of first type is formed over the well of second type. The dummy gate of first type is formed over the well of first type. The drain region of first type is formed in the well of first type and adjacent to the dummy gate of the first type. The source region of first type is formed in the well of second type and adjacent to the gate of first type. The doped region of first type is formed in the well of first type and adjacent to the well of second type.
A radio frequency device in accordance with another embodiment of the present invention includes a substrate, a gate of first type formed over the substrate, multiple dummy gates formed over the substrate, multiple doped regions, a source region of first type and a drain region of first type. The substrate includes a well of first type and a well of second type. The well of second type is adjacent to the well of first well. The gate of first type is formed over the well of second type. The dummy gates are formed over the well of first type. The drain region of first type is formed in the well of first type and adjacent to one of the dummy gates far away from the gate of first type. The source region of first type is formed in the well of second type and adjacent to the gate of first type. The doped regions are formed in the well of first type and between the source region of first type and the drain region of first type.
A method for fabricating a radio frequency device in accordance with an embodiment of the present invention includes: providing a substrate including a well of first type and a well of second type therein, wherein the well of first type and the well of second type are formed adjacent to each other; and forming a dummy gate of first type over the well of first type, and a gate of first type over the well of second type.
A method for fabricating a radio frequency device in accordance with another embodiment of the present invention includes: providing a substrate including a well of first type and a well of second type therein, wherein the well of first type and the well of second type are formed adjacent to each other; and forming a plurality of dummy gates over the well of first type, and a gate of first type over the well of second type.
In the respective above-mentioned embodiments of the present invention, the dummy gate(s) is/are simultaneously formed with the gate in the same process. A material of the dummy gate(s) can be poly-silicon or metal, but not limited to these examples. A process for fabricating the dummy gate(s) can be chemical vapor deposition, metal sputtering, electroplating or other suitable process.
In the respective above-mentioned embodiments of the present invention, the radio frequency device can be n-type metal-oxide-semiconductor (MOS) or p-type MOS. When the radio frequency device is n-type MOS, the first type is n-type and the second type is p-type. Whereas when the radio frequency device is p-type MOS, the first type is p-type and the second type is n-type.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIG. 1 is a schematic sectional view of a conventional high-voltage radio frequency device associated with the prior art.
FIG. 2 is a schematic top view of a radio frequency device in accordance with a preferred embodiment of the present invention.
FIG. 3 illustrates a schematic sectional view of the radio frequency device taken along line A-A in FIG. 2.
FIG. 4 is a schematic top view of a radio frequency device in accordance with another embodiment of the present invention.
FIG. 5 illustrates a schematic sectional view of the radio frequency device taken along line B-B in FIG. 4.
FIG. 6 is a schematic top view of a radio frequency device in accordance with still another embodiment of the present invention.
FIG. 7 illustrates a schematic sectional view of the radio frequency device taken along line C-C in FIG. 6.
FIGS. 8A-8D are flowcharts of a method for fabricating a radio frequency device in accordance with an embodiment of the present invention.
FIGS. 9A-9D are flowcharts of a method for fabricating a radio frequency device in accordance with another embodiment of the present invention.
 DETAILED DESCRIPTION
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
FIG. 2 is a schematic top view of a radio frequency device in accordance with a preferred embodiment of the present invention.
Referring to FIG. 3, FIG. 3 illustrating a schematic sectional view of the radio frequency device taken along line A-A in FIG. 2. As illustrated in FIGS. 2 and 3, the radio frequency device includes a substrate 200, a gate of first type 206, a dummy gate of first type 208, a doped region of first type 210, a source region of first type 212 and a drain region of first type 214. The substrate 200 includes a well of first type 202 and a well of second type 204. The well of second type 204 is adjacent to the well of first type 202. The gate of first type 206 includes a gate electrode and a gate dielectric layer (not labeled). The dummy gate of first type 208 includes a dummy gate electrode and a gate dielectric layer (not labeled).
The gate of first type 206 is formed over the well of second type 204. The dummy gate of first type 208 is formed over the well of first type 202. The drain region of first type 214 is formed in the well of first type 202 and adjacent to the dummy gate of first type 208. The source region of first type 212 is formed in the well of second type 204 and adjacent to the gate of first type 206. The doped region of first type 210 is formed in the well of first type 202 and adjacent to the well of second type 204.
The first type for example is n-type, and the second type for example is p-type. Moreover, a width of the doped region of first type 210 for example is greater than 160 nanometers (nm), and a width of the dummy gate of first type 208 for example is greater than 90 nm. In addition, the radio frequency device for example further includes a plurality of low-doped drain (LDD) structures 209. The LDD structures 209 are formed in the substrate 200 and at two sides of the gate of first type 206 and the dummy gate of first type 208 respectively.
FIG. 4 is a schematic top view of a radio frequency device in accordance with another embodiment of the present invention.
Referring to FIG. 5, FIG. 5 illustrating a schematic sectional view of the radio frequency device taken along line B-B in FIG. 4. As illustrated in FIGS. 4 and 5, the radio frequency device includes a substrate 200, a gate of first type 206, a plurality of dummy gates 208, a plurality of doped regions 210, 218, a source region of first type 212 and a drain region of first type 214. The substrate 200 includes a well of first type 202 and a well of second type 204. The well of second type 204 is adjacent to the well of first type 202. The gate of first type 206 includes a gate electrode and a gate dielectric layer (not labeled), each of the dummy gates 208 includes a dummy gate electrode and a gate dielectric layer (not labeled).
The gate of first type 206 is formed over the well of second type 204 and between the source region of first type 212 and the doped region 210. The dummy gates 208 are formed over the well of first type 202 and between the drain region of first type 214 and the doped region 210. The doped regions 218 are formed in the well of first type 202 and between the respective dummy gates 208. The drain region of first type 214 is formed in the well of first type 202 at a side far away from the well of second type 204. The source region of first type 212 is formed in the well of second type 204 at a side far away from the well of first type 202. The doped region 210 is formed in the well of first type 202 at a side adjacent to the well of second type 204.
The first type for example is n-type, and the second type for example is p-type. The doped regions 210, 218 for example all are n-type doped regions or p-type doped regions. The dummy gates 208 can be n-type dummy gates, p-type dummy gates or combinations thereof. Moreover, a width of each of the doped regions 210, 218 for example is greater than 160 nm, and a width of each of the dummy gates 208 for example is greater than 90 nm. In addition, the radio frequency device for example further includes a plurality of LDD structures 209. The LDD structures 209 are formed in the substrate 200 and at two sides of the gate of first type 206 and the dummy gates 208.
FIG. 6 is a schematic top view of a radio frequency device in accordance with still another embodiment of the present invention.
Referring to FIG. 7, FIG. 7 illustrating a schematic sectional view of the radio frequency device taken along line C-C in FIG. 6. As illustrated in FIGS. 6 and 7, the radio frequency device includes a substrate 200, a gate of first type 206, a plurality of dummy gates 208, a plurality of doped regions 210, 216, a source region of first type 212 and a drain region of first type 214. The substrate 200 includes a well of first type 202 and a well of second type 204. The well of second type 204 is adjacent to the well of first type 202. The gate of first type 206 includes a gate electrode and a gate dielectric layer (not labeled), each of the dummy gates 208 includes a dummy gate electrode and a gate dielectric layer (not labeled).
The gate of first type 206 is formed over the well of second type 204 and between the source region of first type 212 and the doped region 210. The dummy gates 208 are formed over the well of first type 202 and between the drain region of first type 214 and the doped region 210. The doped regions 216 are formed in the well of first type 202 and between the respective dummy gates 208. The drain region of first type 214 is formed in the well of first type 202 at a side far away from the well of second type 204. The source region of first type 212 is formed in the well of second type 204 at a side far away from the well of first type 202. The doped region 210 is formed in the well of first type 202 at a side adjacent to well of second type 204.
The first type for example is n-type, and the second type for example is p-type. The doped regions 210, 216 are different types of doped regions. For example, the doped region 210 is n-type doped region, the doped regions 216 are p-type doped regions; or the doped region 210 is p-type doped region, the doped regions 216 are n-type doped regions. The dummy gates 208 can be n-type dummy gates, p-type dummy gates or combinations thereof. Moreover, a width of each of the doped regions 210, 216 for example is greater than 160 nm, and a width of each of the dummy gates 208 for example is greater than 90 nm. In addition, the radio frequency device for example further includes a plurality of LDD structures 209. The LDD structures 209 are formed in the substrate 200 and at two sides of the gate of first type 206 and the dummy gates 208.
A method for fabricating a radio frequency device in accordance with an embodiment of the present invention will be described below in detailed. FIGS. 8A through 8D shows flow charts of the method for fabricating a radio frequency device. Referring to FIG. 8A firstly, a substrate 200 is provided. The substrate 200 includes a well of first type 202 and a well of second type 204. The well of first type 202 is adjacent to the well of second type 204. Subsequently, referring to FIG. 8B, a dummy gate of first type 208 is formed over the well of first type 202, and a gate of first type 206 is formed over the well of second type 204. Then, referring to FIG. 8C, an ion implantation process 220 is performed using the gate of first type 206 and the dummy gate of first type 208 as a mast to form a plurality of LDD structures 209 in the substrate 200. The LDD structures 209 are formed at two sides of the gate of first type 206 and the dummy gate of first type 208 respectively. After that, referring to FIG. 8D, another ion implantation process 230 is performed to form a drain region of first type 214 in the well of first type 202 and adjacent to the dummy gate of first type 208, to form a source region of first type 212 in the well of second type 204 and adjacent to the gate of first type 206, and to form a doped region of first type 210 in the well of first type 202 and adjacent to the well of second type 204. The doped region of first type 210 is formed between the gate of first type 206 and the dummy gate of first type 208.
In one embodiment, prior to performing the ion implantation process 230, spacers may be formed on the sidewalls of the gate of first type 206 and the dummy gate of first type 208. Then a dielectric layer is formed over the substrate 200 and the gate of first type 206 and the dummy gate of first type 208. The first type for example is n-type, and the second type for example is p-type. Moreover, a width of the doped region of first type 210 for example is greater than 160 nm, and a width of the dummy gate of first type 208 for example is greater than 90 nm.
A method for fabricating a radio frequency device in accordance with another embodiment will be described below in detailed. FIGS. 9A through 9D shows flow charts of the method for fabricating a radio frequency device. Referring to FIG. 9A firstly, a substrate 200 is provided. The substrate 200 includes a well of first type 202 and a well of second type 204. The well of first type 202 is adjacent to the well of second type 204. Next, referring to FIG. 9B, a plurality of dummy gates 208 are formed over the well of first type 202, and a gate of first type 206 is formed over the well of second type 204. Then, referring to FIG. 9C, an ion implantation process 220 is performed using the gate of first type 206 and the dummy gates 208 as a mask to form LDD structures 209 in the substrate 200. The LDD structures 209 are formed at two sides of the gate of first type 206 and the dummy gates 208 respectively. After that, referring to FIG. 9D, another ion implantation process 230 is performed to form a drain region of first type 214 in the doped well of first type 202 and adjacent to the dummy gates 208, to form a source region of first type 212 in the well of second type 204 and adjacent to the gate of first type 206, and to form doped regions 210, 218 in the well of first type 202 and adjacent to the well of second type 204. The doped region 210 is formed in the well of first type 202 and adjacent to the well 204 of second type. The doped regions 218 are formed in the well of first type 202 and between the respective dummy gates 208.
In one embodiment, prior to performing the ion implantation process 230, spacers may be formed on the sidewalls of the gate of first type 206 and the dummy gates 208. Then, a dielectric layer is formed over the substrate 200, the gate of first type 206 and the dummy gates 208. The first type for example is n-type, and the second type for example is p-type. Moreover, a width of the doped region 210 for example is greater than 160 nm, and a width of each of the dummy gates 208 for example is greater than 90 nm.
In addition, in the respective above-mentioned embodiments of the present invention, the dummy gate(s) is/are simultaneously formed together with the gate during the same process. A material of the dummy gate(s) can be poly-silicon or metal, but not limited to these samples. The process for fabricating the dummy gate(s) can be chemical vapor deposition, metal sputtering, electroplating or other suitable process.
Moreover, in the respective above-mentioned embodiments of the present invention, the radio frequency device can be n-type metal-oxide-semiconductor (MOS) device or p-type MOS device. When the radio frequency device is an n-type MOS device, the first type is n-type, and the second type is p-type. Whereas, when the radio device is a p-type MOS device, the first type is p-type, and the second type is n-type.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (19)

What is claimed is:
1. A radio frequency device, comprising:
a substrate comprising a well of first type and a well of second type adjacent to the well of first type;
a dummy gate of first type formed over the well of first type;
a gate of first type formed over the well of second type;
a drain region of first type formed in the well of first type and adjacent to the dummy gate of first type;
a source region of first type formed in the well of second type and adjacent to the gate of first type; and
a doped region of first type formed only in the well of first type and adjacent to the well of second type, wherein the doped region of first type is not directly above the well of second type.
2. The radio frequency device as claimed in claim 1, wherein the doped region of first type is formed between the gate of first type and the dummy gate of first type.
3. The radio frequency device as claimed in claim 1, wherein the first type is an n-type and the second type is a p-type.
4. The radio frequency device as claimed in claim 1, further comprising LDD structures formed in the substrate at two sides of the gate of first type and the dummy gate of first type respectively.
5. The radio frequency device as claimed in claim 1, wherein a width of the doped region of first type is greater than 160 nm.
6. The radio frequency device as claimed in claim 1, wherein a width of the dummy gate of first type is greater than 90 nm.
7. A radio frequency device, comprising:
a substrate comprising a well of first type and a well of second type adjacent to the well of first type;
a plurality of dummy gates formed over the well of first type;
a gate of first type formed over the well of second type;
a drain region of first type formed in the well of first type and adjacent to one of the dummy gates far away from the gate of first type; and
a source region of first type formed in the well of second type and adjacent to the gate of first type.
8. The radio frequency device as claimed in claim 7, further comprising:
a plurality of doped regions formed in the well of first type and between the source region of first type and the drain region of first type.
9. The radio frequency device as claimed in claim 8, wherein the doped regions are formed at two sides of the dummy gates.
10. The radio frequency device as claimed in claim 8, wherein the doped regions are n-type, p-type or combinations thereof.
11. The radio frequency device as claimed in claim 7, wherein the dummy gates are n-type, p-type or combinations thereof.
12. The radio frequency device as claimed in claim 7, wherein the first type is an n-type and the second type is a p-type.
13. The radio frequency device as claimed in claim 7, further comprising LDD structures formed in the substrate at two sides of the gate of first type and the dummy gates respectively.
14. The radio frequency device as claimed in claim 8, wherein a width of each of the doped regions is greater than 160 nm.
15. The radio frequency device as claimed in claim 7, wherein a width of each of the dummy gates is greater than 90 nm.
16. A method for fabricating a radio frequency device, comprising:
providing a substrate comprising a well of first type and a well of second type adjacent to the well of first type;
forming a dummy gate of first type over the well of first type, and a gate of first type over the well of second type;
performing a first ion implantation process using the gate of first type and the dummy gate of first type as a mask to form LDD structures in the substrate at two sides of the gate of first type and the dummy gate of first type respectively; and
performing a second ion implantation process to form a drain region of first type in the well of first type and adjacent to the dummy gate of first type, a source region of first type in the well of second type and adjacent to the gate of first type, and a doped region of first type only in the well of first type and adjacent to the well of second type, wherein the doped region of first type is not directly above the well of second type.
17. The method for fabricating a radio frequency device as claimed in claim 16, wherein the doped region of first type is formed between the gate of first type and the dummy gate of first type.
18. A method for fabricating a radio frequency device, comprising:
providing a substrate comprising a well of first type and a well of second type adjacent to the well of first type;
forming a plurality of dummy gates over the well of first type, and a gate of first type over the well of second type;
performing a first ion implantation process using the gate of first type and the dummy gates as a mask to form LDD structures in the substrate at two sides of the gate of first type and the dummy gates respectively; and
performing a second ion implantation process to form a drain region of first type in the well of first type and adjacent to one of the dummy gates far away from the gate of first type, a source region of first type in the well of second type and adjacent to the gate of first type, and a plurality of doped regions in the well of first type and between the source region of first type and the drain region of first type.
19. The method for fabricating a radio frequency device as claimed in claim 18, wherein the doped regions are formed at two sides of the respective dummy gates.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9490360B2 (en) 2014-02-19 2016-11-08 United Microelectronics Corp. Semiconductor device and operating method thereof
US11101384B1 (en) 2020-09-07 2021-08-24 United Microelectronics Corp. Power semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122192A1 (en) * 2001-07-09 2003-07-03 United Microelectronics Corp. Low-voltage-triggered SOI-SCR device and associated ESD protection circuit
US20070290266A1 (en) * 2003-07-17 2007-12-20 Ming-Dou Ker Turn-on-efficient bipolar structures for on-chip esd protection
US7323740B2 (en) 2003-06-20 2008-01-29 Samsung Electronics Co., Ltd Single chip data processing device with embedded nonvolatile memory and method thereof
US20080203424A1 (en) * 2004-08-30 2008-08-28 Zi-Ping Chen Diode and applications thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030122192A1 (en) * 2001-07-09 2003-07-03 United Microelectronics Corp. Low-voltage-triggered SOI-SCR device and associated ESD protection circuit
US7323740B2 (en) 2003-06-20 2008-01-29 Samsung Electronics Co., Ltd Single chip data processing device with embedded nonvolatile memory and method thereof
US20070290266A1 (en) * 2003-07-17 2007-12-20 Ming-Dou Ker Turn-on-efficient bipolar structures for on-chip esd protection
US20080203424A1 (en) * 2004-08-30 2008-08-28 Zi-Ping Chen Diode and applications thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9490360B2 (en) 2014-02-19 2016-11-08 United Microelectronics Corp. Semiconductor device and operating method thereof
US11101384B1 (en) 2020-09-07 2021-08-24 United Microelectronics Corp. Power semiconductor device
US11637200B2 (en) 2020-09-07 2023-04-25 United Microelectronics Corp. Power semiconductor device

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