TWI462289B - Radio frequency device and method for fabricating the same - Google Patents
Radio frequency device and method for fabricating the same Download PDFInfo
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Description
本發明是關於一種射頻元件，尤指一種能達到高頻率響應，同時維持高輸出阻抗(Rs)及高崩潰電壓(breakdown voltage)的射頻元件。The present invention relates to a radio frequency component, and more particularly to a radio frequency component capable of achieving high frequency response while maintaining high output impedance (Rs) and high breakdown voltage.
為了因應各種無線通訊應用日益普及，對於具高頻率響應之高壓射頻元件的需求也快速增加。因此，對於高壓射頻元件之需求除了維持高輸出阻抗及高崩潰電壓之外，能同時達到高頻率響應是十分重要。習知作法之非對稱高壓射頻元件，雖能有高輸出阻抗及崩潰電壓，但不能有效提高頻率響應。In response to the increasing popularity of various wireless communication applications, the demand for high-voltage RF components with high frequency response has also increased rapidly. Therefore, in addition to maintaining high output impedance and high breakdown voltage, it is important to achieve high frequency response at the same time. The asymmetric high-voltage RF components of the conventional method can have high output impedance and breakdown voltage, but cannot effectively improve the frequency response.
請參照圖1，如圖1所示習知之高壓射頻元件主要包含有一半導體基底100、一N型態之井102、一P型態之摻雜區104、一P型態之埋入摻雜區106、一閘極108、一N型態之源極區110與一N型態之汲極區112。其中，閘極108包含有一閘極電極及一閘極介電層(未標示於圖中)。N型態之井102位於半導體基底100之表面。埋入摻雜區106位於半導體基底100之表面，且連接於N型態之井102。閘極108直接位於半導體基底100之上，且跨越N型態之井102與埋入摻雜區106之交接面。N型態之源極區110位於埋入摻雜區106之表面，且連接於閘極108之一側。N型態之源極區110與N型態之井102之間有埋入摻雜區106以隔離。P型態之摻雜區104位於埋入摻雜區106之表面，且位於N型態之源極區110之遠離閘極108之一側，其可連接於或不連接於N型態之源極區110。N型態之汲極區112位於N型態之井102之表面，且位於閘極108之另一側。Referring to FIG. 1, a conventional high voltage RF component as shown in FIG. 1 mainly includes a semiconductor substrate 100, an N-type well 102, a P-type doped region 104, and a P-type buried doped region. 106. A gate 108, an N-type source region 110 and an N-type drain region 112. The gate 108 includes a gate electrode and a gate dielectric layer (not shown). The N-type well 102 is located on the surface of the semiconductor substrate 100. The buried doped region 106 is located on the surface of the semiconductor substrate 100 and is connected to the N-type well 102. The gate 108 is directly over the semiconductor substrate 100 and spans the interface between the N-type well 102 and the buried doped region 106. The N-type source region 110 is located on the surface of the buried doping region 106 and is connected to one side of the gate 108. There is a buried doping region 106 between the N-type source region 110 and the N-type well 102 to isolate. The P-type doped region 104 is located on the surface of the buried doped region 106 and is located on the side of the N-type source region 110 away from the gate 108, which may or may not be connected to the source of the N-type state. Polar zone 110. The N-type drain region 112 is located on the surface of the N-type well 102 and is located on the other side of the gate 108.
上述習知之高壓射頻元件雖能有效提高輸出阻抗及崩潰電壓，但因閘極所佔面積過大，以致不能有效提高頻率響應。Although the above-mentioned high-voltage radio frequency component can effectively improve the output impedance and the breakdown voltage, the gate occupies an excessively large area, so that the frequency response cannot be effectively improved.
本發明的目的是提供一種改良的射頻元件以有效提高輸出阻抗及崩潰電壓，並兼顧能有效提高頻率響應。SUMMARY OF THE INVENTION It is an object of the present invention to provide an improved radio frequency component to effectively increase output impedance and breakdown voltage, and to achieve an effective increase in frequency response.
本發明係提供一種射頻元件，包含有一基底、一第一型態之閘極位於該基底之上、一第一型態之虛置閘極位於該基底之上、一第一型態之摻雜區、一第一型態之源極區與一第一型態之汲極區。基底包含一第一型態之井與一第二型態之井，且第二型態之井連接於第一型態之井。第一型態之閘極位於第二型態之井之上。第一型態之虛置閘極位於第一型態之井之上。第一型態之汲極區位於第一型態之井內，且鄰接第一型態之虛置閘極。第一型態之源極區位於第二型態之井內，且鄰接第一型態之閘極。第一型態之摻雜區位於第一型態之井內，且鄰接第二型態之井。The present invention provides a radio frequency device comprising a substrate, a gate of a first type is disposed on the substrate, a dummy gate of a first type is disposed on the substrate, and doping of a first type The region, the source region of the first type and the bungee region of the first type. The substrate comprises a well of a first type and a well of a second type, and the well of the second type is connected to the well of the first type. The gate of the first type is located above the well of the second type. The dummy gate of the first type is located above the well of the first type. The first type of drain region is located in the well of the first type and is adjacent to the dummy gate of the first type. The source region of the first type is located in the well of the second type and is adjacent to the gate of the first type. The doped region of the first type is located in the well of the first type and is adjacent to the well of the second type.
本發明另提供一種射頻元件，包含有一基底、一第一型態之閘極位於該基底之上、多數個虛置閘極位於該基底之上、多數個摻雜區、一第一型態之源極區與一第一型態之汲極區。基底包含一第一型態之井與一第二型態之井，且第二型態之井連接於第一型態之井。第一型態之閘極位於第二型態之井之上。虛置閘極位於第一型態之井之上。第一型態之汲極區位於第一型態之井內，且鄰接遠離該第一型態之閘極的該虛置閘極。第一型態之源極區位於第二型態之井內，且鄰接第一型態之閘極。摻雜區位於第一型態之井內，且位於第一型態之源極區與第一型態之汲極區之間。The present invention further provides a radio frequency device comprising a substrate, a gate of a first type is disposed on the substrate, a plurality of dummy gates are disposed on the substrate, a plurality of doped regions, and a first type The source region and a first type of bungee region. The substrate comprises a well of a first type and a well of a second type, and the well of the second type is connected to the well of the first type. The gate of the first type is located above the well of the second type. The dummy gate is located above the well of the first type. The first type of drain region is located in the well of the first type and abuts the dummy gate away from the gate of the first type. The source region of the first type is located in the well of the second type and is adjacent to the gate of the first type. The doped region is located in the well of the first type and is located between the source region of the first type and the drain region of the first type.
本發明另提供一種射頻元件的製造方法，其包括：提供一基底，此基底內包括一第一型態之井與一第二型態之井，其中第二型態之井連接於第一型態之井旁；以及形成一第一型態之虛置閘極於第一型態之井上以及形成一第一型態之閘極於該第二型態之井上。The invention further provides a method for manufacturing a radio frequency component, comprising: providing a substrate comprising a well of a first type and a well of a second type, wherein the well of the second type is connected to the first type Next to the well of the state; and forming a first type of dummy gate on the well of the first type and forming a gate of the first type on the well of the second type.
本發明另提供一種射頻元件的製造方法，其包括：提供一基底，此基底內包括一第一型態之井與一第二型態之井，其中第二型態之井連接於第一型態之井旁；以及形成複數個虛置閘極於第一型態之井，並形成一第一型態之閘極於第二型態之井上。The invention further provides a method for manufacturing a radio frequency component, comprising: providing a substrate comprising a well of a first type and a well of a second type, wherein the well of the second type is connected to the first type Next to the well of the state; and forming a plurality of dummy gates in the well of the first type, and forming a first type of gate on the well of the second type.
本發明中所描述之虛置閘極，其係與閘極同一製程且同時完成。其成分可為多晶矽或金屬，但不局限於此。其製程可為化學氣相沈積、金屬濺鍍、電鍍或其他合適之製程。The dummy gate described in the present invention is completed in the same process as the gate and simultaneously. The composition may be polycrystalline germanium or metal, but is not limited thereto. The process can be chemical vapor deposition, metal sputtering, electroplating or other suitable processes.
本發明中所描述之射頻元件可以為N型金氧半導體或P型金氧半導體。如為N型金氧半導體，則第一型態為N型態，而第二型態為P型態。如為P型金氧半導體，則第一型態為P型態，而第二型態為N型態。The radio frequency component described in the present invention may be an N-type MOS or a P-type MOS. In the case of an N-type MOS, the first type is an N-type state and the second type is a P-type state. In the case of a P-type MOS, the first type is a P-type state and the second type is an N-type state.
為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。The above and other objects, features and advantages of the present invention will become more <RTIgt;
圖2為本發明較佳實施例之一射頻元件之上視圖。2 is a top view of a radio frequency component in accordance with a preferred embodiment of the present invention.
請參照圖3，圖3為沿圖2中AA切線之剖面示意圖。如圖中所示，本發明之射頻元件包含有一基底200、一第一型態之閘極206、一第一型態之虛置閘極208、一第一型態之摻雜區210、一第一型態之源極區212與一第一型態之汲極區214。基底200包含一第一型態之井202與一第二型態之井204，第二型態之井204連接於第一型態之井202旁。第一型態之閘極206包含有一閘極電極及一閘極介電層(未標示於圖中)，第一型態之虛置閘極208包含有一虛置閘極電極及一閘極介電層(未標示於圖中)。Please refer to FIG. 3. FIG. 3 is a cross-sectional view taken along line AA of FIG. As shown in the figure, the radio frequency component of the present invention comprises a substrate 200, a gate 206 of a first type, a dummy gate 208 of a first type, a doped region 210 of a first type, and a The source region 212 of the first type and the drain region 214 of the first type. The substrate 200 includes a first type of well 202 and a second type of well 204, and a second type of well 204 is coupled to the first type of well 202. The first type of gate 206 includes a gate electrode and a gate dielectric layer (not shown). The first type of dummy gate 208 includes a dummy gate electrode and a gate dielectric. Electrical layer (not shown in the figure).
第一型態之閘極206位於第二型態之井204之上。第一型態之虛置閘極208位於第一型態之井202之上。第一型態之汲極區214位於第一型態之井202內，且鄰接第一型態之虛置閘極208。第一型態之源極區212位於第二型態之井204內，且鄰接第一型態之閘極206。第一型態之摻雜區210位於第一型態之井202內，且鄰接第二型態之井204。The first type of gate 206 is located above the second type of well 204. The dummy gate 208 of the first type is located above the well 202 of the first type. The first type of drain region 214 is located within the first type of well 202 and is adjacent to the first type of dummy gate 208. The source region 212 of the first type is located within the well 204 of the second type and is adjacent to the gate 206 of the first type. The doped region 210 of the first type is located within the well 202 of the first type and is adjacent to the well 204 of the second type.
上述之第一型態例如為N型態，第二型態例如為P型態。此外，第一型態之摻雜區210的寬度例如是大於160奈米(nm)，而第一型態之虛置閘極208的寬度例如是大於90奈米。另外，射頻元件例如更包括多數個淺摻雜汲極結構(LDD)209。這些淺摻雜汲極結構209於基底200內，且分別位於第一型態之閘極206與第一型態之虛置閘極208的兩側。The first type described above is, for example, an N type, and the second type is, for example, a P type. Furthermore, the width of the doped region 210 of the first type is, for example, greater than 160 nanometers (nm), and the width of the dummy gate 208 of the first type is, for example, greater than 90 nanometers. In addition, the radio frequency component further includes, for example, a plurality of shallow doped drain structures (LDD) 209. The shallow doped drain structures 209 are within the substrate 200 and are located on either side of the first type of gate 206 and the first type of dummy gate 208, respectively.
圖4為本發明另一實施例之一射頻元件之上視圖。4 is a top view of a radio frequency component according to another embodiment of the present invention.
請參照圖5，圖5為沿圖4中BB切線之剖面示意圖。如圖中所示，本發明之射頻元件包含有一基底200、一第一型態之閘極206、多數個虛置閘極208、多數個摻雜區210、218、一第一型態之源極區212與一第一型態之汲極區214。基底200包含一第一型態之井202與一第二型態之井204，其中第二型態之井204連接於第一型態之井202旁。第一型態之閘極206包含有一閘極電極及一閘極介電層(未標示於圖中)，虛置閘極208包含有虛置閘極電極及閘極介電層(未標示於圖中)。Please refer to FIG. 5. FIG. 5 is a cross-sectional view taken along line BB of FIG. As shown in the figure, the RF component of the present invention comprises a substrate 200, a gate 206 of a first type, a plurality of dummy gates 208, a plurality of doped regions 210, 218, and a source of a first type. The pole region 212 and a first type of drain region 214. The substrate 200 includes a first type of well 202 and a second type of well 204, wherein the second type of well 204 is coupled to the first type of well 202. The first type of gate 206 includes a gate electrode and a gate dielectric layer (not shown), and the dummy gate 208 includes a dummy gate electrode and a gate dielectric layer (not labeled In the picture).
第一型態之閘極206位於第二型態之井204之上，且位於第一型態之源極區212及摻雜區210之間。虛置閘極208位於第一型態之井202之上，且位於第一型態之汲極區214及摻雜區210之間。摻雜區218位於第一型態之井202內，且位於各個虛置閘極208之間。第一型態之汲極區214位於第一型態之井202內，且遠離第二型態之井204之一側。第一型態之源極區212位於第二型態之井204內且遠離第一型態之井202之一側。摻雜區210位於第一型態之井202內，且連接第二型態之井204之一側。The gate 206 of the first type is located above the well 204 of the second type and between the source region 212 of the first type and the doped region 210. The dummy gate 208 is located above the well 202 of the first type and between the drain region 214 of the first type and the doped region 210. Doped region 218 is located within well 202 of the first type and between each dummy gate 208. The first type of drain region 214 is located within the first type of well 202 and away from one side of the second type of well 204. The source region 212 of the first type is located within the well 204 of the second type and away from one side of the well 202 of the first type. Doped region 210 is located within well 202 of the first type and is coupled to one side of well 204 of the second type.
上述之第一型態例如為N型態，而第二型態例如為P型態。上述之摻雜區210、218例如皆為N型態之摻雜區或是皆為P型態之摻雜區。上述這些虛置閘極208可為N型態虛置閘極、P型態虛置閘極或其之組合。此外，摻雜區210、218的寬度例如是大於160奈米。虛置閘極208的寬度例如是大於90奈米。另外，射頻元件例如更包括複數個淺摻雜汲極結構209。這些淺摻雜汲極結構209於基底200內且分別位於第一型態之閘極206與虛置閘極208兩側。The first type described above is, for example, an N-type state, and the second type is, for example, a P-type state. The doped regions 210 and 218 are, for example, N-type doped regions or P-type doped regions. The dummy gates 208 may be N-type dummy gates, P-type dummy gates or a combination thereof. Furthermore, the width of the doped regions 210, 218 is, for example, greater than 160 nm. The width of the dummy gate 208 is, for example, greater than 90 nm. Additionally, the RF component, for example, further includes a plurality of shallowly doped gate structures 209. The shallow doped gate structures 209 are in the substrate 200 and are respectively located on both sides of the gate 206 and the dummy gate 208 of the first type.
圖6為本發明另一實施例之一射頻元件之上視圖。FIG. 6 is a top view of a radio frequency component according to another embodiment of the present invention.
請參照圖7，圖7為沿圖6中CC切線之剖面示意圖。如圖中所示，本發明之射頻元件包含有一基底200、一第一型態之閘極206、多數個虛置閘極208、多數個摻雜區210、216、一第一型態之源極區212與一第一型態之汲極區214。基底200包括一第一型態之井202與一第二型態之井204，其中第二型態之井204連接於第一型態之井202旁。第一型態之閘極206包含有一閘極電極及一閘極介電層(未標示於圖中)，虛置閘極208包含有虛置閘極電極及閘極介電層(未標示於圖中)。Please refer to FIG. 7. FIG. 7 is a cross-sectional view along line CC of FIG. As shown in the figure, the radio frequency component of the present invention comprises a substrate 200, a gate electrode 206 of a first type, a plurality of dummy gates 208, a plurality of doped regions 210, 216, and a source of a first type. The pole region 212 and a first type of drain region 214. The substrate 200 includes a first type well 202 and a second type well 204, wherein the second type well 204 is coupled to the first type well 202. The first type of gate 206 includes a gate electrode and a gate dielectric layer (not shown), and the dummy gate 208 includes a dummy gate electrode and a gate dielectric layer (not labeled In the picture).
第一型態之閘極206位於第二型態之井204之上，且位於第一型態之源極區212及第一型態之摻雜區210之間。虛置閘極208位於第一型態之井202之上，且位於第一型態之汲極區214及摻雜區210之間。摻雜區216位於第一型態之井202之上，且位於各個虛置閘極208之間。第一型態之汲極區214位於第一型態之井202內，且遠離第二型態之井204之一側。第一型態之源極區212位於第二型態之井204內，且遠離第一型態之井202之一側。摻雜區210位於第一型態之井202內，且連接第二型態之井204之一側。The gate 206 of the first type is located above the well 204 of the second type and between the source region 212 of the first type and the doped region 210 of the first type. The dummy gate 208 is located above the well 202 of the first type and between the drain region 214 of the first type and the doped region 210. Doped region 216 is located above well 202 of the first type and between each dummy gate 208. The first type of drain region 214 is located within the first type of well 202 and away from one side of the second type of well 204. The source region 212 of the first type is located within the well 204 of the second type and away from one side of the well 202 of the first type. Doped region 210 is located within well 202 of the first type and is coupled to one side of well 204 of the second type.
上述之第一型態例如為N型態，而第二型態例如為P型態。上述之摻雜區210、216為不同型態之摻雜區。例如，摻雜區210為N型態之摻雜區，而摻雜區216為P型態之摻雜區，或者是摻雜區210為P型態之摻雜區，而摻雜區216為N型態之摻雜區。上述這些虛置閘極208可為N型態虛置閘極、P型態虛置閘極或其之組合。此外，摻雜區210、216的寬度例如是大於160奈米。虛置閘極208的寬度例如是大於90奈米。另外，射頻元件例如更包括多數個淺摻雜汲極結構209。這些淺摻雜汲極結構209於基底200內且分別位於第一型態之閘極206與虛置閘極208兩側。The first type described above is, for example, an N-type state, and the second type is, for example, a P-type state. The doped regions 210, 216 described above are doped regions of different types. For example, the doped region 210 is an N-type doped region, and the doped region 216 is a P-type doped region, or the doped region 210 is a P-type doped region, and the doped region 216 is Doped region of the N type. The dummy gates 208 may be N-type dummy gates, P-type dummy gates or a combination thereof. Furthermore, the width of the doped regions 210, 216 is, for example, greater than 160 nm. The width of the dummy gate 208 is, for example, greater than 90 nm. Additionally, the RF component, for example, further includes a plurality of shallowly doped gate structures 209. The shallow doped gate structures 209 are in the substrate 200 and are respectively located on both sides of the gate 206 and the dummy gate 208 of the first type.
以下將介紹本發明一實施例之射頻元件的製造方法。圖8A至圖8D是本發明一實施例之射頻元件的製造方法的流程圖。請先參照圖8A，提供一基底200，此基底200包括一第一型態之井202與一第二型態之井204，其中第一型態之井202與第二型態之井204相鄰接。接著，請參照圖8B，於第一型態之井202上形成一第一型態之虛置閘極208，並於第二型態之井204上形成一第一型態之閘極206。然後，請參照圖8C，使用第一型態之閘極206與第一型態之虛置閘極208為罩幕進行一離子佈植製程220，以於基底200內形成多個淺摻雜汲極結構209。這些淺摻雜汲極結構209分別位於第一型態之閘極206與第一型態之虛置閘極208的兩側。之後，請參照圖8D，進行另一離子佈植製程230，以於第一型態之井202內形成鄰接第一型態之虛置閘極208的第一型態之汲極區214，於第二型態之井204內形成鄰接第一型態之閘極206的第一型態之源極區212，並於第一型態之井202內形成鄰接第二型態之井204的第一型態之摻雜區210。第一型態之摻雜區210位於第一型態之閘極206與第一型態之虛置閘極208之間。Hereinafter, a method of manufacturing a radio frequency component according to an embodiment of the present invention will be described. 8A to 8D are flowcharts showing a method of manufacturing a radio frequency component according to an embodiment of the present invention. Referring first to FIG. 8A, a substrate 200 is provided. The substrate 200 includes a first type well 202 and a second type well 204, wherein the first type well 202 and the second type well 204 are Adjacent. Next, referring to FIG. 8B, a dummy gate 208 of a first type is formed on the well 202 of the first type, and a gate 206 of a first type is formed on the well 204 of the second type. Then, referring to FIG. 8C, an ion implantation process 220 is performed on the mask using the gate electrode 206 of the first type and the dummy gate 208 of the first type to form a plurality of shallow dopings in the substrate 200. Pole structure 209. The shallow doped gate structures 209 are respectively located on both sides of the gate electrode 206 of the first type and the dummy gate 208 of the first type. Thereafter, referring to FIG. 8D, another ion implantation process 230 is performed to form a first type of drain region 214 adjacent to the first type of dummy gate 208 in the well 202 of the first type. A source region 212 of a first type adjacent to the gate 206 of the first type is formed in the well 204 of the second type, and a well adjacent to the well 204 of the second type is formed in the well 202 of the first type. A doped region 210 of a type. The doped region 210 of the first type is between the gate 206 of the first type and the dummy gate 208 of the first type.
在一實施例中，於進行離子佈植製程230之前，可先於第一型態之閘極206與第一型態之虛置閘極208的側壁形成間隙物。然後，於基底200、第一型態之閘極206與第一型態之虛置閘極208上形成一介電層。上述之第一型態例如為N型態，而第二型態例如為P型態。此外，第一型態之摻雜區210的寬度例如是大於160奈米，而第一型態之虛置閘極208的寬度例如是大於90奈米。In one embodiment, prior to performing the ion implantation process 230, spacers may be formed prior to the sidewalls of the first type of gate 206 and the first type of dummy gates 208. Then, a dielectric layer is formed on the substrate 200, the gate 206 of the first type, and the dummy gate 208 of the first type. The first type described above is, for example, an N-type state, and the second type is, for example, a P-type state. Furthermore, the width of the doped region 210 of the first type is, for example, greater than 160 nm, and the width of the dummy gate 208 of the first type is, for example, greater than 90 nm.
以下將介紹本發明另一實施例之射頻元件的製造方法。圖9A至圖9D是本發明一實施例之射頻元件的製造方法的流程圖。請先參照圖9A，提供一基底200，此基底200包括一第一型態之井202與一第二型態之井204，其中第一型態之井202與第二型態之井204相鄰接。接著，請參照圖9B，於第一型態之井202上形成多個虛置閘極208，並於第二型態之井204上形成一第一型態之閘極206。然後，請參照圖9C，使用第一型態之閘極206與虛置閘極208為罩幕進行一離子佈植製程220，以於基底200內形成多個淺摻雜汲極結構209。這些淺摻雜汲極結構209分別位於第一型態之閘極206與虛置閘極208的兩側。之後，請參照圖9D，進行另一離子佈植製程230，以於第一型態之井202內形成鄰接虛置閘極208的第一型態之汲極區214，於第二型態之井204內形成鄰接第一型態之閘極206的第一型態之源極區212，並於第一型態之井202內形成鄰接第二型態之井204的之摻雜區210、218。摻雜區210位於第一型態之井202內，且連接第二型態之井204之一側。摻雜區218位於第一型態之井202之上內，且位於各個虛置閘極208之間。A method of manufacturing a radio frequency component according to another embodiment of the present invention will be described below. 9A to 9D are flowcharts showing a method of manufacturing a radio frequency component according to an embodiment of the present invention. Referring first to FIG. 9A, a substrate 200 is provided. The substrate 200 includes a first type well 202 and a second type well 204, wherein the first type well 202 and the second type well 204 are Adjacent. Next, referring to FIG. 9B, a plurality of dummy gates 208 are formed on the well 202 of the first type, and a gate 206 of the first type is formed on the well 204 of the second type. Then, referring to FIG. 9C, an ion implantation process 220 is performed on the mask using the first type of gate 206 and the dummy gate 208 to form a plurality of shallow doped gate structures 209 in the substrate 200. The shallow doped gate structures 209 are respectively located on opposite sides of the gate 206 and the dummy gate 208 of the first type. Thereafter, referring to FIG. 9D, another ion implantation process 230 is performed to form a first type of drain region 214 adjacent to the dummy gate 208 in the well 202 of the first type, in the second type. A first type of source region 212 adjacent to the first type of gate 206 is formed in the well 204, and a doped region 210 adjacent to the second type of well 204 is formed in the first type of well 202, 218. Doped region 210 is located within well 202 of the first type and is coupled to one side of well 204 of the second type. Doped region 218 is located above well 202 of the first type and between each dummy gate 208.
在一實施例中，於進行離子佈植製程230之前，可先於第一型態之閘極206與虛置閘極208的側壁形成間隙物。然後，於基底200、第一型態之閘極206與虛置閘極208上形成一介電層。上述之第一型態例如為N型態，而第二型態例如為P型態。此外，第一型態之摻雜區210的寬度例如是大於160奈米，而第一型態之虛置閘極208的寬度例如是大於90奈米。In one embodiment, prior to performing the ion implantation process 230, spacers may be formed prior to the sidewalls of the first type of gate 206 and the dummy gate 208. Then, a dielectric layer is formed on the substrate 200, the gate electrode 206 of the first type, and the dummy gate 208. The first type described above is, for example, an N-type state, and the second type is, for example, a P-type state. Furthermore, the width of the doped region 210 of the first type is, for example, greater than 160 nm, and the width of the dummy gate 208 of the first type is, for example, greater than 90 nm.
本發明中所描述之虛置閘極，其係與閘極同一製程且同時完成。其成分可為多晶矽或金屬，但不局限於此。其製程可為化學汽像沉積、金屬濺鍍、電鍍或其他合適之製程。The dummy gate described in the present invention is completed in the same process as the gate and simultaneously. The composition may be polycrystalline germanium or metal, but is not limited thereto. The process can be chemical vapor deposition, metal sputtering, electroplating or other suitable processes.
本發明中所描述之射頻元件可以為N型金氧半導體或P型金氧半導體。如為N型金氧半導體，則第一型態為N型態，而第二型態為P型態。如為P型金氧半導體，則第一型態為P型態，而第二型態為N型態。The radio frequency component described in the present invention may be an N-type MOS or a P-type MOS. In the case of an N-type MOS, the first type is an N-type state and the second type is a P-type state. In the case of a P-type MOS, the first type is a P-type state and the second type is an N-type state.
以上所述僅為本發明之較佳實施例，並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範疇內，當可作些許之變化與修飾，此些均等變化與修飾皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any changes and modifications may be made without departing from the spirit and scope of the invention. Both modifications and modifications are intended to be within the scope of the invention.
100．．．半導體基底100. . . Semiconductor substrate
102．．．N型態之井102. . . N type well
104．．．P型態之摻雜區104. . . P-type doped region
106．．．P型態之埋入摻雜區106. . . P-type buried doped region
108．．．閘極108. . . Gate
110．．．N型態之源極區110. . . N-type source region
112．．．N型態之汲極區112. . . N-type bungee zone
200．．．基底200. . . Base
202．．．第一型態之井202. . . First type well
204．．．第二型態之井204. . . Second type well
206．．．第一型態之閘極206. . . First type gate
208．．．第一型態之虛置閘極(虛置閘極)208. . . The first type of dummy gate (dummy gate)
209．．．淺摻雜汲極結構209. . . Shallowly doped 汲 structure
210．．．第一型態之摻雜區(摻雜區)210. . . Doped region of the first type (doped region)
212．．．第一型態之源極區212. . . Source region of the first type
214．．．第一型態之汲極區214. . . First type bungee area
216、218．．．摻雜區216, 218. . . Doped region
圖1為習知之一高壓射頻元件之截面示意圖。1 is a schematic cross-sectional view of a conventional high voltage RF component.
圖2為本發明較佳實施例之一射頻元件之上視圖。2 is a top view of a radio frequency component in accordance with a preferred embodiment of the present invention.
圖3為本發明較佳實施例之一射頻元件之剖面示意圖。3 is a cross-sectional view showing a radio frequency component of a preferred embodiment of the present invention.
圖4為本發明另一實施例之一射頻元件之上視圖。4 is a top view of a radio frequency component according to another embodiment of the present invention.
圖5為本發明另一實施例之一射頻元件之剖面示意圖。FIG. 5 is a cross-sectional view showing a radio frequency component according to another embodiment of the present invention.
圖6為本發明另一實施例之一射頻元件之上視圖。FIG. 6 is a top view of a radio frequency component according to another embodiment of the present invention.
圖7為本發明另一實施例之一射頻元件之剖面示意圖。FIG. 7 is a cross-sectional view showing a radio frequency component according to another embodiment of the present invention.
圖8A至圖8D是本發明一實施例之射頻元件的製造方法的流程圖。8A to 8D are flowcharts showing a method of manufacturing a radio frequency component according to an embodiment of the present invention.
圖9A至圖9D是本發明另一實施例之射頻元件的製造方法的流程圖。9A to 9D are flowcharts showing a method of manufacturing a radio frequency component according to another embodiment of the present invention.
200．．．基底200. . . Base
202．．．第一型態之井202. . . First type well
204．．．第二型態之井204. . . Second type well
206．．．第一型態之閘極206. . . First type gate
208．．．第一型態之虛置閘極208. . . First type of dummy gate
209．．．淺摻雜汲極結構209. . . Shallowly doped 汲 structure
210．．．摻雜區210. . . Doped region
212．．．第一型態之源極區212. . . Source region of the first type
214．．．第一型態之汲極區214. . . First type bungee area
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| US20070290266A1 (en) * | 2003-07-17 | 2007-12-20 | Ming-Dou Ker | Turn-on-efficient bipolar structures for on-chip esd protection |
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