US8406043B2 - Phase change memory apparatus having global bit line and method for driving the same - Google Patents

Phase change memory apparatus having global bit line and method for driving the same Download PDF

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Publication number
US8406043B2
US8406043B2 US12833082 US83308210A US8406043B2 US 8406043 B2 US8406043 B2 US 8406043B2 US 12833082 US12833082 US 12833082 US 83308210 A US83308210 A US 83308210A US 8406043 B2 US8406043 B2 US 8406043B2
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phase change
change memory
global bit
internal voltage
bit line
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US20110149643A1 (en )
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Hyuck Soo Yoon
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SK Hynix Inc
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SK Hynix Inc
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0038Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • G11C5/14Power supply arrangements, e.g. Power down/chip (de)selection, layout of wiring/power grids, multiple supply levels
    • G11C5/147Voltage reference generators, voltage and current regulators ; Internally lowered supply level ; Compensation for voltage drops
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00 - G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0023Address circuits or decoders
    • G11C13/0026Bit-line or column circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/72Array wherein the access device being a diode

Abstract

A phase change memory apparatus includes a global bit line and an internal power generation circuit. The global bit line is configured to integratedly control a plurality of bit lines. The internal power generation circuit is configured to supply an internal voltage while the global bit line is discharged and configured to control the internal voltage after the global bit line is discharged, when a deep power down mode signal is enabled.

Description

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) to Korean application number 10-2009-0130176, filed on Dec. 23, 2009, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety as set forth in full.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor integrated circuit and a method for driving the same, and more particularly, to a phase change memory apparatus having a global bit line and a method for driving the same.

2. Related Art

In general, a semiconductor memory apparatus has a number of different operation modes. These operation modes include a standby mode, an active mode, and a deep power down mode. The standby mode refers to a state in which no chip is selected. The active mode refers to a state in which the read and write operations inherent to the semiconductor memory apparatus can be performed in response to the application of commands. In the standby and active modes, the semiconductor memory apparatus has the same internal voltage levels.

In the deep power down mode, the internal voltages under the standby and active modes are dropped or intercepted, so that circuits operating by the internal voltages are interrupted and the current consumed by an internal voltage generation circuit including a level boosting or level dropping circuit comes down to zero.

A phase change memory apparatus as a next-generation memory apparatus also has a standby mode, an active mode, and a deep power down mode. When entering the deep power down mode, internal power is intercepted so that cell data write current supplied from bit lines is intercepted.

When such a phase change memory apparatus operates in the deep power down mode, since internal voltages are intercepted at the same time with the application of a command for entering the deep power down mode, the discharge of the bit lines cannot be smoothly implemented.

That is to say, when entering the deep power down mode, since the internal voltages are intercepted at the same time with the discharge of global bit lines, a time for discharging the global bit lines is extended, and it is difficult to protect the cell data of the bit lines connected to the global bit lines. Due to this fact, a problem can be caused in terms of latch-up, and a power-up time for returning to a normal operation cannot help but be lengthened.

SUMMARY

In one embodiment of the present invention, a phase change memory apparatus comprises a global bit line configured to integratedly control a plurality of bit lines, and an internal power generation circuit configured to supply an internal voltage while the global bit line is discharged and control the internal voltage after the global bit line is discharged when a deep power down mode signal is enabled.

In another embodiment of the present invention, a phase change memory apparatus comprises a plurality of phase change memory cells disposed between a plurality of word lines and a plurality of bit lines which intersect with each other, a plurality of global bit lines configured to classify the plurality of bit lines into groups each having a predetermined number of bit lines and integratedly control the respective groups of bit lines, an internal voltage generation unit configured to supply power for driving the phase change memory cells, and an internal voltage control unit configured to control driving of the internal voltage generation unit when entering a deep power down mode.

In another embodiment of the present invention, a method for driving a phase change memory apparatus comprises the step of generating an internal voltage until a global bit line connected with a plurality of bit lines of phase change memory cells is completely discharged, and then interrupting supply of the internal voltage, when a deep power down mode is entered.

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments are described in conjunction with the attached drawings, in which:

FIG. 1 is a configurational view illustrating a part of a cell array of a phase change memory apparatus according to one embodiment;

FIG. 2 is a schematic view illustrating the transmission paths of read and write currents in the phase change memory apparatus according to one embodiment;

FIG. 3 is a block diagram showing an internal power generation circuit of the phase change memory apparatus according to one embodiment;

FIG. 4 is a detailed circuit diagram of an internal voltage control unit shown in FIG. 3; and

FIG. 5 is a detailed circuit diagram of a global discharge signal generation unit shown in FIG. 3.

DETAILED DESCRIPTION

Hereinafter, a phase change memory apparatus having a global bit line and a method for driving the same according to the present invention will be described below with reference to the accompanying drawings through embodiments.

Referring to FIG. 1, a phase change memory apparatus 100 according to one embodiment can include a cell array CA, a column switch unit 150, a column control circuit 200, and an internal power generation circuit 300.

The cell array CA includes a plurality of word lines WL1-WLn and a plurality of bit lines BL1-BLn, which are arranged to intersect with each other. Respective points of intersection of the plurality of word lines WL1-WLn with the plurality of bit lines BL1-BLn are provided with memory cells C, respectively. The memory cells C can include phase change resistors R connected with the bit lines BL1-BLn, and diodes D connected between the word lines WL1-WLn and the phase change resistors R. Active switches such as MOS transistors can be used in place of the diodes D.

The cell array CA can further include a bit line discharge line BLDIS which is arranged below the plurality of word lines WL1-WLn and extends parallel to the word lines WL1-WLn. The bit line discharge line BLDIS also intersects with the plurality of bit lines BL1-BLn, and discharge circuit elements 120 are disposed at respective points of intersection. The discharge circuit elements 120 may include MOS transistors which are configured to discharge the signals of the bit lines BL1-BLn to a ground voltage when the bit line discharge line BLDIS is enabled. However, the discharge circuit elements 120 are not limited thereto, and can also be used as dummy cells of the same type as the memory cells.

A global bit line GBL is arranged on a side of the plurality of bit lines BL1-BLn on the outer periphery of the cell array CA, and extends parallel to the bit lines BL1-BLn. The global bit line GBL serves as a significant bit line for integrated control of the bit lines BL1-BLn.

The column switch unit 150 includes local switches SW1-SWn which connect the global bit line GBL with the respective bit lines BL1-BLn. The plurality of local switches SW1-SWn are configured to supply the signals of the corresponding bit lines BL1-BLn to the global bit line GBL in response to column select signals LY1-LYn. The column select signals LY1-LYn are activated one by one in an active mode and select unit cells C connected to the corresponding bit lines BL.

The column control circuit 200 is disposed on one end of the global bit line GBL. The column control circuit 200 includes a GBL discharge unit 160, a global column switch 170, a sense amplifier (S/A) 180, and a write driver (W/D) 190.

The GBL discharge unit 160 is configured to discharge the signal loaded on the global bit line GBL, in response to a global bit line discharge signal GBLDIS. The global discharge unit 160 may include an NMOS transistor which is driven in response to the global bit line discharge signal GBLDIS as shown in FIG. 2.

The global column switch 170 serves as a switch which selectively connects a node 195 (hereinafter referred to as a connection node), connecting the sense amplifier 180 and the write driver 190, and the global bit line GBL. The global column switch 170 may include a PMOS transistor P which is configured to electrically connect the connection node 195 and the global bit line GBL in response to a first global column switching signal GYSWP, and an NMOS transistor N which is configured to electrically connect the connection node 195 and the global bit line GBL in response to a second global column switching signal GYSWN. The first and second global column switching signals GYSWP and GYSWN may be signals which have opposite phases.

The sense amplifier 180 is configured to sense the data of the cell C which is applied via the global bit line GBL, compare the data with a reference voltage, and determine data “1” or “0”.

The write driver 190 is configured to supply the global bit line GBL with a driving voltage corresponding to write data when writing the data of the cell C.

Thus, the phase change memory apparatus 100 configured as mentioned above has a current transmission path in which the current supplied from the sense amplifier 180 or the write driver 190 is transferred to the corresponding memory cell C through the global column switch 170, the global bit line GBL, the column switch unit 150, and the bit lines BL1-BLn, as shown in FIG. 2.

The internal power generation circuit 300 includes an internal voltage control unit 310, an internal voltage generation unit 330, and a global discharge signal generation unit 350.

The internal voltage control unit 310 is configured to control the driving of the internal voltage generation unit 330 in the deep power down mode, that is, when a deep power down mode signal DPD is enabled. In detail, the internal voltage control unit 310 is configured to maintain power supply while the global bit line GBL is discharged when entering the deep power down mode. The internal voltage control unit 310 receives the deep power down mode signal DPD and generates a delayed deep power down mode signal dDPD. The internal voltage control unit 310 may comprise, but not limited to, a delay unit composed of a chain of a plurality of inverters as shown in FIG. 4. The delay value of the internal voltage control unit 310 corresponds to a time capable of completely discharging the global bit line GBL. That is, the delay time value of the internal voltage control unit 310 is a predetermined time period which allows the global bit lines sufficient amounts of time to substantially discharge signals.

The internal voltage generation unit 330 is configured to generate an internal voltage Vint in the active mode and interrupt the generation of the internal voltage Vint when the delayed deep power down mode signal dDPD is enabled. Accordingly, the output currents of the internal circuit of the semiconductor memory apparatus become zero.

The global discharge signal generation unit 350 is configured to generate a global bit line discharge signal GBLDIS in response to the deep power down mode signal DPD and a global bit line discharge command GBLDISC. Namely, the global discharge signal generation unit 350 is configured such that the global bit line discharge signal GBLDIS is enabled when both the deep power down mode signal DPD and the global bit line discharge command GBLDISC are enabled. The global bit line discharge command GBLDISC may be a signal which is always enabled.

As shown in FIG. 5, the global discharge signal generation unit 350 can include a NOR gate NOR which receives the deep power down mode signal DPD and the global bit line discharge command GBLDISC, and an inverter IN which inverts the output signal of the NOR gate NOR.

In the phase change memory apparatus having the configuration as stated above, when the deep power down mode signal DPD is enabled, while the internal voltage control unit 310 delays the deep power down mode signal DPD for a predetermined time, the global bit line discharge signal GBLDIS is enabled such that all the signals loaded on the global bit line GBL are discharged. Thereafter, the level of the internal voltage Vint as the output level of the internal voltage generation unit 330 is controlled, that is, dropped using the delayed deep power down mode signal dDPD.

As a consequence, since the internal voltage is continuously supplied when the deep power down mode signal DPD is enabled and the global bit line GBL is discharged, it is possible to prevent or protecting against discharge speeds from decreasing.

Also, since only the global bit line GBL is discharged in the deep power down mode and the bit lines BL connected thereto are floated, then cell data can be protected.

Because the discharge speed is improved in this way, a problem caused in terms of latch-up can be solved or minimized, and as a result current consumption characteristics can be improved.

The present invention is not limited to the above-mentioned embodiments.

It is obvious to those skilled in the art that, although the semiconductor memory apparatus according to the embodiment has been described with reference to a plurality of bit lines and one single global line for the sake of convenience in explanation, the semiconductor memory apparatus includes a plurality of global lines.

While certain embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are by way of example only. Accordingly, the phase change memory apparatus having a global bit line and the method for driving the same described herein should not be limited based on the described embodiments. Rather, the phase change memory apparatus having a global bit line and the method for driving the same described herein should only be limited in light of the claims that follow when taken in conjunction with the above description and accompanying drawings.

Claims (12)

What is claimed is:
1. A phase change memory apparatus comprising:
a global bit line configured to integratedly control a plurality of bit lines; and
an internal power generation circuit configured to supply an internal voltage while the global bit line is discharged and control the internal voltage after the global bit line is discharged, when a deep power down mode signal is enabled.
2. The phase change memory apparatus according to claim 1, wherein the internal power generation circuit comprises:
an internal voltage control unit configured to receive the deep power down mode signal and output a control signal; and
an internal voltage generation unit configured to control generation of the internal voltage in response to the control signal.
3. The phase change memory apparatus according to claim 2, wherein the internal voltage control unit comprises a delay unit, and the control signal is a delayed deep power down mode signal which is delayed for a predetermined time.
4. The phase change memory apparatus according to claim 3, wherein the predetermined time is for substantially completely discharging the global bit line.
5. The phase change memory apparatus according to claim 2, wherein the internal power generation circuit further comprises:
a global discharge signal generation unit configured to generate a signal for discharging the global bit line in response to the deep power down mode signal.
6. The phase change memory apparatus according to claim 5, wherein the global discharge signal generation unit is configured to generate a signal for discharging the global bit line when both the deep power down mode signal and a global bit line discharge command are enabled.
7. A phase change memory apparatus comprising:
phase change memory cells disposed between intersecting word and bit lines;
global bit lines configured to classify and integratedly control groups of bit lines each group having a predetermined number of bit lines;
an internal voltage generation unit configured to supply power for driving the phase change memory cells; and
an internal voltage control unit configured to control driving of the internal voltage generation unit when entering a deep power down mode, wherein the internal voltage control unit is configured to maintain the internal voltage generation unit in driving the phase change memory cells until the global bit lines are substantially discharged when entering the deep power down mode.
8. The phase change memory apparatus according to claim 7, wherein the internal voltage control unit comprises a delay unit which receives a deep power down mode signal for determining entry to the deep power down mode and delays the deep power down mode signal for a predetermined time.
9. The phase change memory apparatus according to claim 8, wherein the predetermined time allows the global bit lines sufficient amounts of time to substantially discharge.
10. The phase change memory apparatus according to claim 8, further comprising:
a global discharge signal generation unit configured to generate a signal for discharging the global bit lines in response to the deep power down mode signal.
11. The phase change memory apparatus according to claim 10, wherein the global discharge signal generation unit is configured to generate the signal for discharging the global bit lines when both the deep power down mode signal and a global bit line discharge command are enabled.
12. A method for driving a phase change memory apparatus, comprising the step of:
generating an internal voltage until a global bit line connected with a plurality of bit lines of phase change memory cells is substantially completely discharged, and then interrupting supply of the internal voltage, when a deep power down mode is entered.
US12833082 2009-12-23 2010-07-09 Phase change memory apparatus having global bit line and method for driving the same Active 2031-07-12 US8406043B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120092946A1 (en) * 2010-10-19 2012-04-19 Samsung Electronics Co., Ltd. Memory devices and memory systems including discharge lines and methods of forming
US20140063989A1 (en) * 2012-08-29 2014-03-06 SK Hynix Inc. Semiconductor memory device including write driver and method of controlling the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150048427A (en) * 2013-10-28 2015-05-07 에스케이하이닉스 주식회사 Discharge circuit

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003143240A (en) 2001-10-31 2003-05-16 Matsushita Electric Ind Co Ltd Data transmission circuit, and the semiconductor integrated circuit
JP2005056529A (en) 2003-08-07 2005-03-03 Elpida Memory Inc Semiconductor storage device
JP2005092912A (en) 2003-09-12 2005-04-07 Sharp Corp Nonvolatile semiconductor memory device
JP2005317124A (en) 2004-04-28 2005-11-10 Matsushita Electric Ind Co Ltd Semiconductor memory device
US20060023497A1 (en) * 2004-07-28 2006-02-02 Sharp Kabushiki Kaisha Nonvolatile semiconductor memory device and read method
JP2007004966A (en) 2005-06-21 2007-01-11 Samsung Electronics Co Ltd Phase change memory device
KR20070019066A (en) 2005-08-11 2007-02-15 삼성전자주식회사 Semiconductor memory device for discharging wordline with negative voltage corresponding to temperature
US7402965B2 (en) 2006-09-21 2008-07-22 Rockwell Automation Technologies, Inc. DC common bus self-protection method and system
US7453716B2 (en) 2004-10-26 2008-11-18 Samsung Electronics Co., Ltd Semiconductor memory device with stacked control transistors
KR20090052016A (en) 2007-11-20 2009-05-25 삼성전자주식회사 Phase change memory device and bitline discharge method thereof
US20090141567A1 (en) 2007-11-09 2009-06-04 Kwang Jin Lee Semiconductor device having memory array, method of writing, and systems associated therewith
US20090141579A1 (en) * 2007-11-29 2009-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Power Up/Down Sequence Scheme for Memory Devices
US20090285009A1 (en) * 2008-05-19 2009-11-19 Samsung Electronics Co., Ltd. Nonvolatile memory devices using variable resistive elements
US20100118593A1 (en) 2005-08-10 2010-05-13 Samsung Electronics Co., Ltd. Variable resistance memory device and system thereof
US20120005558A1 (en) * 2010-07-01 2012-01-05 Steiner Avi System and method for data recovery in multi-level cell memories

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003143240A (en) 2001-10-31 2003-05-16 Matsushita Electric Ind Co Ltd Data transmission circuit, and the semiconductor integrated circuit
JP2005056529A (en) 2003-08-07 2005-03-03 Elpida Memory Inc Semiconductor storage device
JP2005092912A (en) 2003-09-12 2005-04-07 Sharp Corp Nonvolatile semiconductor memory device
JP2005317124A (en) 2004-04-28 2005-11-10 Matsushita Electric Ind Co Ltd Semiconductor memory device
US20060023497A1 (en) * 2004-07-28 2006-02-02 Sharp Kabushiki Kaisha Nonvolatile semiconductor memory device and read method
US7453716B2 (en) 2004-10-26 2008-11-18 Samsung Electronics Co., Ltd Semiconductor memory device with stacked control transistors
JP2007004966A (en) 2005-06-21 2007-01-11 Samsung Electronics Co Ltd Phase change memory device
US7227776B2 (en) 2005-06-21 2007-06-05 Samsung Electronics Co., Ltd. Phase change random access memory (PRAM) device
US20100118593A1 (en) 2005-08-10 2010-05-13 Samsung Electronics Co., Ltd. Variable resistance memory device and system thereof
KR20070019066A (en) 2005-08-11 2007-02-15 삼성전자주식회사 Semiconductor memory device for discharging wordline with negative voltage corresponding to temperature
US7402965B2 (en) 2006-09-21 2008-07-22 Rockwell Automation Technologies, Inc. DC common bus self-protection method and system
US20090141567A1 (en) 2007-11-09 2009-06-04 Kwang Jin Lee Semiconductor device having memory array, method of writing, and systems associated therewith
KR20090052016A (en) 2007-11-20 2009-05-25 삼성전자주식회사 Phase change memory device and bitline discharge method thereof
US20090141579A1 (en) * 2007-11-29 2009-06-04 Taiwan Semiconductor Manufacturing Co., Ltd. Power Up/Down Sequence Scheme for Memory Devices
US20090285009A1 (en) * 2008-05-19 2009-11-19 Samsung Electronics Co., Ltd. Nonvolatile memory devices using variable resistive elements
KR20090120242A (en) 2008-05-19 2009-11-24 삼성전자주식회사 Nonvolatile memory device using variable resistive element
US20120005558A1 (en) * 2010-07-01 2012-01-05 Steiner Avi System and method for data recovery in multi-level cell memories

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120092946A1 (en) * 2010-10-19 2012-04-19 Samsung Electronics Co., Ltd. Memory devices and memory systems including discharge lines and methods of forming
US8724411B2 (en) * 2010-10-19 2014-05-13 Samsung Electronics Co., Ltd. Memory devices and memory systems including discharge lines
US20140063989A1 (en) * 2012-08-29 2014-03-06 SK Hynix Inc. Semiconductor memory device including write driver and method of controlling the same
US9019783B2 (en) * 2012-08-29 2015-04-28 SK Hynix Inc. Semiconductor memory device including write driver and method of controlling the same

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KR101094918B1 (en) 2011-12-15 grant
US20110149643A1 (en) 2011-06-23 application
KR20110073029A (en) 2011-06-29 application

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