US8129248B2 - Method of producing bipolar transistor structures in a semiconductor process - Google Patents

Method of producing bipolar transistor structures in a semiconductor process Download PDF

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US8129248B2
US8129248B2 US12/833,573 US83357310A US8129248B2 US 8129248 B2 US8129248 B2 US 8129248B2 US 83357310 A US83357310 A US 83357310A US 8129248 B2 US8129248 B2 US 8129248B2
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window
silicon layer
bipolar transistor
trisilane
semiconductor process
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US20110165760A1 (en
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Thomas Scharnagl
Berthold Staufer
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Texas Instruments Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02658—Pretreatments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors

Definitions

  • the invention relates to a method of producing bipolar transistor structures in a semiconductor process, in particular transistor structures in BICOM (bipolar complementary) technology.
  • the window for a transistor base is usually structured by means of an anisotropic plasma etching step.
  • the window defined by a patterned resist layer is thus structured with straight side walls that extend through a polycrystalline silicon layer (hereinafter “poly”) covered with an oxide layer.
  • poly polycrystalline silicon layer
  • an advanced trisilane (Si 3 H 8 ) epitaxial process is a preferred option due to the low cost and high yield of that process.
  • the method of producing bipolar transistor structures in a semiconductor process comprises the step of structuring, by plasma etching, a base window in a polycrystalline silicon layer covered with an oxide layer, and the further step of epitaxial growing a silicon layer in the base window from trisilane.
  • the plasma etching is performed in a sequence of anisotropic etch and isotropic ash steps, thereby creating stepped and inwardly sloping window edges. Due to the inwardly sloping side walls of the window, the epitaxially grown silicon layer is formed without inwardly overhanging structures, and the cause of poly stringers forming is thus eliminated.
  • FIG. 1 a to 1 e are schematic sectional views illustrating successive semiconductor process steps in the formation of a bipolar transistor base window that would result in the occurrence of poly stringers;
  • FIGS. 2 a and 2 b are schematic sectional views illustrating alternative semiconductor process steps in the formation of a bipolar transistor base window that avoid the occurrence of poly stringers.
  • a bipolar base window 10 is shown as defined by a patterned resist 12 and extending through a polycrystalline silicon layer 14 covered by an oxide layer 16 .
  • the window is structured using an anisotropic plasma etching step. As a result the window has straight side walls that extend all the way through the oxide layer 16 and the poly layer 14 down to an underlying oxide layer 18 .
  • an EPI layer 20 is subsequently grown in the exposed window and over the adjacent oxide layer 16 using an advanced trisilane epitaxial process, the EPI layer 20 is formed with inwardly bulged overhanging beads 20 a . Underneath the beads 20 a , outwardly directed recesses 20 b are formed.
  • dielectric layers 22 are deposited over the EPI layer 20 .
  • the dielectric layers 22 completely fill the recesses 20 b left by the EPI layer 20 .
  • anisotropic plasma etching cannot remove the dielectric material from the recesses 20 b .
  • An alternative wet etching step is not possible for reasons of process technology.
  • the residual dielectric material from the recesses 20 b acts like a screen to the anisotropic etching, and any material from the EPI layer that is located immediately underneath will not be removed, thereby leaving “poly stringers” 26 next to the structured part of the EPI layer. These poly stringers can make the semiconductor component inoperative.
  • the inventive method involves shaping of the base window with side walls that are stepped and slope inwardly of the window, as shown. This is achieved with a plasma etch process that consists of sequential anisotropic etch and isotropic ash steps.
  • the sequential anisotropic etch and isotropic ash steps must be adjusted so as to achieve the desired shape of the window side walls.
  • an EPI layer 28 is obtained free from overhanging beads, and the EPI layer can be structured without any risk of forming poly stringers.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

In the method of producing bipolar transistor structures in a semiconductor process, an advanced epitaxial trisilane process can be used without the risk of poly stringers being formed. A base window is structured in a polycrystalline silicon layer covered with an oxide layer, and a further step is epitaxial growing of a silicon layer in the base window from trisilane. The window structuring is performed in a sequence of anisotropic etch and isotropic ash steps, thereby creating stepped and inwardly sloping window edges. Due to the inwardly sloping side walls of the window, the epitaxially grown silicon layer is formed without inwardly overhanging structures, and the cause of poly stringers forming is thus eliminated.

Description

FIELD OF THE INVENTION
The invention relates to a method of producing bipolar transistor structures in a semiconductor process, in particular transistor structures in BICOM (bipolar complementary) technology.
BACKGROUND
In a typical sequence of a BICOM fabricating process the window for a transistor base is usually structured by means of an anisotropic plasma etching step. The window defined by a patterned resist layer is thus structured with straight side walls that extend through a polycrystalline silicon layer (hereinafter “poly”) covered with an oxide layer. For epitaxial (“EPI”) growing of a silicon layer in the base window an advanced trisilane (Si3H8) epitaxial process is a preferred option due to the low cost and high yield of that process. With shrinking component dimensions and increasing thickness of the polycrystalline silicon layer, however, the trisilane epitaxial process is not applicable due to the forming of residual poly stringers after structuring that epitaxial layer by etching, as will be explained in more detail with reference to the appending drawings. These stringers affect operation of the resulting circuit component.
SUMMARY
In one aspect of the invention a method of producing bipolar transistor structures in a semiconductor process is provided, wherein an advanced epitaxial trisilane process can be used without the risk of poly stringers being formed. In accordance with the invention, the method of producing bipolar transistor structures in a semiconductor process comprises the step of structuring, by plasma etching, a base window in a polycrystalline silicon layer covered with an oxide layer, and the further step of epitaxial growing a silicon layer in the base window from trisilane. The plasma etching is performed in a sequence of anisotropic etch and isotropic ash steps, thereby creating stepped and inwardly sloping window edges. Due to the inwardly sloping side walls of the window, the epitaxially grown silicon layer is formed without inwardly overhanging structures, and the cause of poly stringers forming is thus eliminated.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 a to 1 e are schematic sectional views illustrating successive semiconductor process steps in the formation of a bipolar transistor base window that would result in the occurrence of poly stringers; and
FIGS. 2 a and 2 b are schematic sectional views illustrating alternative semiconductor process steps in the formation of a bipolar transistor base window that avoid the occurrence of poly stringers.
 DETAILED DESCRIPTION OF AN EXAMPLE EMBODIMENT
In FIG. 1 a, a bipolar base window 10 is shown as defined by a patterned resist 12 and extending through a polycrystalline silicon layer 14 covered by an oxide layer 16. The window is structured using an anisotropic plasma etching step. As a result the window has straight side walls that extend all the way through the oxide layer 16 and the poly layer 14 down to an underlying oxide layer 18.
If, as illustrated in FIG. 1 b, an EPI layer 20 is subsequently grown in the exposed window and over the adjacent oxide layer 16 using an advanced trisilane epitaxial process, the EPI layer 20 is formed with inwardly bulged overhanging beads 20 a. Underneath the beads 20 a, outwardly directed recesses 20 b are formed.
In a subsequent process step, as illustrated in FIG. 1 c, dielectric layers 22 (oxide, nitride, etc.) are deposited over the EPI layer 20. The dielectric layers 22 completely fill the recesses 20 b left by the EPI layer 20.
In a further subsequent process step, as illustrated in FIG. 1 d, anisotropic plasma etching cannot remove the dielectric material from the recesses 20 b. An alternative wet etching step is not possible for reasons of process technology.
When the EPI layer 20 is then structured, as illustrated in FIG. 1 e, the residual dielectric material from the recesses 20 b acts like a screen to the anisotropic etching, and any material from the EPI layer that is located immediately underneath will not be removed, thereby leaving “poly stringers” 26 next to the structured part of the EPI layer. These poly stringers can make the semiconductor component inoperative.
Turning now to FIG. 2 a, the inventive method involves shaping of the base window with side walls that are stepped and slope inwardly of the window, as shown. This is achieved with a plasma etch process that consists of sequential anisotropic etch and isotropic ash steps. The sequential anisotropic etch and isotropic ash steps must be adjusted so as to achieve the desired shape of the window side walls.
When the EPI layer is then grown over the base window using a trisilane epitaxial process, as shown in FIG. 2 b, an EPI layer 28 is obtained free from overhanging beads, and the EPI layer can be structured without any risk of forming poly stringers.
Although the invention has been described hereinabove with reference to a specific embodiment, it is not limited to this embodiment and no doubt further alternatives will occur to the skilled person that lie within the scope of the invention as claimed.

Claims (1)

The invention claimed is:
1. A method of producing bipolar transistor structures in a semiconductor process, comprising the steps of:
structuring, by plasma etching, a base window in a polycrystalline silicon layer covered with an oxide layer;
epitaxial growing a silicon layer in the base window from trisilane;
wherein said plasma etching is performed in a sequence of anisotropic etch and isotropic ash steps, thereby creating stepped and inwardly sloping window edges.
US12/833,573 2009-07-13 2010-07-09 Method of producing bipolar transistor structures in a semiconductor process Active 2030-10-21 US8129248B2 (en)

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DE102009032854 2009-07-13
DE102009032854.8A DE102009032854B4 (en) 2009-07-13 2009-07-13 Method for producing bipolar transistor structures in a semiconductor process
DE102009032854.8 2009-07-13

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009032854B4 (en) 2009-07-13 2015-07-23 Texas Instruments Deutschland Gmbh Method for producing bipolar transistor structures in a semiconductor process
CN102693911A (en) * 2011-03-23 2012-09-26 上海华虹Nec电子有限公司 Dry etching method

Citations (22)

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US4698128A (en) * 1986-11-17 1987-10-06 Motorola, Inc. Sloped contact etch process
US4764245A (en) * 1986-05-07 1988-08-16 Siemens Aktiengesellschaft Method for generating contact holes with beveled sidewalls in intermediate oxide layers
US4902377A (en) * 1989-05-23 1990-02-20 Motorola, Inc. Sloped contact etch process
US4999318A (en) * 1986-11-12 1991-03-12 Hitachi, Ltd. Method for forming metal layer interconnects using stepped via walls
US5317193A (en) * 1992-05-07 1994-05-31 Mitsubishi Denki Kabushiki Kaisha Contact via for semiconductor device
US5366848A (en) * 1991-04-09 1994-11-22 Sgs-Thomson Microelectronics, Inc. Method of producing submicron contacts with unique etched slopes
US5663091A (en) * 1993-05-20 1997-09-02 Actel Corporation Method for fabricating an electrically programmable antifuse
US6040247A (en) * 1995-01-10 2000-03-21 Lg Semicon Co., Ltd. Method for etching contact
US6137135A (en) * 1997-08-08 2000-10-24 Sanyo Electric Co., Ltd. Semiconductor device and method of fabricating the same
US6313019B1 (en) * 2000-08-22 2001-11-06 Advanced Micro Devices Y-gate formation using damascene processing
US6495294B1 (en) * 1999-10-28 2002-12-17 Denso Corporation Method for manufacturing semiconductor substrate having an epitaxial film in the trench
US20030052088A1 (en) * 2001-09-19 2003-03-20 Anisul Khan Method for increasing capacitance in stacked and trench capacitors
US20040178171A1 (en) * 2001-05-10 2004-09-16 Ranganathan Nagarajan Sloped trench etching process
US20040212045A1 (en) * 2003-01-23 2004-10-28 Infineon Technologies Ag Bipolar transistor and method of producing same
US20060189124A1 (en) * 2005-02-10 2006-08-24 Gottfried Beer Semiconductor device having a through contact through a housing composition and method for producing the same
US20060281246A1 (en) * 2005-03-31 2006-12-14 Stefan Tegen Semiconductor having structure with openings
US20080014725A1 (en) * 2001-02-12 2008-01-17 Asm America, Inc. Deposition over mixed substrates using trisilane
US20080054304A1 (en) * 2005-08-25 2008-03-06 Sadaka Mariam G Semiconductor Device Including a Lateral Field-Effect Transistor and Schottky Diode
US20090224363A1 (en) * 2008-03-10 2009-09-10 Hiroshi Yoshida Semiconductor device and manufacturing method thereof
US20090301549A1 (en) * 2006-10-09 2009-12-10 Soltaix, Inc. Solar module structures and assembly methods for three-dimensional thin-film solar cells
US20100171223A1 (en) * 2009-01-05 2010-07-08 Chen-Cheng Kuo Through-Silicon Via With Scalloped Sidewalls
DE102009032854A1 (en) 2009-07-13 2011-01-27 Texas Instruments Deutschland Gmbh Method for manufacturing bipolar transistor base windows during semiconductor production process, involves implementing corroding process after completion of corroding and isotropic incineration processes such that window edges are formed

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2756100B1 (en) * 1996-11-19 1999-02-12 Sgs Thomson Microelectronics BIPOLAR TRANSISTOR WITH INHOMOGENEOUS TRANSMITTER IN A BICMOS INTEGRATED CIRCUIT

Patent Citations (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4764245A (en) * 1986-05-07 1988-08-16 Siemens Aktiengesellschaft Method for generating contact holes with beveled sidewalls in intermediate oxide layers
US4999318A (en) * 1986-11-12 1991-03-12 Hitachi, Ltd. Method for forming metal layer interconnects using stepped via walls
US4698128A (en) * 1986-11-17 1987-10-06 Motorola, Inc. Sloped contact etch process
US4902377A (en) * 1989-05-23 1990-02-20 Motorola, Inc. Sloped contact etch process
US5366848A (en) * 1991-04-09 1994-11-22 Sgs-Thomson Microelectronics, Inc. Method of producing submicron contacts with unique etched slopes
US5317193A (en) * 1992-05-07 1994-05-31 Mitsubishi Denki Kabushiki Kaisha Contact via for semiconductor device
US5663091A (en) * 1993-05-20 1997-09-02 Actel Corporation Method for fabricating an electrically programmable antifuse
US6040247A (en) * 1995-01-10 2000-03-21 Lg Semicon Co., Ltd. Method for etching contact
US6137135A (en) * 1997-08-08 2000-10-24 Sanyo Electric Co., Ltd. Semiconductor device and method of fabricating the same
US6495294B1 (en) * 1999-10-28 2002-12-17 Denso Corporation Method for manufacturing semiconductor substrate having an epitaxial film in the trench
US6313019B1 (en) * 2000-08-22 2001-11-06 Advanced Micro Devices Y-gate formation using damascene processing
US20080014725A1 (en) * 2001-02-12 2008-01-17 Asm America, Inc. Deposition over mixed substrates using trisilane
US20040178171A1 (en) * 2001-05-10 2004-09-16 Ranganathan Nagarajan Sloped trench etching process
US20030052088A1 (en) * 2001-09-19 2003-03-20 Anisul Khan Method for increasing capacitance in stacked and trench capacitors
US20040212045A1 (en) * 2003-01-23 2004-10-28 Infineon Technologies Ag Bipolar transistor and method of producing same
US20060189124A1 (en) * 2005-02-10 2006-08-24 Gottfried Beer Semiconductor device having a through contact through a housing composition and method for producing the same
US20060281246A1 (en) * 2005-03-31 2006-12-14 Stefan Tegen Semiconductor having structure with openings
US20080054304A1 (en) * 2005-08-25 2008-03-06 Sadaka Mariam G Semiconductor Device Including a Lateral Field-Effect Transistor and Schottky Diode
US20090301549A1 (en) * 2006-10-09 2009-12-10 Soltaix, Inc. Solar module structures and assembly methods for three-dimensional thin-film solar cells
US20090224363A1 (en) * 2008-03-10 2009-09-10 Hiroshi Yoshida Semiconductor device and manufacturing method thereof
US20100171223A1 (en) * 2009-01-05 2010-07-08 Chen-Cheng Kuo Through-Silicon Via With Scalloped Sidewalls
DE102009032854A1 (en) 2009-07-13 2011-01-27 Texas Instruments Deutschland Gmbh Method for manufacturing bipolar transistor base windows during semiconductor production process, involves implementing corroding process after completion of corroding and isotropic incineration processes such that window edges are formed

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DE102009032854B4 (en) 2015-07-23
US20110165760A1 (en) 2011-07-07
DE102009032854A1 (en) 2011-01-27

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