US7514990B1 - Very low frequency high pass filter - Google Patents
Very low frequency high pass filter Download PDFInfo
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- US7514990B1 US7514990B1 US11/582,906 US58290606A US7514990B1 US 7514990 B1 US7514990 B1 US 7514990B1 US 58290606 A US58290606 A US 58290606A US 7514990 B1 US7514990 B1 US 7514990B1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/003—Changing the DC level
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/56—Modifications of input or output impedances, not otherwise provided for
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
- H03H1/02—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network of RC networks, e.g. integrated networks
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/27—A biasing circuit node being switched in an amplifier circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/54—Two or more capacitor coupled amplifier stages in cascade
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
- H03H7/01—Frequency selective two-port networks
- H03H7/12—Bandpass or bandstop filters with adjustable bandwidth and fixed centre frequency
Definitions
- the present invention relates generally to high pass filters.
- High pass filters pass high frequency signals above a cutoff frequency and attenuate low frequency signals below the cutoff frequency. High pass filters typically cannot achieve very low cutoff frequencies due to diode leakage current.
- a capacitor C HP is connected to an output of Amp 1 , and an input of Amp 2 .
- Resistors R 1 , R 2 , . . . , and R n are connected in parallel to one end of the capacitor C HP and the input of Amp 2 , and to a source node of transistors M 1 , M 2 , . . . , and M n and a cathode of diodes D 11 , D 21 , . . . , and D n1 .
- a source node of transistor M CH is connected to one end of the capacitor C HP and the input of Amp 2 , and to a cathode of diode D o1 .
- a drain node of transistors M 1 , M 2 , . . . , M n , and M CH is connected to a cathode of diodes D 12 , D 22 , . . . , D n2 , and D o2 and to the reference node V REF .
- the anodes of diodes D 11 , D 21 , . . . , D n1 , D 12 , D 22 , . . . , D n2 , D o1 , and D o2 are connected to ground.
- the transistors M 1 , M 2 , . . . , M n , and M CH receive control signals MSW 1 , MSW 2 , . . . , MSW n , and CLK, respectively, which control transistors M 1 , M 2 , . . . , M n , and M CH .
- Transistors M 1 , M 2 , . . . , and M n open or close bias networks 20 of different resistances based on a desired cutoff frequency of the high-pass filter.
- the cutoff frequency represents the frequency at which the output power is half the input power.
- the transistor M CH is controlled by the clock signal CLK and is used to charge the capacitor C HP using voltage V REF during initialization.
- the resistance through paths R 1 , R 2 , . . . , and R n may be too large, thereby increasing a time to charge capacitor C HP .
- the bias network 20 includes an NMOS transistor M 1 fabricated using a twin-well process.
- a resistor R 1 is connected at one end to a communication node V C , and at the other end to a source of the transistor M 1 and a cathode of a diode D 11 .
- the drain of transistor M 1 is connected to a cathode of diode D 12 and a reference node V REF1 .
- Control signal MSW 1 controls the switching of transistor M 1 .
- Anodes of diodes D 11 , D 12 are connected to an anode of diode D 13 .
- a cathode of diode D 13 is connected to a second reference node V REF2 and to a cathode of diode D 14 .
- An anode of diode D 14 is connected to ground.
- a deep n-well 34 is formed in a p-type substrate 32 .
- a p-well 36 is formed in the deep n-well 34 .
- An n+ source region 38 and an n+ drain region 40 are formed in the p-well 36 .
- Diodes D 11 -D 14 are inherent in regions between n-type and p-type regions (i.e. p-n junctions). For example, current flows from the p-type side (the anode) to the n-type side (the cathode).
- a diode D 11 is inherently present in the region 42 between the source 38 and the p-well 36 .
- a diode D 12 is inherently present in the region 44 between the drain 40 and the p-well 36 .
- a diode D 13 is inherently present in the region 46 between the p-well 36 and the deep n-well 34 .
- a diode D 14 is inherently present in the region 48 between the deep n-well 34 and the p-type substrate 32 .
- a variable frequency module controls a cutoff frequency of a high pass filter and includes a resistive element that communicates with a capacitive element of the high pass filter.
- a first transistor communicates with the resistive element and a reference node and includes a first source/drain region formed in a first well region and a first diode region formed between the first source/drain region and the first well region.
- a first node of the first diode region is connected to the first source/drain region and the reference node, and a second node of the first diode region is connected to the reference node.
- the first transistor further includes a first contact region formed in the first well region that is connected to the first source/drain region and the first well region.
- the first transistor further includes a second diode region formed between a second source/drain region and the first well region. A first node of the second diode region is connected to the second source/drain region, and a second node of the second diode region is connected to the second node of the first diode region and the reference node.
- a second transistor communicates with the capacitive element and the reference node and includes a third source/drain region formed in a second well region and a third diode region formed between the third source/drain region and the second well region.
- a first node of the third diode region is connected to the third source/drain region and the reference node, and a second node of the third diode region is connected to the reference node.
- the second transistor further includes a second contact region formed in the second well region that is connected to the third source/drain region and the second well region.
- the second transistor further includes a fourth diode formed between a fourth source/drain region and the second well region.
- a first node of the fourth diode region is connected to the fourth source/drain region, and a second node of the fourth diode region is connected to the second node of the third diode region and the reference node.
- the first transistor and the second transistor are of a twin-well design.
- variable frequency module receives a reference voltage signal.
- the reference node receives the reference voltage signal.
- variable frequency module includes an input signal and an output signal.
- a first node of the capacitive element receives the input signal, a second node of the capacitive element communicates with a communication node of the variable frequency module, and the output signal is generated at the second node of the capacitive element.
- the first transistor receives a program signal.
- the second transistor receives a clock signal.
- a variable frequency module that controls a cutoff frequency of a high pass filter includes a resistive element that communicates with a capacitive element of the high pass filter.
- a transistor includes a source/drain region formed in a well region, a diode region formed between the source/drain region and the well region, and a contact region formed in the well region. The contact region is connected to the source/drain region, the well region, and a reference voltage.
- the resistive element includes N resistors and further the variable frequency module further includes N ⁇ 1 of the transistors. First ends of each of the N resistors are connected together. Second ends of each of the N resistors communicate with a respective one of the N transistors. N is an integer greater than or equal to 2.
- variable frequency module further includes N additional resistive elements and N additional transistors that each include a source/drain region formed in a well region, a diode region formed between the source/drain region and the well region, and a contact region formed in the well region.
- a first end of each of the N additional resistive elements connects to an associated one of the N additional transistors and a second end of each of the N additional resistive elements connects to an adjacent one of the N+1 transistors and wherein N is an integer greater than or equal to 1.
- the transistors are NMOS transistors and/or PMOS transistors.
- a variable frequency module that controls a cutoff frequency of a high pass filter includes resistive means for communicating with a capacitive means for providing a capacitance of the high pass filter.
- First transistor means communicate with the resistive means and a reference node and include a first source/drain region formed in a first well region and a first diode region formed between the first source/drain region and the first well region. A first node of the first diode region is connected to the first source/drain region and the reference node, and a second node of the first diode region is connected to the reference node.
- the first transistor means further includes a first contact region formed in the first well region that is connected to the first source/drain region and the first well region.
- the first transistor means further includes a second diode region formed between a second source/drain region and the first well region. A first node of the second diode region is connected to the second source/drain region, and a second node of the second diode region is connected to the second node of the first diode region and the reference node.
- variable frequency module further includes second transistor means for communicating with the capacitive means and the reference node and includes a third source/drain region formed in a second well region and a third diode region formed between the third source/drain region and the second well region.
- a first node of the third diode region is connected to the third source/drain region and the reference node, and a second node of the third diode region is connected to the reference node.
- the second transistor means further includes a second contact region formed in the second well region that is connected to the third source/drain region and the second well region.
- the second transistor means further includes a fourth diode formed between a fourth source/drain region and the second well region.
- a first node of the fourth diode region is connected to the fourth source/drain region, and a second node of the fourth diode region is connected to the second node of the third diode region and the reference node.
- the first transistor means and the second transistor means are of a twin-well design.
- variable frequency module receives a reference voltage signal.
- the reference node receives the reference voltage signal.
- the variable frequency module also includes an input signal and an output signal.
- a first node of the capacitive means receives the input signal, a second node of the capacitive means communicates with a communication node of the variable frequency module, and the output signal is generated at the second node of the capacitive means.
- the first transistor means receives a program signal.
- the second transistor means receives a clock signal.
- the resistive means includes N resistor means for providing resistances and the variable frequency module further includes N ⁇ 1 transistor means for communicating with respective ones of the N resistor means. Each of the N resistor means are connected together. Second ends of each of the N resistor means communicates with a respective one of the N transistor means. N is an integer greater than or equal to 2.
- variable frequency module further includes N additional resistive means for providing resistances and N additional transistor means for controlling current that flows through the N additional resistive means.
- Each of the N additional transistor means includes a source/drain region formed in a well region, a diode region formed between the source/drain region and the well region, and a contact region formed in the well region.
- a first end of each of the N additional resistive means connects to an associated one of the N additional transistor means and a second end of each of the N additional resistive means connects to an adjacent one of the N+1 transistor means.
- N is an integer greater than or equal to 1.
- Each of the N+1 transistor means implements an NMOS and/or PMOS transistor.
- FIG. 2 is a circuit diagram of a bias network of the high pass filter of FIG. 1 using an NMOS transistor fabricated using a twin-well process;
- FIG. 3 is a cross-sectional diagram of an NMOS transistor fabricated using a twin-well process
- FIG. 4 is a circuit diagram of a high pass filter with a variable frequency control module
- FIG. 5 is a circuit diagram of the variable frequency control module
- FIG. 6 is a circuit diagram of the variable frequency control module
- FIG. 7A is a circuit diagram of the diode connections required to implement the variable frequency module using NMOS technology
- FIG. 7B is a circuit diagram representing the equivalent circuit after the connecting of the diodes of the variable frequency module using NMOS technology
- FIG. 7C is a circuit diagram of the diode connections required to implement the variable frequency module using PMOS technology
- FIG. 7D is a circuit diagram representing the equivalent circuit after the connecting of the diodes of the variable frequency module using PMOS technology
- FIG. 8 is a cross-sectional diagram of an NMOS transistor fabricated using a twin-well process with a diode bypass connection
- FIG. 9 is a cross-sectional diagram of a PMOS transistor fabricated using a twin-well process with a diode bypass connection
- FIG. 10 is a circuit diagram representing the equivalent circuit after the connecting of the diodes of the variable frequency module using PMOS technology of FIG. 9 ;
- FIG. 11A is a functional block diagram of a hard disk drive
- FIG. 11B is a functional block diagram of a digital versatile disk (DVD).
- DVD digital versatile disk
- FIG. 11C is a functional block diagram of a high definition television
- FIG. 11D is a functional block diagram of a vehicle control system
- FIG. 11E is a functional block diagram of a cellular phone
- FIG. 11F is a functional block diagram of a set top box.
- FIG. 11G is a functional block diagram of a media player.
- module, circuit and/or device refers to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described function.
- ASIC Application Specific Integrated Circuit
- processor shared, dedicated, or group
- memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described function.
- phrase at least one of A, B, and C should be construed to mean a logical (A or B or C), using a non-exclusive logical or. It should be understood that steps within a method may be executed in different order without altering the principles of the present disclosure.
- a high-pass filter 50 with amplifiers Amp 1 , Amp 2 , and a variable frequency module 52 is shown.
- a capacitor C HP is connected to an output of Amp 1 and an input of Amp 2 .
- the variable frequency module 52 receives a reference voltage signal V REF , and controls a resistive path of the high-pass filter 50 .
- the variable frequency module 52 allows the high pass filter 50 to achieve a low cutoff frequency based on the connections of the inherent diodes. Normally, diodes D 11 , D 21 , . . . , D n1 , D 12 , D 22 , . .
- variable frequency module 52 connects the anode of diodes D 11 , D 21 , . . . , D n1 , and D o1 to V REF , effectively bypassing diodes D 21 , D 22 , D n2 , and D o2 .
- This connection prevents leakage current from draining capacitor C HP , and helps hold V C by forward biasing diodes D 11 , D 21 , . . . , D n1 , and D o1 using V REF . Therefore, by preventing this leakage current and holding V C , the variable frequency module 52 creates a lower cutoff frequency for the high pass filter 50 .
- a communication node V C is connected to the first ends of resistors R 1 , R 2 , . . . , and R n , the cathode of diode D o1 , and the source of transistor M CH .
- resistors R 1 , R 2 , . . . , and R n those skilled in the art can appreciate that other resistive elements may be used.
- the second ends of resistors R 1 -R n are connected to the sources of transistors M 1 , M 2 , . . . , and M n and the cathodes of diodes D 11 , D 21 , .
- the drains of transistors M 1 , M 2 , . . . , M n , and M CH are connected to the anodes of diodes D 11 , D 21 , . . . , D n1 , D 21 , D 22 , . . . , D n2 , D o1 , and D o2 and to V REF .
- These connections effectively bypass diodes D 21 , D 22 , . . . , D n2 , and D o2 , preventing leakage current from draining V C and holding V C by forward biasing diodes D 11 , D 21 , . . . , D n1 , and D o1 .
- Control signals MSW 1 , MSW 2 , . . . , and MSW n control the various NMOS bias transistors M 1 , M 2 , . . . , and M n , which open paths of different resistances based on the desired cutoff frequency of the high-pass filter.
- a control module (not shown) may send a control signal that opens a path of higher resistance, which creates a lower cutoff frequency.
- the transistor M CH controlled by the clock signal CLK, is used to charge the capacitor C HP using voltage V REF during initialization.
- the resistance through paths R 1 , R 2 , . . . , and R n may be too large, thereby increasing a time to charge capacitor C HP .
- the communication voltage signal V C is high impedance.
- the diodes D 11 , D 21 , . . . , and D n1 , D 12 , D 22 , . . . , and D n2 , D o1 , and D o2 are connected as shown in FIG. 1 , node V C will drain off due to diode leakage current, which creates a higher cutoff frequency than is desired.
- the diodes do not drain current from node V C .
- V REF forward biases the first diodes D 11 , D 21 , . . . , D n1 , and D o1 .
- the first diodes D 11 , D 21 , . . . , D n1 , and D o1 help to maintain the voltage at node V c by supplying current.
- FIG. 6 a circuit diagram of the variable frequency module 52 is shown with resistors R 1 , R 2 , . . . , and R n connected in a series pattern as opposed to the parallel pattern of FIG. 5 .
- Communication node V C is connected to the first end of resistor R 1 and the cathode of diode D o1 , and the source of transistor M CH .
- the first end of resistor R 2 is connected to the second end of resistor R 1 .
- the first end of resistor R n is connected to the second end of resistor R n ⁇ 1 and the second end of resistor R n is connected to the cathode of diode D n1 and the source of transistor M n .
- the remaining elements and their associated connections, and the control signals MSW 1 -MSW n are the same as shown in FIG. 5 .
- FIGS. 7A-7B diode connections for NMOS transistors are shown.
- the connection of the diode D NMOS1 bypasses diode D NMOS2 .
- the equivalent connection is shown after bypassing diode D NMOS2 (see FIG. 7A ).
- Diode D NMOS1 can now be forward biased to help maintain the voltage at capacitor C HP (see FIG. 4 ) by providing leakage current.
- diode connections for PMOS transistors are shown.
- the connection of the diode D PMOS1 bypasses diode D PMOS2 .
- the equivalent connection is shown after bypassing diode D PMOS2 (see FIG. 7C ).
- Diode D PMOS1 can now be reverse biased to help maintain the voltage at capacitor C HP (see FIG. 4 ) by providing reverse leakage current. This PMOS configuration can be used if the twin-well process is not available.
- FIG. 8 a cross-sectional view of an NMOS transistor 54 created using a twin-well process with a diode bypass connection is shown.
- a deep n-well 58 is formed in a p-type substrate 56 .
- a p-well 60 is formed in the deep n-well 58 .
- An n+ source region 62 and an n+ drain region 64 are formed in the p-well 60 .
- a p+ bulk contact 66 is formed in the p-well 60 near the drain region 64 .
- Diodes D 11 -D 14 are inherent in regions between n-type and p-type regions (i.e. p-n junctions).
- a diode D 11 is inherently present in the region 68 between the source 62 and the p-well 60 .
- a diode D 12 is inherently present in the region 70 between the drain 64 and the p-well 60 .
- a diode D 13 is inherently present in the region 72 between the p-well 60 and the deep n-well 58 .
- a diode D 14 is inherently present in the region 74 between the deep n-well 58 and the p-type substrate 56 .
- the p+ bulk contact 66 is connected to the entire p-well 60 .
- the p+ bulk contact 66 By connecting to the entire p-well 60 , current can flow through the less resistive p+ bulk contact 66 to p-well 60 path, as opposed to flowing through the more resistive n+ drain region 64 to p-well 60 path (diode D 12 ). Therefore, by electrically coupling the drain 64 and the p+ bulk contact 66 and connecting to V REF 76 , diode D 12 is effectively bypassed, because the drain 64 is connected to the p-well bulk contact 66 , which is connected to the anodes (the p-well bulk) of diodes D 11 , D 12 , and D 13 .
- FIG. 9 a cross-sectional view of a PMOS transistor 84 created using the twin-well process with a diode bypass connection is shown.
- An n-well 90 is formed in a p-type substrate 88 .
- a p+ source region 92 and a p+ drain region 94 are formed in the n-well 90 .
- An n+ bulk contact 96 is formed in the n-well 90 near the drain region 94 .
- An n+ bulk contact 98 is formed in the n-well 90 near the source region 92 .
- a diode D 31 is inherently present in the region 98 between the source region 92 and the n-well 90 .
- a diode D 32 is inherently present in the region 100 between the drain region 94 and the n-well 90 .
- a diode D 33 is inherently present in a region 102 between the n-well 90 and the p-substrate 88 .
- An anode of a diode D PMOS1 connects to a source of an ideal transistor.
- An anode of a diode D PMOS2 connects to a drain of the ideal transistor.
- Cathodes of diodes D PMOS1 and D PMOS2 are connected to a cathode of a diode D PMOS3 .
- An anode of diode D PMOS3 connects to a reference voltage such as ground.
- Signal MSW PMOS communicates with a gate of the ideal transistor.
- variable frequency module can be implemented in high pass filters of a hard disk drive 400 .
- the variable frequency module may be implemented in either or both signal processing and/or control circuits, which are generally identified in FIG. 5A at 402 .
- the signal processing and/or control circuit 402 and/or other circuits (not shown) in the HDD 400 may process data, perform coding and/or encryption, perform calculations, and/or format data that is output to and/or received from a magnetic storage medium 406 .
- the HDD 400 may communicate with a host device (not shown) such as a computer, mobile computing devices such as personal digital assistants, cellular phones, media or MP3 players and the like, and/or other devices via one or more wired or wireless communication links 408 .
- the HDD 400 may be connected to memory 409 such as random access memory (RAM), low latency nonvolatile memory such as flash memory, read only memory (ROM) and/or other suitable electronic data storage.
- RAM random access memory
- ROM read only memory
- variable frequency module can be implemented in a digital versatile disc (DVD) drive 410 .
- the variable frequency module may be implemented in high pass filters of signal processing and/or control circuits, which are generally identified in FIG. 11B at 412 .
- the signal processing and/or control circuit 412 and/or other circuits (not shown) in the DVD 410 may process data, perform coding and/or encryption, perform calculations, and/or format data that is read from and/or data written to an optical storage medium 416 .
- the signal processing and/or control circuit 412 and/or other circuits (not shown) in the DVD 410 can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive.
- the DVD drive 410 may communicate with an output device (not shown) such as a computer, television or other device via one or more wired or wireless communication links 417 .
- the DVD 410 may communicate with mass data storage 418 that stores data in a nonvolatile manner.
- the mass data storage 418 may include a hard disk drive (HDD).
- the HDD may have the configuration shown in FIG. 11A .
- the HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′.
- the DVD 410 may be connected to memory 419 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.
- variable frequency module can be implemented in high pass filters of a high definition television (HDTV) 420 .
- the device may be implemented in either or both signal processing and/or control circuits, which are generally identified in FIG. 11E at 422 .
- the HDTV 420 receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display 426 .
- signal processing circuit and/or control circuit 422 and/or other circuits (not shown) of the HDTV 420 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.
- the HDTV 420 may communicate with mass data storage 427 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. At least one HDD may have the configuration shown in FIG. 11A and/or at least one DVD may have the configuration shown in FIG. 11B .
- the HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′.
- the HDTV 420 may be connected to memory 428 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.
- the HDTV 420 also may support connections with a WLAN via a WLAN network interface 429 .
- variable frequency module may implement and/or be implemented in high pass filters of a control system of a vehicle 430 .
- the variable frequency module may be implemented in a powertrain control system 432 that receives inputs from one or more sensors such as temperature sensors, pressure sensors, rotational sensors, airflow sensors and/or any other suitable sensors and/or that generates one or more output control signals such as engine operating parameters, transmission operating parameters, and/or other control signals.
- the variable frequency module may also be implemented in other control systems 440 of the vehicle 430 .
- the control system 440 may likewise receive signals from input sensors 442 and/or output control signals to one or more output devices 444 .
- the control system 440 may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc and the like. Still other implementations are contemplated.
- the powertrain control system 432 may communicate with mass data storage 446 that stores data in a nonvolatile manner.
- the mass data storage 446 may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 11A and/or at least one DVD may have the configuration shown in FIG. 11B .
- the HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′.
- the powertrain control system 432 may be connected to memory 447 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.
- the powertrain control system 432 also may support connections with a WLAN via a WLAN network interface 448 .
- the control system 440 may also include mass data storage, memory and/or a WLAN interface (all not shown).
- variable frequency module can be implemented in high pass filters of a cellular phone 450 that may include a cellular antenna 451 .
- the variable frequency module may implement and/or be implemented in either or both signal processing and/or control circuits, which are generally identified in FIG. 11E at 452 .
- the cellular phone 450 includes a microphone 456 , an audio output 458 such as a speaker and/or audio output jack, a display 460 and/or an input device 462 such as a keypad, pointing device, voice actuation and/or other input device.
- the signal processing and/or control circuits 452 and/or other circuits (not shown) in the cellular phone 450 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular phone functions.
- the cellular phone 450 may communicate with mass data storage 464 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 11A and/or at least one DVD may have the configuration shown in FIG. 11B .
- the HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′.
- the cellular phone 450 may be connected to memory 466 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.
- the cellular phone 450 also may support connections with a WLAN via a WLAN network interface 468 .
- variable frequency module can be implemented in high pass filters of a set top box 480 .
- the variable frequency module may implement and/or be implemented in either or both signal processing and/or control circuits, which are generally identified in FIG. 5E at 484 .
- the set top box 480 receives signals from a source such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display 488 such as a television and/or monitor and/or other video and/or audio output devices.
- the signal processing and/or control circuits 484 and/or other circuits (not shown) of the set top box 480 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.
- the set top box 480 may communicate with mass data storage 490 that stores data in a nonvolatile manner.
- the mass data storage 490 may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 11A and/or at least one DVD may have the configuration shown in FIG. 11B .
- the HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′.
- the set top box 480 may be connected to memory 494 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.
- the set top box 480 also may support connections with a WLAN via a WLAN network interface 496 .
- variable frequency module can be implemented in high pass filters of a media player 500 .
- the variable frequency module may implement and/or be implemented in either or both signal processing and/or control circuits, which are generally identified in FIG. 11G at 504 .
- the media player 500 includes a display 507 and/or a user input 508 such as a keypad, touchpad and the like.
- the media player 500 may employ a graphical user interface (GUI) that typically employs menus, drop down menus, icons and/or a point-and-click interface via the display 507 and/or user input 508 .
- the media player 500 further includes an audio output 509 such as a speaker and/or audio output jack.
- the signal processing and/or control circuits 504 and/or other circuits (not shown) of the media player 500 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function.
- the media player 500 may communicate with mass data storage 510 that stores data such as compressed audio and/or video content in a nonvolatile manner.
- the compressed audio files include files that are compliant with MP3 format or other suitable compressed audio and/or video formats.
- the mass data storage may include optical and/or magnetic storage devices for example hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in FIG. 11A and/or at least one DVD may have the configuration shown in FIG. 11B .
- the HDD may be a mini HDD that includes one or more platters having a diameter that is smaller than approximately 1.8′′.
- the media player 500 may be connected to memory 514 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage.
- the media player 500 also may support connections with a WLAN via a WLAN network interface 516 . Still other implementations in addition to those described above are contemplated.
Abstract
Description
Claims (34)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US11/582,906 US7514990B1 (en) | 2006-04-21 | 2006-10-18 | Very low frequency high pass filter |
US12/413,654 US8076969B1 (en) | 2006-04-21 | 2009-03-30 | Apparatus for attenuating low frequency signals |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US79386306P | 2006-04-21 | 2006-04-21 | |
US11/582,906 US7514990B1 (en) | 2006-04-21 | 2006-10-18 | Very low frequency high pass filter |
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US12/413,654 Continuation US8076969B1 (en) | 2006-04-21 | 2009-03-30 | Apparatus for attenuating low frequency signals |
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US7514990B1 true US7514990B1 (en) | 2009-04-07 |
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Application Number | Title | Priority Date | Filing Date |
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US11/582,906 Expired - Fee Related US7514990B1 (en) | 2006-04-21 | 2006-10-18 | Very low frequency high pass filter |
US12/413,654 Expired - Fee Related US8076969B1 (en) | 2006-04-21 | 2009-03-30 | Apparatus for attenuating low frequency signals |
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US12/413,654 Expired - Fee Related US8076969B1 (en) | 2006-04-21 | 2009-03-30 | Apparatus for attenuating low frequency signals |
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US11070049B2 (en) | 2017-11-08 | 2021-07-20 | Eaton Intelligent Power Limited | System, method, and apparatus for power distribution in an electric mobile application using a combined breaker and relay |
US11108225B2 (en) | 2017-11-08 | 2021-08-31 | Eaton Intelligent Power Limited | System, method, and apparatus for power distribution in an electric mobile application using a combined breaker and relay |
US11368031B2 (en) | 2017-11-08 | 2022-06-21 | Eaton Intelligent Power Limited | Power distribution and circuit protection for a mobile application having a high efficiency inverter |
US11670937B2 (en) | 2019-02-22 | 2023-06-06 | Eaton Intelligent Power Limited | Coolant connector having a chamfered lip and fir tree axially aligned with at least one o-ring |
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