US7464246B2 - System and method for dynamic sizing of cache sequential list - Google Patents

System and method for dynamic sizing of cache sequential list Download PDF

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Publication number
US7464246B2
US7464246B2 US10/954,937 US95493704A US7464246B2 US 7464246 B2 US7464246 B2 US 7464246B2 US 95493704 A US95493704 A US 95493704A US 7464246 B2 US7464246 B2 US 7464246B2
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sequential
data list
cache
list
random
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US20060069871A1 (en
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Binny Sher Gill
Dharmendra Shantilal Modha
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International Business Machines Corp
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International Business Machines Corp
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Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GILL, BINNY SHER, MODHA, DHARMENDRA SHANTILAL
Priority to US10/954,937 priority Critical patent/US7464246B2/en
Priority to TW094133273A priority patent/TWI393004B/zh
Priority to CNB2005101070534A priority patent/CN100442249C/zh
Publication of US20060069871A1 publication Critical patent/US20060069871A1/en
Priority to US12/032,851 priority patent/US7509470B2/en
Priority to US12/033,105 priority patent/US7533239B2/en
Priority to US12/060,431 priority patent/US7793065B2/en
Priority to US12/060,945 priority patent/US7707382B2/en
Publication of US7464246B2 publication Critical patent/US7464246B2/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Definitions

  • the present invention relates generally to data caching.
  • Caching is a fundamental technique in hiding delays in writing data to and reading data from storage, such as hard disk drive storage. These delays can be referred to as input/output (I/O) latency. Because caching is effective in hiding I/O latency, it is widely used in storage controllers, databases, file systems, and operating systems.
  • I/O input/output
  • a cache thus may be defined as a high speed memory or storage device that is used to reduce the effective time required to read data from or write data to a lower speed memory or device.
  • a modern storage controller cache typically contains volatile memory used as a read cache and a non-volatile memory used as a write cache.
  • the effectiveness of a read cache depends upon its “hit” ratio, that is, the fraction of requests that are served from the cache without necessitating a disk trip (which represents a “miss” in finding data in the cache).
  • the present invention is focused on improving the performance of a read cache, i.e., increasing the hit ratio or equivalently minimizing the miss ratio.
  • cache is managed in uniformly sized units called pages.
  • demand paging requires a page to be copied into cache from the slower memory (e.g., a disk) only in the event of a cache miss of the page, i.e., only if the page was required by the host and it could not be found in cache, necessitating a relatively slower disk access.
  • cache management is relatively simple, and seeks to intelligently select a page from cache for replacement when the cache is full and a new page is to be stored in cache owing to a “miss”.
  • One well-known policy simply replaces the page whose next access is farthest in the future with the new page.
  • Another policy (least recently used, or LRU) replaces the least recently used page with the new page.
  • the present invention understands that a simpler approach to speculative prefetching can be employed that uses the principle of sequentiality, which is a characteristic of demanded data (data to be read) in which consecutively numbered pages in ascending order without gaps are often required.
  • Sequential file access arises in many contexts, including video-on-demand, database scans, copy, backup, and recovery.
  • detecting sequentiality is easy, requiring very little history information, and can attain nearly 100% predictive accuracy.
  • the present invention critically observes that when synchronous and asynchronous prefetching strategies are used along with the LRU-based caching, and an asynchronous trigger track is accessed, an asynchronous prefetch of the next group of tracks occurs.
  • an LRU-based cache these newly fetched group of tracks along with the asynchronous trigger track are placed at the MRU end of the list, with the unaccessed tracks within the current prefetch group remaining where they were in the LRU list, hence, potentially near the LRU end of the list.
  • the resulting algorithm can violate the so-called stack property, and as a result, when the amount of cache space given to sequentially prefetched data increases, sequential misses do not necessarily decrease.
  • stack property can be a crucial ingredient in proper cache management.
  • both of the above problems can be hidden if (i) only synchronous prefetching is used or (ii) if both synchronous and asynchronous prefetching are used, setting the asynchronous trigger to always be the last track in a prefetched group, but of course the first approach amounts to foregoing all potential benefits of asynchronous prefetching, while the second approach can result in a sequential miss if the track being prefetched is accessed before it is in the cache.
  • one purpose of the present invention is to avoid violation of the stack property without incurring additional sequential misses. More generally, the present invention represents a significant improvement in cache management when sequential prefetch is used.
  • a general purpose computer is programmed according to the inventive steps herein.
  • the invention can also be embodied as an article of manufacture—a machine component—that is used by a digital processing apparatus and which tangibly embodies a program of instructions that is executable by the digital processing apparatus to execute the present logic.
  • This invention may be realized in a critical machine component that causes a digital processing apparatus to perform the inventive method steps herein.
  • a method for caching data includes maintaining a random data list and a sequential data list, and dynamically establishing a desired size for the sequential data list.
  • the establishing act can include determining whether a least recently used (LRU) portion of the sequential data list is more valuable in terms of cache misses than a least recently used (LRU) portion of the random list and if so, increasing the desired size, otherwise decreasing the desired size.
  • the method includes computing a marginal utility of adding space to the sequential data list in terms of sequential misses, and empirically determining a marginal utility of adding space to the random data list. Based on the computing and determining acts, the desired size of the sequential data list is established.
  • the computing act can determine the marginal utility to be equal to a number between s/L and 2 s/L, inclusive, wherein s represents the rate of sequential misses for synchronous and asynchronous prefetching and L represents the length of the sequential data list.
  • the empirically determining act may include determining the number of sequential misses between two successive cache hits in the bottom ⁇ L portion of the random data list. The desired size is increased if the computed marginal utility of adding space to the sequential data list exceeds the empirically determined marginal utility of adding space to the random data list, and otherwise is decreased.
  • the method may further include moving at least one newly prefetched group of tracks along with an asynchronous trigger track in the group of tracks to a most recently used (MRU) portion of the sequential data list.
  • MRU most recently used
  • the method may include moving at least some unaccessed tracks in the group of tracks to the MRU portion of the sequential data list. Also, if desired the method may include determining whether the size of at least a portion of the sequential data list exceeds the desired size, and replacing at least one cache element, based thereon.
  • a data system uses a least recently used (LRU) caching scheme which in turn uses synchronous and asynchronous prefetch of data from a data storage device.
  • LRU least recently used
  • a computer program product includes means for computing a marginal utility of adding space to a sequential list of a cache in terms of sequential misses. Means are also provided for empirically determining a marginal utility of adding space to a random list in cache. The computer program product has means for, responsive to the computing and determining means, establishing a desired size of the sequential list.
  • LRU least recently used
  • a processor is associated with a cache for executing logic to move a newly prefetched group of tracks along with an asynchronous trigger track in the group of tracks to a most recently used (MRU) portion of a sequential cache list.
  • the logic also moves unaccessed tracks in the group of tracks to the MRU portion of the sequential cache list.
  • MRU most recently used
  • a processor associated with a cache executes logic for determining whether the size of a sequential cache list exceeds a desired size, and based thereon, replacing at least one cache element.
  • FIG. 1 is a block diagram of one non-limiting system in which the present cache management policy can be used
  • FIG. 2 is a schematic illustration of the random page list and sequential page list in cache
  • FIG. 3 is a flow chart of the cache size management logic
  • FIG. 4 is a flow chart of the cache replacement logic.
  • FIG. 1 a system is shown, generally designated 10 , that illustrates one non-limiting environment in which the present invention can be used.
  • the present invention is a system for managing a data cache that caches data from a slower memory.
  • the present invention may be implemented in database systems such as DB2 and Oracle, as well as RAID-based systems such as the present assignee's “Shark” system, as well as other systems, such as individual hard disk drives, etc. Accordingly, it is to be understood that while FIG. 1 illustrates one non-limiting implementation that has a “Shark” architecture, it is but representative of the environments that the present invention finds use.
  • the present invention may be implemented in a file system, database system, or other system that must allocate space for variable-sized data objects.
  • the processor or processors (computers) of the present invention may be personal computers made by International Business Machines Corporation (IBM) of Armonk, N.Y., or any computers, including computers sold under trademarks such as AS400, with accompanying IBM Network Stations.
  • IBM International Business Machines Corporation
  • AS400 IBM Network Stations
  • processors 12 may communicate with one or more host computers 14 through an array 16 of host adapters with associated connectors 18 . Also, the processor or processors 12 may communicate with slower storage, such as a RAID-configured disk storage system 20 , through respective device adapters 22 . The processors 12 may have respective non-volatile storages (NVS) 24 for receiving communication from the other processor, as well as a respective, preferably solid state implemented, data cache 26 . One or both processors are programmed to execute the logic herein.
  • NVS non-volatile storages
  • the flow charts and pseudo code herein illustrate the structure of the present logic executed by the processor(s) 12 as embodied in computer program software.
  • the flow charts and pseudo code illustrate the structures of logic elements, such as computer program code elements or electronic logic circuits, that function according to this invention.
  • the invention is practiced in its essential embodiment by a machine component that renders the logic elements in a form that instructs a digital processing apparatus (that is, a computer) to perform a sequence of function steps corresponding to those shown.
  • the flow charts and/or pseudo code may be embodied in a computer program that is executed by a processor as a series of computer-executable instructions. These instructions may reside, for example, in a program storage device of the system 10 .
  • the program storage device may be RAM, or a magnetic or optical disk or diskette, DASD array, magnetic tape, electronic read-only memory, or other appropriate data storage device.
  • the computer-executable instructions may be lines of compiled C/C++ compatible code.
  • each cache 26 has a capacity of eight gigabytes (GB) (per cluster)
  • each NVS 24 has a capacity of two GB (per cluster)
  • four 600 MHz PowerPC/RS64IV CPUs per cluster
  • sixteen RAID-5 (6+parity+spare) arrays with 72 GB, 10K rpm drives may be used in the data storage 20 .
  • An AIX computer can implement the host computer 14 with the following configuration: sixteen GB RAM, two-way SMP with one GHz PowerPC/Power4 CPUs.
  • the host computer 14 may be connected to the processors 12 through two fiber channel cards implementing the host adaptor array 16 .
  • each cache 26 may include two stacked lists, namely, a RANDOM list 28 and a sequential (“SEQ”) list 30 .
  • the random list 28 lists cached pages that may have been randomly accessed pursuant to, e.g., a read demand, while the SEQ list 30 maintains a list of pages that were cached pursuant to speculative sequential caching or sequential read demands, the principles of which are set forth herein.
  • MRU most recently used
  • LRU least recently used
  • a respective portion 32 , 34 of each list at its bottom e.g., 2%, can be thought of as an LRU portion.
  • a desired size 36 of its LRU portion is dynamically determined and adjusted in accordance with the logic set forth below, to optimize cache performance.
  • a newly prefetched group of tracks along with the asynchronous trigger track in the current group of tracks are placed at the MRU (top) end of the SEQ list 30 .
  • all unaccessed tracks in the current group of tracks are also moved to the MRU end of the list 30 , to retain the benefits of asynchronous prefetching while ridding it of the anomalous behavior noted above.
  • the inventive adaptive, self-tuning, low overhead algorithm of the present invention is shown for dynamically partitioning the amount of cache space among the SEQ list 30 and RANDOM list 28 to minimize the overall miss rate.
  • the marginal utility of adding space to the SEQ list 30 is computed.
  • the marginal utility at block 38 is computed to be between s/L and 2 s/L, and may be chosen for convenience to be the latter, wherein “s” represents the rate of misses from sequential cache for synchronous and asynchronous prefetching and “L” represents the length of the SEQ list 30 (e.g., in 4 KB pages).
  • “s” is the sum over potentially multiple streams of the respective rates of sequential cache misses for synchronous and asynchronous prefetching, which is straightforward to observe.
  • This “marginal utility” may be regarded as a measure of how the rate of sequential cache misses changes as the size of the list changes.
  • block 40 shows that the marginal utility of adding space to the RANDOM list 28 is also determined empirically.
  • this marginal utility is determined to be 1/ ⁇ L, wherein ⁇ L is the length of the bottom-most portion of the RANDOM cache 28 during a time period defined by two successive cache hits in the bottom-most portion of the random list 28 .
  • the time period for sampling for undertaking the empirical determination at block 40 may itself be adapted to actual operating conditions, although some fixed time period may also be used.
  • the logic flows to decision diamond 42 to determine which marginal utility is greater. If the marginal utility of increasing the SEQ cache exceeds the marginal utility of increasing the RANDOM cache, the logic increases the desired size 36 ( FIG. 2 ) of the SEQ list 30 at block 44 ; otherwise, it decreases the desired size 36 at block 46 .
  • FIG. 4 shows an exemplary non-limiting logic flow for replacing pages in cache.
  • decision diamond 48 it can be determined whether a boundary condition exists.
  • boundary conditions include the RANDOM list 28 falling below 2% or exceeding 98% of overall cache size. Another boundary condition may exist if the initialization shown in the pseudocode below has not been executed.
  • the logic can flow to decision diamond 50 to determine whether the LRU track in the SEQ list 30 is older than the LRU track in the RANDOM list 28 , it being understood that this test uses timestamps given to cached data in accordance with principles known in the art. If the test at decision diamond 50 is negative, the logic replaces a page from the RANDOM list 28 at block 52 ; otherwise, it replaces from the SEQ list 30 at block 54 .
  • the logic flows to decision diamond 56 to determine whether the size of at least a portion of the SEQ list 30 , e.g., the LRU portion 34 shown in FIG. 2 , exceeds the desired size 36 . If it does, the logic flows to block 54 , and otherwise flows to block 52 .
  • the logic shown in FIG. 3 continuously or periodically loops back to block 38 , such that the desired size of the LRU portion of the SEQ list 30 is dynamically established during operation, changing as cache use dictates.
  • Lines 1 - 3 are used during the initialization phase only.
  • the counter “seqmiss” tracks the number of sequential misses between two consecutive bottom hits in RANDOM, and is initialized to zero.
  • the variable “desiredSeqListSize” is the desired size 36 of the SEQ list 30 , and is initially set to zero meaning a boundary condition initially exists. The remaining logic thus starts only after SEQ is populated (see lines 69 - 73 ).
  • the variable “adapt” determines the instantaneous magnitude and direction of the adaptation to desiredSeqListSize.
  • Lines 4 - 50 describe the cache management policy.
  • the quantity ratio in line 4 can be set to (2*s* ⁇ L)/L in some non-limiting embodiments.
  • line 70 (which carries out the actual adaptation) is executed only when a track is actually evicted from one of the lists.
  • Lines 11 - 27 deal with the case when a track in SEQ is hit. If the hit is in the bottom portion of the SEQ list (line 12 ) and “ratio” has become large (line 13 ), in other words, no hit has been observed in the bottom of the RANDOM list for a while, then “adapt” is set to 1 (line 14 ) meaning that “desiredSeqListSize” is increased at the fastest rate possible. If the hit track is an asynchronous trigger track (line 17 ), then line 18 asynchronously reads ahead the next sequential group of tracks. Lines 21 - 27 describe the implementation of a non-limiting way to detect sequential access patterns.
  • Lines 28 - 40 deal with a cache miss.
  • a sequential miss lines 29 - 31
  • a group of tracks is synchronously read-ahead at line 32 .
  • the remaining lines deal with the detection of sequential access patterns.
  • Lines 41 - 50 (i) read the missing tracks from a given range of tracks; (ii) places all tracks in the given range at the MRU position; and (iii) set the asynchronous trigger.
  • Lines 51 - 73 implement the cache replacement policy of FIG. 4 above and execute out the adaptation. As is typical in multithreaded systems, the present invention assumes that these lines may run on a separate thread (line 51 ). If the size of the free queue drops below some predetermined threshold (line 52 ), then tracks are evicted from SEQ if it exceeds desiredSeqListSize and tracks are evicted from RANDOM otherwise. In either case, the evicted tracks are placed on the free queue. Finally, lines 68 - 73 evict the LRU track from the desired list, and effect an adaption as described above.
  • the present invention combines caching along with sequential prefetching, and does not require a history to be kept.
US10/954,937 2004-09-30 2004-09-30 System and method for dynamic sizing of cache sequential list Expired - Fee Related US7464246B2 (en)

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US10/954,937 US7464246B2 (en) 2004-09-30 2004-09-30 System and method for dynamic sizing of cache sequential list
TW094133273A TWI393004B (zh) 2004-09-30 2005-09-26 用於動態改變快取記憶體順序清單大小之系統以及方法
CNB2005101070534A CN100442249C (zh) 2004-09-30 2005-09-29 用于高速缓存器顺序列表的动态尺寸确定的系统和方法
US12/032,851 US7509470B2 (en) 2004-09-30 2008-02-18 System and method for dynamic sizing of cache sequential list
US12/033,105 US7533239B2 (en) 2004-09-30 2008-02-19 System and method for dynamic sizing of cache sequential list
US12/060,431 US7793065B2 (en) 2004-09-30 2008-04-01 System and method for dynamic sizing of cache sequential list
US12/060,945 US7707382B2 (en) 2004-09-30 2008-04-02 System and method for dynamic sizing of cache sequential list

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US12/033,105 Division US7533239B2 (en) 2004-09-30 2008-02-19 System and method for dynamic sizing of cache sequential list
US12/033,105 Continuation US7533239B2 (en) 2004-09-30 2008-02-19 System and method for dynamic sizing of cache sequential list

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US12/033,105 Expired - Fee Related US7533239B2 (en) 2004-09-30 2008-02-19 System and method for dynamic sizing of cache sequential list
US12/060,431 Expired - Fee Related US7793065B2 (en) 2004-09-30 2008-04-01 System and method for dynamic sizing of cache sequential list
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US12/060,431 Expired - Fee Related US7793065B2 (en) 2004-09-30 2008-04-01 System and method for dynamic sizing of cache sequential list
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US20080140940A1 (en) 2008-06-12
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US20080195834A1 (en) 2008-08-14
US7509470B2 (en) 2009-03-24
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US7707382B2 (en) 2010-04-27
US20080140939A1 (en) 2008-06-12
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US7533239B2 (en) 2009-05-12

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