US7385856B2 - Non-volatile memory device and inspection method for non-volatile memory device - Google Patents
Non-volatile memory device and inspection method for non-volatile memory device Download PDFInfo
- Publication number
- US7385856B2 US7385856B2 US11/087,589 US8758905A US7385856B2 US 7385856 B2 US7385856 B2 US 7385856B2 US 8758905 A US8758905 A US 8758905A US 7385856 B2 US7385856 B2 US 7385856B2
- Authority
- US
- United States
- Prior art keywords
- voltage
- bit line
- volatile memory
- memory device
- cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active, expires
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
Definitions
- the present invention relates to a non-volatile memory device and an inspection method for a non-volatile memory device.
- Flash memories and EEPROMs are known as non-volatile memory devices. Data stored in the non-volatile memory is not deleted even if the power supply is turned off, provided that it is not erased or overwritten.
- FIG. 1 is a circuit diagram partly showing the structure of a conventional non-volatile memory device.
- This non-volatile memory device comprises a current supply circuit 106 , a current supply circuit 107 (including a switch 124 ), a plurality of memory cells 1151 , 1152 (although only two are illustrated in the drawing), a plurality of bit lines 117 (although only one is illustrated in the drawing), a plurality of word lines 1181 , 1182 (although only two are illustrated in the drawing), and a plurality of source lines 119 (although only one is illustrated in the drawing).
- a memory cell array 112 is described as an example. In the memory cell array 112 , memory cells 1151 and 1152 shares the source line 119 .
- the bit lines 117 extend in the Y direction (first direction)
- the word lines 1181 , 1182 extend in the X direction (second direction) which is substantially perpendicular to the Y direction (first direction).
- Memory cells 1151 and 1152 are disposed respectively at the positions where the plurality of bit lines 117 and the plurality of word lines 118 intersect with each other.
- data is written by means of channel hot electrons.
- Channel hot electrons are generated when a predetermined constant current flows between the source and drain of memory cell 1151 and 1152 .
- the non-volatile memory device illustrated in FIG. 1 is a split gate type non-volatile memory device. The control gate of this memory is connected to the word line 118 , the source, to the source line 119 , and the drain, to the bit line 117 .
- the current supply circuit 106 is able to supply a constant current, which is substantially uniform, to the memory cells 1151 and 1152 and its corresponding bit line 117 .
- the current supply circuit 107 supplies a current to the bit line 117 , via the switch 124 .
- a selected bit line 117 s , a selected word line 1181 s and a selected source line 119 s are selected respectively among the plurality of bit lines 117 , the plurality of word lines 118 and the plurality of source lines.
- a selected cell 1151 s is selected among the plurality of memory cells, by means of the selected bit line 117 s and the selected word line 1181 s .
- a voltage VSW source voltage
- VWW gate voltage
- the current supply circuit 106 supplies a predetermined constant current from the selected source line 119 s to the selected bit line 117 s via the source of the selected cell 1151 s and the drain of the selected cell.
- the voltage VBW of the selected bit line (namely, the drain voltage)
- Vth is the threshold voltage of the selected memory cell 1151 s .
- the data is read out from the memory cell 115 as described below.
- a selected bit line 117 s and a selected word line 1181 s are selected respectively among the plurality of bit lines 117 and the plurality of word lines 118 .
- the plurality of source lines 119 are fixed to 0V and are not selected.
- a selected cell 1151 s is selected among the plurality of memory cells on the basis of the selected bit line 117 s and the selected word line 1181 s .
- a voltage VWR gate voltage
- VBR drain voltage
- a sense amplifier (not illustrated) senses the current that flows in the path from the selected bit line 117 s , to the drain of the selected cell 1151 s , the source of the selected cell 1151 s , and the corresponding source line 119 s (0V). Since the current varies depending on the electric charge (stored data) accumulated in the floating gate, then it is therefore possible to read out the data.
- This non-volatile memory device comprises a first and second voltage supply circuits.
- the first voltage supply circuits apply a first voltage to the non-selected memory cells.
- the second voltage supply circuits apply a second voltage to the selected memory cells. The timing of applying first voltage and second voltage is controlled.
- This memory device is provided with a memory cell array in which memory cell units are arranged.
- a ground potential is given to a word line being adjacent to the word line to be written after a potential being larger than 0V is given, and a writing potential is given to the word line to be written.
- a non-volatile memory device comprises a plurality of bit lines extending in a first direction, a plurality of word lines extending in a second direction substantially perpendicular to the first direction, a plurality of memory cells provided respectively so as to correspond to the positions of the intersections between the plurality of bit lines and the plurality of word lines, a plurality of source lines corresponding to a plurality of memory cells which are connected to a same bit line, a current source capable of supplying the constant current to a selected memory cell and the corresponding bit line and a voltage control circuit which keeps a voltage of a selected bit line equal to or higher than a predetermined voltage.
- An inspection method for a non-volatile memory device comprises selecting a selected word line from a plurality of word lines, selecting a selected bit line from a plurality of bit lines, writing data to a selected cell by causing a constant current on the selected cell and the selected bit line in keeping a voltage of the selected bit line equal to or higher than a predetermined voltage and determining whether data is written to the selected cell or not.
- the memory cell which disturbs other memory cells can be detected and screened.
- the reliability of the memory cell is improved.
- FIG. 1 partly shows a composition of a conventional non-volatile memory device
- FIG. 2 is a circuit block diagram showing the composition of an embodiment of the non-volatile memory device according to the present invention
- FIG. 3 partly shows a composition of the non-volatile memory device according to the embodiment of the present invention.
- FIG. 4 is a flow chart showing an embodiment of an inspection method for a non-volatile memory device according to the present invention.
- FIG. 2 is a circuit block diagram showing the structure of a first embodiment of a non-volatile memory device according to the present invention.
- the non-volatile memory device 1 a first X decoder 2 , a second X decoder 3 , a Y decoder 4 , a Y selector 5 , a switch 13 , a voltage control circuit 14 , a plurality of bit lines 17 (in the diagram, only two are depicted), a plurality of word lines 18 (in the diagram, a couple of word lines 181 and 182 is depicted), a plurality of source lines 19 (in the diagram, only one is depicted), a plurality of memory cells 15 (in the diagram, only four 151 and 152 are depicted), a current supply circuit 6 , a current supply circuit 7 , a voltage supply circuit 8 , a voltage supply circuit 9 , a control circuit 10 , a sense amplifier 11 .
- the memory array 12 comprises a plurality of memory cells 15 .
- the bit lines 17 extend in the Y (first) direction. One end of each bit line is connected to the Y selector 5 , and the other end thereof is connected respectively to the current supply circuit 7 .
- the word lines 18 extend in the X direction (second direction), which is substantially perpendicular to the Y direction (first direction). Here, “substantially” means within a certain range of error (the same applies below).
- One terminal of each word line is connected to the first X decoder 2 .
- the source lines 19 extend in the X direction. One end of each source line is connected to the second X decoder 3 .
- the source lines 19 are formed between the memory cells 151 and 152 .
- the memory cells 151 and 152 share the source line, and are connected to the same bit line 17 .
- the source line 19 can be shared by more than two memory cells on the same bit line.
- Memory cells 15 are provided respectively at the positions of the intersections between the plurality of bit lines 17 and the plurality of word lines 18 . These memory cells are non-volatile semiconductor memory cells. Data is written to the memory cells by a predetermined constant current flowing between the drain and the source. When the predetermined constant current flows, the channel hot electrons are generated and injected to a floating gate.
- a split gate type non-volatile memory is depicted as one example of a non-volatile semiconductor memory cell. In each cell, the control gate is connected to a word line 18 , the source is connected to a source line 19 and the drain is connected to a bit line 17 .
- the control gate, source and drain of the memory cell 151 are connected respectively to the word line 181 , the source line 19 and the bit line 17 .
- the control gate, source and drain of the memory cell 152 are connected respectively to the word line 182 , the source line 19 and the bit line 17 .
- the first X decoder 2 selects (activates) one word line 18 ( 181 or 182 ) to be a selected word line 18 ( 181 or 182 ) s, among the plurality of word lines 18 ( 181 and 182 ), based on a control signal from the control circuit 10 .
- the second X decoder 3 selects (activates) one source line 19 to be a selected source line 19 s , among the plurality of source lines 19 , based on a control signal from the control circuit 10 . Alternatively, it selects all of the plurality of source lines 19 .
- the Y decoder 4 decodes the address signal included in the control signal received from the control circuit 10 , and outputs this address signal to the Y selector 5 .
- the Y selector 5 selects (activates) one bit line 17 to be a selected bit line 17 s , among the plurality of bit lines 17 , based on the control signal from the control circuit 10 and the address signal from the Y decoder 4 . Alternatively, it selects all of the plurality of bit lines 17 .
- one memory cell 15 ( 151 or 152 ) is selected as a selected cell 15 ( 151 or 152 ) s among the plurality of memory cells 15 ( 151 and 152 ). If all of the plurality of bit lines 17 are selected, then the memory cells 15 ( 151 or 152 ) on the selected word line 18 s are selected as the selected cells 15 ( 151 or 152 ) s.
- the current supply circuit 6 is able to supply a constant current which is substantially uniform, via the Y selector 5 , to a path from the bit line 17 , to the memory cell 15 , to the source line 19 , on the basis of the control signal from the control circuit 10 .
- the current supply circuit 7 is able to supply a constant current to the bit line 17 on the basis of the control signal from the control circuit 10 .
- the voltage control circuit 14 is able to keep a voltage of bit line 17 equal to or more than a predetermined voltage.
- the voltage control circuit 14 supplies a voltage via the switch 13 , and operates based on the control signal from the control circuit 10 .
- FIG. 3 is a circuit diagram partly showing the structure of a non-volatile memory device of the embodiment. The same reference numerals are applied to the same structure as shown in FIG. 2 .
- the voltage control circuit is connected to the bit line 17 , and connected in parallel to the current supply circuit 6 .
- the voltage control circuit 14 is a clamp circuit which has an N-channel transistor 26 and a power supply 27 .
- the voltage control circuit 14 clamps a voltage of bit line 17 when an external voltage Vdp is applied to the gate of the transistor 26 .
- the clamped voltage is Vdp ⁇ Vtn, where the Vtn is a threshold voltage of the transistor 26 .
- the voltage of the bit line 17 can be controlled by controlling the external voltage Vdp.
- the voltage Vdp ⁇ Vtn of the selected bit line 17 s is controlled to keep a predetermined voltage or higher.
- the predetermined voltage is a voltage that an unintended writing does not occur to the unselected memory cell (in this case, memory cell 152 ), which shares the source line 19 with selected memory cell 151 s.
- the voltage supply circuit 8 is able to apply a predetermined voltage respectively to the word line 18 ( 181 and 182 ), via the first X decoder 2 on the basis of the control signal from the control circuit 10 .
- the voltage supply circuit 9 is able to apply a predetermined voltage respectively to the source line 19 , via the second X decoder 3 on the basis of the control signal from the control circuit 10 .
- the sense amplifier 11 reads out the data stored in the selected cell 15 s based on the current flowing in the selected cell 15 s.
- the control circuit 10 controls the operations of the first X decoder 2 , the second X decoder 3 , the Y decoder 4 , the Y selector 5 , the switch 13 , the current supply circuit 6 , the current supply circuit 7 , the voltage supply circuit 8 , the voltage supply circuit 9 and the sense amplifier 11 .
- a CPU can be used as a control circuit 10 .
- Under the control of the control circuit 10 a write operation, read-out operation, erase operation and screening test are carried out.
- the control circuit 10 controls these operations based on a prescribed program.
- the program may be stored in a storage device, such as a ROM (not illustrated).
- a write operation and read-out operation performed in the non-volatile memory device 1 will be described.
- the operations of the memory cell 151 are described below as an example.
- a data write operation to a memory cell 15 ( 151 and 152 ) is carried out as described below.
- a selected word line 181 s is selected from the plurality of word lines 18 by the first X decoder 2 .
- a selected source line 19 s is selected among the plurality of source lines by the second X decoder 3 .
- a selected bit line 17 s is selected among the plurality of bit lines 17 by the Y selector 5 .
- a selected cell 151 s is selected among the plurality of memory cells 151 , 152 in accordance with the selected bit line 17 s and the selected word line 181 s.
- the voltage supply circuit 9 applies a voltage VSW (source voltage, e.g. 7.5V) to the selected source line 19 s .
- the voltage supply circuit 8 applies a voltage VWW (gate voltage, e.g. 1.5V) to the selected word line 181 s.
- a predetermined constant current flows from the selected source line 19 s to the selected bit line 17 s via the source and the drain of the selected cell 151 s by the current supply circuit 6 .
- the voltage VBW (drain voltage) of the selected bit line is VWW ⁇ Vth.
- Vth is the threshold voltage of the selected cell 15 s .
- data is written to the selected cell 151 s by injecting channel hot electrons into the floating gate. The channel hot electrons are generated by the constant current flowing in the selected cell 151 s.
- the unselected source lines 19 is a floating state
- the unselected word lines 18 are set to 0V
- the unselected bit lines 17 are set to 3.2V.
- a data read-out operation from a memory cell 15 ( 151 and 152 ) is now described with reference to FIG. 2 .
- a selected word line 181 s is selected from the plurality of word lines 18 by the first X decoder 2 .
- a selected bit line 17 s is selected from the plurality of bit lines 17 by the Y selector 5 .
- No source line is selected, and all of the plurality source lines are set to 0V.
- a selected cell 151 s is selected from the plurality of memory cells, in accordance with the selected bit line 17 s and the selected word line 181 s.
- the voltage supply circuit 8 applies a voltage VWR (gate voltage, e.g. 2.5V) to the selected word line 18 s .
- the selected bit line 17 s is set to a voltage VBR (drain voltage, e.g. 0.5V).
- VBR drain voltage, e.g. 0.5V.
- the sense amplifier 11 senses the current flowing from the selected bit line 17 s to selected source line 19 s , via the drain and the source of the selected cell 151 s . In this case, since the amount of the current varies depending on the electric charge (stored data) that has been accumulated in the floating gate of the cell, then the stored data can be read out.
- the unselected word lines 18 and bit lines 17 are set respectively to 0V.
- a selected word line 181 s is selected from the plurality of word lines 18 by the first X decoder 2 .
- the plurality of source lines 19 and the plurality of bit lines 17 are all set to 0V and are not selected. All of the memory cells 15 on the selected word line 18 s are selected as selected cells 15 s.
- the voltage supply circuit 8 applies a voltage VWR (gate voltage, e.g. 12V) to the selected word line 181 s . Consequently, the electrons are extracted from the floating gate, by a Fowler-Nordheim (FN) tunneling effect, and hence the data can be erased.
- VWR gate voltage, e.g. 12V
- FIG. 4 is a flow chart showing the embodiment of the inspection method for a non-volatile memory device according to the present invention.
- a selected bit line 17 s is selected from the plurality of bit lines 17 by the Y selector 5 .
- the voltage control circuit 14 is electrically connected to the selected bit line 17 s via the switch 13 .
- a predetermined voltage Vdp is applied to the transistor 26 of the voltage control circuit 14 .
- a selected word line 181 s is selected from the plurality of word lines 18 by the first X decoder 2 .
- a selected source line 19 s is selected from the plurality of source lines by the second X decoder 3 .
- the selected bit line 17 s is already selected in Step S 01 .
- a selected cell 151 s is selected from the plurality of memory cells, in accordance with the selected bit line 17 s and the selected word line 181 s.
- the voltage supply circuit 9 applies a voltage VSW (source voltage, e.g. 7.5V) to the selected source line 19 s .
- the voltage supply circuit 8 applies a voltage VWW (gate voltage, e.g. 1.5V) to the selected word line 181 s .
- the current supply circuit 6 causes a predetermined constant current to flow from the selected source line 19 s to the selected bit line 17 s , via the source and the drain of the selected cell 151 s .
- the voltage VBW (drain voltage) of the selected bit line 17 s is VWW ⁇ Vth.
- Vth is the threshold voltage of the selected cell 151 s.
- the transistor 26 of the voltage control circuit 14 becomes on-state.
- the voltage of the selected bit line 17 s is clamped at Vdp ⁇ Vtn.
- the constant current flows from the power supply VDD 27 to the current supply circuit 6 via the transistor 26 , and the constant current does not flow into the selected cell 151 s . That is, data is not written to the selected cell 151 s .
- the voltage VBW of the selected bit line 17 s is lower than Vdp ⁇ Vtn.
- This expression means the threshold voltage of the selected cell 151 s is higher than the intended threshold voltage.
- the transistor 26 of the voltage control circuit 14 becomes off-state.
- the selected bit line 17 s is not influenced by the voltage control circuit 14 .
- the constant current flows into the selected cell 151 s , and the data is written to the selected cell 151 s.
- the control circuit 10 determines whether or not data has been written to other memory cells 15 located on the same selected bit line 17 s as the selected cell 151 s . If data is not written to the other cells (Step S 03 : No), then the procedure returns to step S 01 and data writing is continued for the remaining memory cells 15 .
- a selected word line 181 s is selected from the plurality of word lines 18 by the first X decoder 2 . No source line 19 is selected, and the ground voltage (0V) is applied to all the source lines 19 .
- the selected bit line 17 s is already selected in Step S 01 .
- a selected cell 151 s is selected from the plurality of memory cells, in accordance with the selected bit line 17 s and the selected word line 181 s . The read out operation as described above is performed to the selected cell 151 s.
- the control circuit 10 determines whether or not data has been written to the selected cell 151 s , on the basis of the read out data. That is, the control circuit 10 judges whether or not data has been written to the selected cell 151 s in the writing operation of Step S 02 .
- Step S 04 If data has been written to the selected cell 15 s (Step S 04 : Yes), then that selected cell 151 s is taken to have passed the screening test, and the control circuit 10 outputs a signal indicating a pass.
- Step S 04 If no data has been written to the selected cell 15 s , (Step S 04 : No), then that selected cell 151 s is taken not to have passed the disturb test, and the control circuit 10 outputs a signal indicating a failure.
- the control circuit 10 determines whether or not the inspection in steps S 04 -S 07 has been completed for all of the memory cells 15 on the selected bit line 17 s selected at step S 01 . If it has not been completed (Step S 08 : No), then the procedure returns to step S 04 and inspection is continued for the remaining memory cells 15 .
- the control circuit 10 determines whether or not the inspection in steps S 01 -S 08 has been completed for all of the bit lines 17 relating to the memory cell array 12 under inspection. If inspection has been completed (Step S 09 : No), then the procedure returns to step S 01 and inspection is continued for the memory cells 15 on the remaining bit lines 17 .
- the inspection method is carried out by means of the steps S 01 -S 09 described above.
- the threshold voltage of the selected cell 151 s is high, the difference between drain voltage and source voltage of the non-selected cell, which shares the source line with the selected cell, is increased. The unintended writing may occur to the non-selected cell 15 . In this case, data is properly written to the selected cell 15 which has higher threshold voltage. Therefore, It is difficult to detect the memory cell 15 which has higher threshold voltage in a screening test which test a writing error. According to the inspection method for non-volatile memory device of the present invention, if the threshold voltage of the selected cell 151 s is high, the writing operation is not performed properly. Therefore, the memory cell which has higher threshold voltage can be detected in the screening test.
- the memory cell which disturbs other memory cells, which share the source line with this memory cell can be detected, and be screened.
- the reliability of the memory cell is improved.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
Abstract
Description
Claims (21)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-089503 | 2004-03-25 | ||
JP2004089503A JP4346482B2 (en) | 2004-03-25 | 2004-03-25 | Nonvolatile memory device and method for verifying nonvolatile memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050213418A1 US20050213418A1 (en) | 2005-09-29 |
US7385856B2 true US7385856B2 (en) | 2008-06-10 |
Family
ID=34989637
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/087,589 Active 2025-04-26 US7385856B2 (en) | 2004-03-25 | 2005-03-24 | Non-volatile memory device and inspection method for non-volatile memory device |
Country Status (2)
Country | Link |
---|---|
US (1) | US7385856B2 (en) |
JP (1) | JP4346482B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090097323A1 (en) * | 2006-03-16 | 2009-04-16 | Freescale Semiconductor, Inc. | Bitline current generator for a non-volatile memory array and a non-volatile memory array |
US9818489B2 (en) | 2016-03-25 | 2017-11-14 | Renesas Electronics Corporation | Semiconductor memory device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5754482A (en) * | 1996-08-23 | 1998-05-19 | Motorola, Inc. | Memory using undecoded precharge for high speed data sensing |
US5761125A (en) * | 1994-08-10 | 1998-06-02 | Kabushiki Kaisha Toshiba | Cell threshold value distribution detection circuit and method of detecting cell threshold value |
US5852578A (en) * | 1997-06-17 | 1998-12-22 | Hoang; Loc B. | Flash cell having self-timed programming |
US5912842A (en) * | 1995-11-14 | 1999-06-15 | Programmable Microelectronics Corp. | Nonvolatile PMOS two transistor memory cell and array |
US5986940A (en) * | 1997-02-27 | 1999-11-16 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with a constant current source |
US6097638A (en) * | 1997-02-12 | 2000-08-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
JP3198998B2 (en) | 1997-09-11 | 2001-08-13 | 日本電気株式会社 | Semiconductor nonvolatile memory |
US6441428B1 (en) * | 2001-03-19 | 2002-08-27 | Micron Technology, Inc. | One-sided floating-gate memory cell |
JP2004014052A (en) | 2002-06-10 | 2004-01-15 | Toshiba Corp | Nonvolatile semiconductor memory device |
US20040196695A1 (en) * | 2003-04-04 | 2004-10-07 | Renesas Technology Corp. | Nonvolatile memory device and semiconductor device |
-
2004
- 2004-03-25 JP JP2004089503A patent/JP4346482B2/en not_active Expired - Fee Related
-
2005
- 2005-03-24 US US11/087,589 patent/US7385856B2/en active Active
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5761125A (en) * | 1994-08-10 | 1998-06-02 | Kabushiki Kaisha Toshiba | Cell threshold value distribution detection circuit and method of detecting cell threshold value |
US5912842A (en) * | 1995-11-14 | 1999-06-15 | Programmable Microelectronics Corp. | Nonvolatile PMOS two transistor memory cell and array |
US5754482A (en) * | 1996-08-23 | 1998-05-19 | Motorola, Inc. | Memory using undecoded precharge for high speed data sensing |
US6097638A (en) * | 1997-02-12 | 2000-08-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US5986940A (en) * | 1997-02-27 | 1999-11-16 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit device with a constant current source |
US5852578A (en) * | 1997-06-17 | 1998-12-22 | Hoang; Loc B. | Flash cell having self-timed programming |
JP3198998B2 (en) | 1997-09-11 | 2001-08-13 | 日本電気株式会社 | Semiconductor nonvolatile memory |
US6441428B1 (en) * | 2001-03-19 | 2002-08-27 | Micron Technology, Inc. | One-sided floating-gate memory cell |
JP2004014052A (en) | 2002-06-10 | 2004-01-15 | Toshiba Corp | Nonvolatile semiconductor memory device |
US20040196695A1 (en) * | 2003-04-04 | 2004-10-07 | Renesas Technology Corp. | Nonvolatile memory device and semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090097323A1 (en) * | 2006-03-16 | 2009-04-16 | Freescale Semiconductor, Inc. | Bitline current generator for a non-volatile memory array and a non-volatile memory array |
US8077521B2 (en) | 2006-03-16 | 2011-12-13 | Freescale Semiconductor, Inc. | Bitline current generator for a non-volatile memory array and a non-volatile memory array |
US9818489B2 (en) | 2016-03-25 | 2017-11-14 | Renesas Electronics Corporation | Semiconductor memory device |
US10204690B2 (en) | 2016-03-25 | 2019-02-12 | Renesas Electronics Corporation | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
JP2005276347A (en) | 2005-10-06 |
US20050213418A1 (en) | 2005-09-29 |
JP4346482B2 (en) | 2009-10-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10032517B2 (en) | Memory architecture having two independently controlled voltage pumps | |
US7272049B2 (en) | Nonvolatile semiconductor memory device having uniform operational characteristics for memory cells | |
KR100381804B1 (en) | Nonvolatile semiconductor memory device and method of erasing data of nonvolatile semiconductor memory device | |
US6515908B2 (en) | Nonvolatile semiconductor memory device having reduced erase time and method of erasing data of the same | |
JP3652453B2 (en) | Semiconductor memory device | |
US7251161B2 (en) | Semiconductor device and method of controlling said semiconductor device | |
EP1077450A2 (en) | NAND type nonvolatile memory | |
US5844847A (en) | Method and Nonvolatile semiconductor memory for repairing over-erased cells | |
KR100215762B1 (en) | Non-volatile semiconductor memory device and method for verifying operationg of the same | |
US20030133327A1 (en) | Nonvolatile semiconductor storage device having a shortened time required for a data erasing operation and data erasing method thereof | |
KR100297669B1 (en) | Semiconductor storage, with the ability to perform sweeping pie-fire operations in aggregate for all memory cells | |
US20050213363A1 (en) | Non-volatile memory device and inspection method for non-volatile memory device | |
KR100924377B1 (en) | Accurate verify apparatus and method for nor flash memory cells in the presence of high column leakage | |
KR20090026502A (en) | Operating method of flash memory device | |
US20030043629A1 (en) | Nonvolatile semiconductor memory device that can suppress effect of threshold voltage variation of memory cell transistor | |
US7385856B2 (en) | Non-volatile memory device and inspection method for non-volatile memory device | |
KR20120069115A (en) | Semiconductor memory device and method for operating thereof | |
JP2735498B2 (en) | Non-volatile memory | |
JPH11176173A (en) | Nonvolatile semiconductor storage device | |
US7031194B2 (en) | Nonvolatile semiconductor memory and method for controlling the same | |
JPH1055697A (en) | Non-volatile semiconductor memory | |
KR100276947B1 (en) | Current control circuit and non-volatile semiconductor memory device having the same | |
JP3133675B2 (en) | Semiconductor storage device | |
JP3544222B2 (en) | Nonvolatile semiconductor memory device | |
JP2006216196A (en) | Nonvolatile semiconductor memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: NEC ELECTRONICS CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OGA, HIROFUMI;KASHIMURA, MASAHIKO;AMANAI, MASAKAZU;REEL/FRAME:016410/0295 Effective date: 20050315 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:025346/0859 Effective date: 20100401 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF ADDRESS;ASSIGNOR:RENESAS ELECTRONICS CORPORATION;REEL/FRAME:044928/0001 Effective date: 20150806 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 12 |