US7277479B2  Reconfigurable fir filter  Google Patents
Reconfigurable fir filterInfo
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 US7277479B2 US7277479B2 US10248920 US24892003A US7277479B2 US 7277479 B2 US7277479 B2 US 7277479B2 US 10248920 US10248920 US 10248920 US 24892003 A US24892003 A US 24892003A US 7277479 B2 US7277479 B2 US 7277479B2
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 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
 H03H17/00—Networks using digital techniques
 H03H17/02—Frequency selective networks
 H03H17/0294—Variable filters; Programmable filters
Abstract
Description
1. Field of the Invention
The present invention relates to digital signal processing, and more specifically, to a programmable digital finite impulse response (FIR) filter.
2. Description of the Prior Art
Finite impulse response (FIR) filters are important components in digital communications systems. Much effort has been made to improve filter performance, reduce hardware, and increase operating speed. In addition, software radios, such as those introduced in J. Mitola, “The Software Radio Architecture,” IEEE Communications Magazine, vol. 33, pp. 2638, May 1995 or E. Buracchini, “The Software Radio Concept,” IEEE Communications Magazine, vol. 38, pp. 138143, September 2000, have recently gained much attention due to the need for integrated and reconfigurable communications systems. To this end, reconfigurability has become an important issue for future filter design.
FIR filters can be used to perform a wide variety of tasks such as spectral shaping, matched filtering, noise rejection, channel equalization, etc. Hence, various architectures and implementation methods have been proposed to improve the performance of filters with respect to speed and complexity. However, due to the recent explosive proliferation in wired and wireless communication standards, traditional hardwired devices may be less suitable for future communication needs.
On the other hand, software radio has gained much attention from researchers worldwide due to a strong demand for reconfigurable communication systems capable of performing multistandard operations. In light of this trend, programmability and reconfigurability need be taken into account in filter architecture design.
A typical Ntap FIR filter can be described by:
where,
y[n] is a filtered digital signal, n being an index of elements of the signal;
h_{i }is a filtering coefficient; and
x is an unfiltered digital signal.
It is well known in the art that a canonical signed digit (CSD) representation can be used to reduce the complexity of a digital FIR filter implementation as in R. M. Hewlitt and E. S. Swartzlantler Jr., “Canonical Signed Digit Representation for FIR Digital Filters,” in Proc. of IEEE Workshop on Signal Processing Systems, 2000, pp.416426; M. Tamada and A. Nishihara, “HighSpeed FIR Digital Filter with CSD Coefficients Implemented on FPGA,” in Proc. of the ASPDAC, 2001, pp. 78; and Y. M. Hasan, L. J. Karem, M. Falkinburg, A. Helwig, and M. Ronning, “Canonic Signed Digit Chebyshev FIR Filter Design,” IEEE Signal Processing Letters, vol. 8, pp. 167169, June 2001, for example. Encoding filter coefficients using a CSD representation reduces the number of partial products and thus saves silicon area and power consumption in hardware implementation. Hence, this technique has been popular for fixedcoefficient implementation of FIR filters. According to the CSD representation:
where,
d_{i,k }is an element of the set {1, 0, −1};
p_{k }is an element of the set {0, . . . , L}, where L+1 is the length of the coefficients;
and
M_{i }is the number of nonzero digits in h_{i}.
When applying the CSD representation to implementing programmable, rather than fixedcoefficient, FIR filters, it is only natural to implement the same number of programmable CSDs for each filter coefficient to maintain regularity. However, for most filters, only a few taps require highprecision coefficients. Valuable hardware resources will be wasted if all taps are implemented with the highest precision. To minimize hardware complexity, programmable FIR filters restricting the number of allowable nonzero CSDs in every tap have been proposed in T. Zhangwen, Z. Zhanpeng, Z. Jie, and M. Hao, “A HighSpeed, Programmable, CSD Coefficient FIR Filter,” in Proc. of 4th International Conference on ASIC, 2001, pp.397400; and in K. T. Hong, S. D. Yi, and K. M. Chung, “A HighSpeed Programmable FIR Digital Filter Using Switching Arrays,” in Proc. of IEEE Asia Pacific Conference on Circuits and Systems, 1996, pp. 492495. Unfortunately, this restriction may lower the coefficient precision and degrade the frequency response of the filter, and it may also induce a large overhead by assigning more CSDs than necessary to most taps. Another hardwareefficient implementation of programmable FIR filters with CSD coefficients has been presented in K. Y. Khoo, A. Kwentus, and A. N. Willson Jr., “A Programmable FIR Digital Filter Using CSD Coefficients,” IEEE Journal of SolidState Circuits, vol. 31, pp. 869874, June 1996. This implementation includes a 32tap linearphase filter with two nonzero CSDs in each tap. Additional nonzero CSDs can be allocated to specific filter taps, making it a reconfigurable FIR filter architecture. Nevertheless, some computational resources can still be unused and the critical path can be quite longin some cases.
Another state of the art programmable FIR filter is taught by Willson, Jr. et al. in U.S. Pat. No. 5,479,363, which is included herein by reference. Consider
Generally, the prior art programmable FIR filters suffer from drawbacks of program inflexibility, speed, precision range, and critical path dependence on precision.
It is therefore a primary objective of the present invention to provide a highly flexible, reconfigurable FIR filter in which both a tap number and a number of nonzero digits in each tap can be arbitrarily assigned, and in which critical path is independent of coefficient precision.
Briefly summarized, a digit processing unit (DPU) for providing a CSD coefficient to a FIR filter according to the present invention includes a register, a multiplexer, a coefficient multiplier, and an adder. The register is connected to an input node and stores and delays an input digital signal to be filtered. The multiplexer has inputs connected to the input node and to an output of the register, an output of the multiplexer is for connecting to a second DPU. The coefficient multiplier is connected to the output of the register and multiplies the input digital signal by a CSD coefficient and outputs a product. The adder is connected to the coefficient multiplier and adds the product to products of other DPUs, the output of the adder being a component of the filtered digital signal.
According to a preferred embodiment of the present invention, DPUs are connected in series to form a FIR filter, and a group of DPUs can have multiplexers set so that the register of each DPU stores the same part of the digital signal for processing a single filter coefficient. Additionally, the adders of the DPUs are consolidated into a single optimized adder.
A method according to the present invention for filtering an input digital signal according to a function defined by a series of coefficients is also provided. The method serially receives the input digital signal as a series of equal length elements, then, simultaneously multiplies each element of the serially received digital signal by a corresponding coefficient of the series of coefficients, and further adds the products of the multiplications, before finally outputting the sum of the products of the multiplications as the filtered digital signal.
It is an advantage of the present invention that the multiplexers allow DPUs to be combined to process coefficients having a wide range of precisions in the same FIR filter.
It is a further advantage of the present invention that the critical path is a coefficient multiplier and an optimized consolidated adder and is independent of an amount of DPUs processing a single coefficient, that is, coefficient precision or number of digits.
It is a further advantage of the present invention that the FIR filter can be easily configured as a matched filter, a pulseshaping filter, or other filters.
It is a further advantage of the present invention that the FIR filter has scalability, modularity, and cascadability amenable to VLSI implementation.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
A generalized digit processing unit (DPU) 10 according to the present invention is illustrated in
The coefficient multiplier 16 is programmed with a unit set of canonical signed digits (CSDs) of a filter coefficient, the advantages of using CSDs having been explained previously. For instance, the unit set of CSDs can be a single CSD. When the filter coefficient comprises a single CSD, the multiplexer 16 is set to receive input from the register 12 thereby delaying output to the next stage DPU, which processes another filter coefficient. However, when the CSD representation of the coefficient comprises two CSDs, the multiplexer 16 is set to combine the DPU 10 with the next stage DPU (by forwarding the undelayed input digital signal) such that two coefficient multipliers operate on the same input digital signal data to realize a two CSD coefficient. In this way, one or more CSDs can be realized with a single or a series of DPUs 10.
Referring to Eqn. 3 and Table 1, the multiplier 36 is set with the multiplicand d_{i,k}, the zero bit indicating a zero value and the plus bit indicating a positive value. The shifter 37 is set to evaluate the multiplicand 2^{−p} ^{ k },
the three shift bits being a binary representation of p_{k}. Working in conjunction, the multiplier 3 and shifter 37 evaluate a single CSD multiplication, that is, the term
d_{i,k}·2^{−p} ^{ k }·x[n−i]
of Eqn. 3.
TABLE 1  
d_{i,k}  zero  plus 
0  1  0 
−1  0  0 
1  0  1 
As mentioned with reference to Table 1, the multiplier 36 is used to multiply the input data x[n−i] by d_{i,k}, which can have values of “1”, “0”, and “1”. If d_{i,k }is “0, the zero signal will be “1” forcing the output of the multiplier 36 to be “0” regardless of input. Otherwise, the zero signal will be 0″ and if the CSD coefficient is 1, the plus signal will be “1” and the multiplier output is the same as the input. If the CSD coefficient, d_{i,k}, is “−1”, the plus signal will be “0” and the output is equivalent to the one's complement representation of the input data. The “1 ” required to form the two's complement can be added by the multiplier 36 or, as in the preferred embodiment, accumulated and later added into a summed filter output when the DPU 30 is incorporated into a filter.
The shifter 37 is used to multiply the output of the multiplier 36 d_{i,k}x[n−i] by 2^{−p} ^{ k },
where p_{k }ranges from “0” to “7”. In the preferred embodiment, the shifter 37 performs an arithmetic left shift and expands the 7bit multiplier output (excluding the most significant bit—MSB) into a 14bit output by shifting the input left by 7−p_{k }
bits. Zeros are padded at the least significant bit (LSB) if d_{i,k }is “1 or 0” and ones are padded if d_{i,k }is −1″.
Please refer to
Refer to
The sign extension generator 56 is required as the accumulated sum at the adder 52 has a longer bit length than the addend output of each DPU 30. For power saving reasons, it is better to handle sign extension bits of the DPUs 30 individually rather than extend the addends of the DPUs 30 to the bit length of the adder 52. The sign extension generator 56 evaluates the sum of the sign extension bits based on the sign signals of the DPUs 30 by examining relations between the number of nonnegative sign signals and the sum of the corresponding sign extension bits.
Suppose, for example, that each DPU 30 used in the processing element 50 processes 8bit data with 8bit filter coefficients so as to produce a 15bit output (a 14bit addend signal and a 1bit sign signal, referring to
Continuing the example above, the adder 52 sums eight 14bit addend signals from the eight DPUs 30, one 24bit accumulated sum at the register 54, and the 10bit sign extension signal. The adder 52 includes five 14bit full adder arrays in a twolevel arrangement that compress the fourteen LSBs of the accumulated sum at the register 54 and the eight addend signals into four 14bit signals. A twolevel carry save adder is provided to add the ten MSBs at the register 54, the sign extension signal, and the above four 14bit signals. The adder 52 further comprises an ELM adder, such as in T. P. Kelliher, R. M. Owens, M. J. Irwin, and T. T. Hwang, “ELMA Fast Addition Algorithm Discovered by a Program,” IEEE Transactions on Computers, vol. 41, pp.11811184, September 1992, modified to reduce the critical path delay and compute the final sum.
It can be seen in
In practical application, the present invention can be implemented with single poly quadruplemetal 0.35μm CMOS technology. In accordance with the abovementioned example of eight DPUs 30 processing 8bit signal data, measurement results have shown that a fabricated chip consumes 16.5 mW of power when operating at 86 MHz under 2.5V.
In contrast to the prior art, the present invention has a critical path including a coefficient multiplier and an optimized consolidated adder that is independent of coefficient precision or number of digits. Furthermore, the present invention DPUs can be combined to process coefficients having a wide range of precisions in the same configurable FIR filter or processing element, and such a FIR filter is thus scalable, modular, cascadable, and well suited to VLSI implementation.
Those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention.
Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (10)
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US20080109506A1 (en) *  20061024  20080508  HungLun Chien  Data Transformation Method and Data Transformation Circuit Capable of Saving Numeral Operations 
KR100947084B1 (en)  20080428  20100310  엘아이지넥스원 주식회사  Finite impulse response filter and method of signal processing by using it 
US9893714B2 (en)  20150901  20180213  Nxp Usa, Inc.  Configurable FIR filter with segmented cells 
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Cited By (4)
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US20080109506A1 (en) *  20061024  20080508  HungLun Chien  Data Transformation Method and Data Transformation Circuit Capable of Saving Numeral Operations 
US7849118B2 (en) *  20061024  20101207  Princeton Technology Corporation  Data transformation method and data transformation circuit capable of saving numeral operations 
KR100947084B1 (en)  20080428  20100310  엘아이지넥스원 주식회사  Finite impulse response filter and method of signal processing by using it 
US9893714B2 (en)  20150901  20180213  Nxp Usa, Inc.  Configurable FIR filter with segmented cells 
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