KR100947084B1  Finite impulse response filter and method of signal processing by using it  Google Patents
Finite impulse response filter and method of signal processing by using it Download PDFInfo
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 KR100947084B1 KR100947084B1 KR1020080039366A KR20080039366A KR100947084B1 KR 100947084 B1 KR100947084 B1 KR 100947084B1 KR 1020080039366 A KR1020080039366 A KR 1020080039366A KR 20080039366 A KR20080039366 A KR 20080039366A KR 100947084 B1 KR100947084 B1 KR 100947084B1
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Abstract
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The present invention relates to a finite impulse response filter and a signal processing method using the same. More specifically, it is used for pulse compression for signal detection in pulse compression radar, has excellent scalability according to increasing order of the filter, and does not delay signal processing time and the signal processing method using the same It is about.
Radar systems are systems that measure the distance and speed of a target using radio waves. Among the various types of radars used in the radar system, the pulse radar has been recently spotlighted because it has the advantage of being able to determine the distance, direction, and relative speed of the target.
The pulse radar operates by the principle of making and copying a short pulse radio wave to the transmitter and analyzing the information of the returned signal to identify the characteristics of the detection object. The type of pulse radar uses pulse waves without modulation. It can be divided into an unmodulated pulse radar and a pulse compression radar that compresses and transmits a pulse.
The measurable distance of the radar is proportional to the output power of the transmitted radio waves, and in the case of a pulse radar, the output power can be expressed as the product of the maximum power and the pulse width.
In this case, the increase of the maximum power, which is one of the methods for increasing the output power of the transmitting radio wave, requires a high voltage power supply device, and the use of such a high voltage power supply device impairs the size and stability of the radar. There is a problem that is large and inefficient in terms of cost and high cost.
Therefore, a method of increasing the pulse width of a transmitting radio wave is mainly used as a method for increasing the output power of the transmitting radio wave, rather than increasing the maximum power.
The method of increasing the output width of the transmitting radio wave by increasing the pulse width also has a problem of lowering the resolution within the detection range of the radar. However, the problem is a transmission pulse modulating a frequency for a wide pulse. By using, it is possible to obtain a desired measurement distance without sacrificing detection resolution and signaltonoise ratio (SNR).
As such, frequency modulation is performed on the wide pulse to perform pulse compression by using correlation between the transmitted signal and the received signal.
Pulse compression may be performed using a batch processing method using a fast Fourier transform (FFT) and a real time processing method using a matched filter.
A finite impulse response (FIR) filter is mainly used as a matching filter used in the dual realtime processing technique. Here, the finite impulse response filter is a type of digital filter, and the impulse response of the filter has a finite length and can accurately specify the linear phase response.
1 is a block diagram of a conventional finite impulse response filter for pulse compression radar.
As shown in FIG. 1, an input and output relation of a finite impulse response filter having an nth order filter is expressed by Equation 1 below.
Equation 1
From here,
x (k), x (k1), x (kn), x (ki) are input signals, y (k) is output signals, w _{i} , w _{0} , w _{1} , w _{n} are filter coefficients .
In the conventional finite impulse response filter, Equation 1 is directly implemented when n + 1 signal inputs are sequentially performed. In other words, implementation of Equation 1 is performed by sequentially adding a plurality of result values multiplied by an input signal and a filter coefficient corresponding to the input signal.
In this case, n + 1 multipliers and n adders are used to implement a finite impulse response filter having norder filter order having an inputoutput relation as shown in Equation 1, and the time required for calculating the final output value from the first input signal. Is the same as Equation 2 below.
Equation 2
From here,
T _{o} is the time required for the final output, T _{p} is the time at which the multiplication calculation of the filter components is completed, T _{S} is the time at which the addition calculation of the filter components is completed, and n is the order of the filter.
In the conventional finite impulse response filter for pulse compression radar as shown in Equation 2, since the time required from the first input of the input signal to the final output of the output value is proportional to the order n of the filter, the final value of the output value increases with the filter order. There was a problem that the output time is delayed.
In addition, if the output is not calculated before the next input, it must go through as many buffering steps as needed. In other words, when the order of the filter is increased, the output time delay is increased by the increased order, and there is a problem in that the configuration of the adders constituting the filter is increased by the order of the increased filter in the overall structure.
In addition, as the input speed increases, the processing time may be relatively shortened, and thus the output time may be delayed.
The present invention has been made to solve the above problems, and is used for pulse compression for signal detection in a pulse compression radar, and has excellent scalability according to the increase of the order of the filter, and at the same time, there is no delay in signal processing time. An object of the present invention is to provide an impulse response filter and a signal processing method using the same.
The finite impulse filter according to the present invention for achieving the above object performs a sum operation of the first operation result value and the initial value according to the multiplication of the input signal and the first filter coefficients and outputs the result value according to the sum operation A first unit filter; And performing a second operation on the result of multiplying the input signal with the second filter coefficient and the result of the sum operation received from the first unit filter, and calculating the result value according to the sum operation. And a second unit filter to output.
In addition, a signal processing method according to the present invention for achieving the above object comprises the steps of: a) performing a multiplication of the received input signal and the first filter coefficients; b) performing a sum operation of the resultant value and the initial value according to the multiplication operation; c) outputting a result value according to the sum operation; d) performing a multiplication of the received input signal with a second filter coefficient; e) performing a sum operation of the result value according to the multiplication operation in step d) and the result value according to the sum operation in step c); And f) outputting a result of the sum operation in step e).
According to the present invention, it is possible to easily expand the configuration to increase the number of the second unit filter having a simple structure of the adder and the adder when the order of the filter is increased, so the expandability is excellent, and the filter order is increased or the input signal is introduced. Since the delay of output signal calculation does not occur due to the increase in speed, high speed processing is possible.
In addition, since it can be used as a matched filter for realtime processing of the pulse compression process required in the operation of the pulse compression radar, a device for a field compression gate array (FPGA) for a pulse compression radar using the finite impulse response filter of the present invention. It is possible to implement the effect.
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are assigned to the same components as much as possible, even if shown on different drawings. In addition, in describing the present invention, when it is determined that the detailed description of the related wellknown configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, preferred embodiments of the present invention will be described below, but the technical idea of the present invention may be implemented by those skilled in the art without being limited or limited thereto.
2 is a block diagram of a finite impulse response filter in accordance with a preferred embodiment of the present invention.
As shown in FIG. 2, the finite impulse response filter 1 according to the preferred embodiment of the present invention includes a first unit filter 10 and a second unit filter 20a, 20b, 20c, and 20d.
X (k) is an input signal, W _{n} is a first filter coefficient, 0 is an initial value, W _{0} , W _{1} , W _{n} _{2} , and W _{n1} is a second filter coefficient, Z _{0} (k), Let Z _{1} _{(} k), Z _{2} (k), Z _{n} _{1} (k), Z _{n} (k), and y (k) be output values.
The first unit filter 10 may include a first input terminal 12 receiving the input signal, a first multiplier 13 performing a multiplication of the input signal with a first filter coefficient, and a first multiplication according to the multiplication operation. A first adder 14 performs a sum operation of the operation result value and the initial value, and a first storage unit 15 outputs the result value according to the sum operation.
The second unit filters 20a, 20b, 20c, and 20d are second input terminals 22a, 22b, 22c, and 22d that receive the input signal, and a second multiplier in which a multiplication of the input signal and the second filter coefficient is performed. (23a, 23b, 23c, 23d), the second operation result value according to the multiplication operation and the sum operation result value transmitted from the first unit filter 10 or the previous second unit filter 20a, 20b, 20c, and Second adders 24a, 24b, 24c, and 24d for performing a summation operation, and second storage units 25a, 25b, 25c, and 25d for outputting a result value according to the summation operation.
At this time, the input signal is simultaneously received by the first input terminal 12 of the first unit filter 10 and the second input terminals 22a, 22b, 22c, 22d of the second unit filters 20a, 20b, 20c, and 20d. It is preferable that this be done.
The operation process of the finite impulse response filter 1 according to the preferred embodiment of the present invention is as follows.
Simultaneous input of an input signal is performed to the first input terminal 12 and the second input terminals 22a, 22b, 22c, and 22d. The input signal inputted to the first input terminal 12 is multiplied by the first filter coefficient of the first unit filter 10 by the first multiplier 13, and then the first operation according to the multiplication operation. The result value is transmitted to the first adder 14, and the first adder 14 performs the sum operation of the first operation result value and the initial value.
The result of the sum operation performed by the first unit filter 10 is transmitted to the second adder 24a of the second unit filter 20a via the first storage unit 15.
A second operation according to the multiplication operation after performing a multiplication operation of the input signal input to the second input terminal 22a and the second filter coefficient of the second unit filter 20a by a second multiplier 23a The resultant value is transmitted to the second adder 24a, and the second adder 24a performs a sum operation between the second operation result value and the result value according to the sum operation received from the first unit filter 10.
The result of the sum operation performed by the second unit filter 20a is transmitted to the second adder 24b of the second unit filter 20b through the second storage unit 25a.
Since the operation process of the second unit filters 20b, 20c, and 20d is the same as that of the second unit filter 20a, it is omitted. Finally, the second unit filter 20d performs the second adder 24d of the second unit filter 20d. The result of the sum operation is transmitted to the outside through the output terminal 26 through the second storage unit 25d.
As described above, the finite impulse response filter 1 according to the preferred embodiment of the present invention transmits the result of the first unit filter 10 to the second adder 24a of the second unit filter 20a, and the second It is preferable to perform processing for each of the result values in a serial configuration in which the result value of the unit filter 20a is transmitted to the second adder 24b of the second unit filter 20b.
3 is a flowchart illustrating a signal processing method according to a preferred embodiment of the present invention. As shown in FIG. 3, the signal processing method according to the preferred embodiment of the present invention includes the following steps performed in time series in the finite impulse response filter 1.
In S10, the first multiplier 13 performs a multiplication of the input signal with the first filter coefficients of the first unit filter 10.
In S20, the first adder 14 performs a sum operation of the first operation result value and the initial value according to the multiplication operation.
In operation S30, the first storage unit 15 outputs a result value according to the sum operation.
At this time, it is preferable that the output of the result value according to the sum operation is made up of the second adder 24a of the second unit filter 20a.
In operation S40, the second multiplier 23a multiplies the input signal with the second filter coefficients of the second unit filter 20a.
In S50, the second adder 24a performs a sum operation of the second operation result value according to the multiplication operation of S40 and the result value according to the sum operation of the output in S30.
When the second storage unit 25a outputs the result value according to the sum operation of S50 in S60, the termination is completed.
In this case, it is preferable that the input signals in S10 and S40 are simultaneously received, and the finite impulse response filter 1 of the present invention increases the number of second unit filters 20a according to the increased filter order. Since the filter can be implemented according to the increased filter order, it is preferable to repeatedly perform the steps S40 to S60 by the number of the increased second unit filters.
For example, in the case of the finite impulse response filter 1 composed of four second unit filters 20a, 20b, 20c, and 20d as shown in FIG. 2, the S40 to S60 are repeatedly performed four times. It is desirable to output the result.
The relation between the input signal and the output signal according to the operation of the finite impulse response filter 1 of the present invention is represented by Equation 3 below.
Equation 3
Where x (k) is the input signal, W _{0} , W _{1} , W _{n} _{2} , W _{n} _{1} , W _{n} is the filter coefficient, Z _{0} (k), Z _{1 (} k), Z _{2} (k) , Z _{n} _{2} (k), Z _{n} _{1} (k), y (k) is the output value, n is the order of the filter.
As in Equation 3, the n + 1 th output value Z _{n} (k) in the finite impulse response filter (1) of the present invention is a result of n multiplication between the input signal x (k) and the filter coefficient W _{o} and n. Equation 3 represents the input and output relation of the finite impulse response filter because the sum of the resultant values according to the sum of the first output value Z _{n} _{} _{1} (k).
The finite impulse response filter of the present invention is composed of a combination of a first unit filter and a second unit filter having a basic configuration of a multiplier and an adder, and processes the result values of the first unit filter and the second unit filters in a serial manner. Even if the order of the finite impulse response filter is increased, the number of the second unit filters can be simply increased, thereby achieving excellent scalability.
In addition, the finite impulse response filter of the present invention is composed of a combination of the first unit filter and the second unit filter composed of the basic configuration of the multiplier and the adder, so that the calculation time is very fast, the output of the final value even if the inflow speed of the input signal increases There is no delay.
In addition, since it can be used as a matched filter for realtime processing of the pulse compression process for pulse compression radar, it is possible to implement a field programmable gate array (FPGA) for pulse compression radar.
The above description is merely illustrative of the technical idea of the present invention, and various modifications, changes, and substitutions may be made by those skilled in the art without departing from the essential characteristics of the present invention. It will be possible. Accordingly, the embodiments disclosed in the present invention and the accompanying drawings are not intended to limit the technical spirit of the present invention, but to describe the present invention, and the scope of the present invention is not limited to these embodiments and the accompanying drawings. The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.
According to the present invention, the processing time of the filter does not decrease depending on the order of the filter or the inflow rate of the input signal, and can be easily extended even if the order of the filter increases, so that the higherorder asymmetric finite impulse response digital used for radar pulse compression is used. It is possible to use the filter in the field of implementing field programmable gate array (FPGA) devices.
1 is a block diagram of a conventional finite impulse response filter for pulse compression radar,
2 is a block diagram of a finite impulse response filter in accordance with a preferred embodiment of the present invention, and
3 is a flowchart of a signal processing method according to a preferred embodiment of the present invention.
<Brief description of the main parts of the drawings>
(1): finite impulse response filter (10): first unit filter
(12): first input stage (13): first multiplier
14: first adder 15: first storage unit
(20a, 20b, 20c, 20d): second unit filter
(22a, 22b, 22c, 22d): second input terminal
(23a, 23b, 23c, 23d): second multiplier
(24a, 24b, 24c, 24d): second adder
(25a, 25b, 25c, 25d): Second storage section 26: Output stage
Claims (7)
 A first unit filter performing a sum operation of the first operation result value and the initial value according to the multiply operation of the input signal and the first filter coefficient and outputting the result value according to the sum operation; AndPerforming a second operation on the result of the multiplication of the input signal with the second filter coefficient and the result of the sum operation received from the first unit filter, and outputting the result of the sum operation A finite impulse response filter comprising a second unit filter.
 The method of claim 1,Performing a sum operation of the third operation result value according to the multiplication operation of the input signal and the third filter coefficient and the result value according to the sum operation received from the second unit filter, and outputting the result value according to the sum operation The finite impulse response filter further comprises a third unit filter.
 The method of claim 1,The input signal is,Finite impulse response filter, characterized in that the simultaneous reception to the first unit filter and the second unit filter.
 The method of claim 1,The first unit filter,A first multiplier for performing a multiplication of the input signal and a first filter coefficient, a first adder for performing a sum operation of the first operation result value and an initial value, and And a first storage unit for outputting a result value according to the sum operation.
 The method of claim 1,The second unit filter,A second multiplier for multiplying the input signal with a second filter coefficient, a result value according to the sum operation received from the second operation result value and the first unit filter; And a second adder for performing a summation with and a second storage unit for outputting a result value according to the summation.
 a) performing a multiplication of the received input signal with the first filter coefficients;b) performing a sum operation of the resultant value and the initial value according to the multiplication operation;c) outputting a result value according to the sum operation;d) performing a multiplication of the received input signal with a second filter coefficient;e) performing a sum operation of the result value according to the multiplication operation in step d) and the result value according to the sum operation in step c); Andf) outputting a result value for the summation operation in step e).
 The method of claim 6,The signal processing method, characterized in that the input signal of step a) and d) is received at the same time.
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US6556044B2 (en)  20010918  20030429  Altera Corporation  Programmable logic device including multipliers and configurations thereof to reduce resource utilization 
US6584481B1 (en)  19990721  20030624  Xilinx, Inc.  FPGA implemented bitserial multiplier and infinite impulse response filter 
JP2004236319A (en)  20030128  20040819  Agere Systems Inc  Multidimension hybrid type and transposition type finite time impulse response filter 
US7277479B2 (en)  20030302  20071002  Mediatek Inc.  Reconfigurable fir filter 

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Patent Citations (4)
Publication number  Priority date  Publication date  Assignee  Title 

US6584481B1 (en)  19990721  20030624  Xilinx, Inc.  FPGA implemented bitserial multiplier and infinite impulse response filter 
US6556044B2 (en)  20010918  20030429  Altera Corporation  Programmable logic device including multipliers and configurations thereof to reduce resource utilization 
JP2004236319A (en)  20030128  20040819  Agere Systems Inc  Multidimension hybrid type and transposition type finite time impulse response filter 
US7277479B2 (en)  20030302  20071002  Mediatek Inc.  Reconfigurable fir filter 
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