US7117425B2 - Decoder architecture for reed solomon codes - Google Patents
Decoder architecture for reed solomon codes Download PDFInfo
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- US7117425B2 US7117425B2 US10/251,776 US25177602A US7117425B2 US 7117425 B2 US7117425 B2 US 7117425B2 US 25177602 A US25177602 A US 25177602A US 7117425 B2 US7117425 B2 US 7117425B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1545—Determination of error locations, e.g. Chien search or other methods or arrangements for the determination of the roots of the error locator polynomial
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/1525—Determination and particular use of error location polynomials
- H03M13/153—Determination and particular use of error location polynomials using the Berlekamp-Massey algorithm
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/13—Linear codes
- H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
- H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
- H03M13/158—Finite field arithmetic processing
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- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
Description
{αIr0, αIr0+1, αIr0+2, . . . , αIr0+r−1},
where Ir0 is an arbitrary logarithm in base α of the first root. In transmission or storage, some of the codeword symbols may be corrupted when received at the decoder.
A(z)=ΣA i z i
In
B (i+1)(z)←zB i(z)
indicates that the B coefficients are updated in a shifting operation,
B 0 (i+1)=0,B 1 (i+1) =B 0 i ,B 2 (i+1) =B 1 i , . . . , B r (i+1) =B (r−1) i
and the notation
U (i+1)(z)←ROTATED [U i(z)]
indicates that the U coefficients are updated in a shifting operation, with the highest degree coefficient shifting to the lowest degree,
Λ(α−i)=0
implies that the codeword symbol with index n−1−i is in error, where n is the number of symbols in the codeword. When Λ(α−1)=0, the codeword symbol with index n−1−i is corrected by adding the error value,
e (n−1−i)=α(−i)(r+lr0−1)/((B(α−i)Λodd(α−1))
where Λodd(z) is the polynomial obtained from Λ(z) by deleting all terms with even powers of z. When lr0 is chosen so that r+lr0−1 is the multiplicative order of α in the Galois field, the formula simplifies to
e (n−1−i)=1/((B(α−i)Λodd(α−i)
B(z)=z p A(z).
e (n−1−i)=α(−i)(r+lr0−1)/((α−ip A(α−i)Λodd(α−i))
=α(−i)(r+lr0−1−p)/((A(α−i)Λodd(α−i))
B (i+1)(z)←ROTATED [B i(z)]
function. In this function, the modified B′(z) is zB(z), where the highest order term, if it overflows, is shifted back to the lowest order slice, setting the accompanying o(z) flag.
Λ(i+1)(z)←Λi(z)+ΔB (i+1)(z),
which is loaded in
U (i+1)(z)←ROTATED [U i(z)]
one of the terms of which is loaded in
((Δ≠0) AND (2j<=i))
in
B (i+1)(z)←Λi(z).
in a field of characteristic 2 like GF(256). This accomplishes the function
B (i+1)(z)←ΦB (i+1)(z)
in
TABLE 1 |
Comparison of Slice Efficiency |
Feng | | ||
Area |
3 |
1 |
|
3 symbol registers | 3 symbol registers | |
1 |
1 symbol adder | |
5 symbol multiplexers | 8 symbol multiplexers | |
(~1,270 gates) | (628 gates) | |
Delay per |
2 |
|
1 |
||
1 |
3 |
|
2 |
||
1 |
3 |
|
1 |
3 register setups | |
(~16 ns) | (~16.8 ns) | |
Product of Delay * Area | 20,320 | 10,550 |
where o1 is 0 or 1, and neither polynomial has a constant term. The storage of a constant term for the polynomial B(z) is not required, because initialization of B(z) is performed by the
B (i+1)(z)←ROTATED [B i(z)]
indicates that the coefficients are updated in a shifting operation, with the highest degree coefficient shifting to the coefficient of z,
APPENDIX A |
Example Single and Dual Multipliers in Verilog |
Description: multiply by alpha**1003 = alpha**(−20) in GF(1024) | ||
module mula1003(inp, outp); | ||
input [9:0] inp; | ||
output [9:0] outp; | ||
reg [9:0] outp; | ||
always @(inp) | ||
begin | ||
outp[0] = inp[1] {circumflex over ( )} inp[4] {circumflex over ( )} inp[5] {circumflex over ( )} inp[7]; | ||
outp[1] = inp[0] {circumflex over ( )} inp[1] {circumflex over ( )} inp[4] {circumflex over ( )} inp[6] {circumflex over ( )} inp[7]; | ||
outp[2] = inp[3] {circumflex over ( )} inp[6] {circumflex over ( )} inp[7] {circumflex over ( )} inp[9]; | ||
outp[3] = inp[2] {circumflex over ( )} inp[3] {circumflex over ( )} inp[6] {circumflex over ( )} inp[8] {circumflex over ( )} inp[9]; | ||
outp[4] = inp[1] {circumflex over ( )} inp[4] {circumflex over ( )} inp[7] {circumflex over ( )} inp[8] {circumflex over ( )} inp[9]; | ||
outp[5] = inp[0] {circumflex over ( )} inp[1] {circumflex over ( )} inp[5] {circumflex over ( )} inp[6] {circumflex over ( )} inp[7] {circumflex over ( )} inp[8]; | ||
outp[6] = inp[0] {circumflex over ( )} inp[1] {circumflex over ( )} inp[3] {circumflex over ( )} inp[6] {circumflex over ( )} inp[9]; | ||
outp[7] = inp[0] {circumflex over ( )} inp[2] {circumflex over ( )} inp[3] {circumflex over ( )} inp[7] {circumflex over ( )} inp[8] {circumflex over ( )} inp[9]; | ||
outp[8] = inp[2] {circumflex over ( )} inp[3] {circumflex over ( )} inp[5] {circumflex over ( )} inp[8]; | ||
outp[9] = inp[2] {circumflex over ( )} inp[4] {circumflex over ( )} inp[5] {circumflex over ( )} inp[9]; | ||
end | ||
endmodule | ||
Description: multiply by alpha**1003 or alpha**(983) in GF(1024) | ||
Note that common terms are labelled cm and shared | ||
p0 are remaining terms for alpha**1003, p1 are remaining for | ||
alpha**(983) | ||
module duala1003or983(inp, select, outp); | ||
input [9:0] inp; | ||
input select; | ||
output [9:0] outp; | ||
reg [9:0] outp; | ||
reg [9:0] p0; | ||
reg [9:0] p1; | ||
reg [9:0] cm; | ||
always @(inp) | ||
begin | ||
p0[0] = inp[4] {circumflex over ( )} inp[7]; | ||
p0[1] = inp[1] {circumflex over ( )} inp[6] {circumflex over ( )} inp[7]; | ||
p0[2] = inp[6] {circumflex over ( )} inp[9]; | ||
p0[3] = inp[3] {circumflex over ( )} inp[8] {circumflex over ( )} inp[9]; | ||
p0[4] = inp[1]; | ||
p0[5] = inp[0] {circumflex over ( )} inp[1] {circumflex over ( )} inp[7]; | ||
p0[6] = inp[0] {circumflex over ( )} inp[3]; | ||
p0[7] = inp[2] {circumflex over ( )} inp[3] {circumflex over ( )} inp[9]; | ||
p0[8] = inp[2] {circumflex over ( )} inp[5]; | ||
p0[9] = inp[4] {circumflex over ( )} inp[5]; | ||
p1[0] = inp[0] {circumflex over ( )} inp[2] {circumflex over ( )} inp[3] {circumflex over ( )} inp[8]; | ||
p1[1] = inp[2] {circumflex over ( )} inp[5] {circumflex over ( )} inp[9]; | ||
p1[2] = inp[1] {circumflex over ( )} inp[2] {circumflex over ( )} inp[4] {circumflex over ( )} inp[5]; | ||
p1[3] = inp[0] {circumflex over ( )} inp[1] {circumflex over ( )} inp[4] {circumflex over ( )} inp[7]; | ||
p1[4] = inp[2] {circumflex over ( )} inp[6]; | ||
p1[5] = inp[3]; | ||
p1[6] = inp[4] {circumflex over ( )} inp[8]; | ||
p1[7] = inp[1] {circumflex over ( )} inp[5]; | ||
p1[8] = inp[0] {circumflex over ( )} inp[1] {circumflex over ( )} inp[6]; | ||
p1[9] = inp[0] {circumflex over ( )} inp[3] {circumflex over ( )} inp[7]; | ||
cm[0] = inp[1] {circumflex over ( )} inp[5]; | ||
cm[1] = inp[0] {circumflex over ( )} inp[4]; | ||
cm[2] = inp[3] {circumflex over ( )} inp[7]; | ||
cm[3] = inp[2] {circumflex over ( )} inp[6]; | ||
cm[4] = inp[4] {circumflex over ( )} inp[7] {circumflex over ( )} inp[8] {circumflex over ( )} inp[9]; | ||
cm[5] = inp[5] {circumflex over ( )} inp[6] {circumflex over ( )} inp[8]; | ||
cm[6] = inp[1] {circumflex over ( )} inp[6] {circumflex over ( )} inp[9]; | ||
cm[7] = inp[0] {circumflex over ( )} inp[7] {circumflex over ( )} inp[8]; | ||
cm[8] = inp[3] {circumflex over ( )} inp[8]; | ||
cm[9] = inp[2] {circumflex over ( )} inp[9]; | ||
end | ||
Claims (15)
Priority Applications (2)
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US10/251,776 US7117425B2 (en) | 2002-09-23 | 2002-09-23 | Decoder architecture for reed solomon codes |
US11/505,451 US20070011592A1 (en) | 2002-09-23 | 2006-08-17 | Decoder architecture for Reed Solomon codes |
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US10/251,776 US7117425B2 (en) | 2002-09-23 | 2002-09-23 | Decoder architecture for reed solomon codes |
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US11/505,451 Continuation US20070011592A1 (en) | 2002-09-23 | 2006-08-17 | Decoder architecture for Reed Solomon codes |
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US7117425B2 true US7117425B2 (en) | 2006-10-03 |
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US11/505,451 Abandoned US20070011592A1 (en) | 2002-09-23 | 2006-08-17 | Decoder architecture for Reed Solomon codes |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US20100011277A1 (en) * | 2008-07-10 | 2010-01-14 | Poeppelman Alan D | Adjustable error-correction for a reed solomon encoder/decoder |
TWI514778B (en) * | 2014-03-27 | 2015-12-21 | Storart Technology Co Ltd | Method and circuit for shortening latency of chien's search algorithm for bch codewords |
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US7814398B2 (en) * | 2006-06-09 | 2010-10-12 | Seagate Technology Llc | Communication channel with Reed-Solomon encoding and single parity check |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US6119262A (en) * | 1997-08-19 | 2000-09-12 | Chuen-Shen Bernard Shung | Method and apparatus for solving key equation polynomials in decoding error correction codes |
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2002
- 2002-09-23 US US10/251,776 patent/US7117425B2/en not_active Expired - Fee Related
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Publication number | Priority date | Publication date | Assignee | Title |
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US6119262A (en) * | 1997-08-19 | 2000-09-12 | Chuen-Shen Bernard Shung | Method and apparatus for solving key equation polynomials in decoding error correction codes |
Non-Patent Citations (7)
Title |
---|
Arambepola et al., VLSI array architecture for Reed Solomon decoding, Nov. 1991, IEEE, p. 2963-2966. * |
Choomchuary et al., Tine domain algorithm and architectures for Reed Solomon decoding, Jun. 1993, IEEE Proceedings-1, vol. 140, No. 3, p. 189-196. * |
Elwyn Belekamp, Algebraic Coding Theory, 1968. |
J.L. Massey, Shift Register Synthesis and BCH Coding, IEEE Transactions on Information Theory, vol. IT-15, No. 1, 1969, pp. 122-127. |
Toshio Horiguchi, High Speed Coding of BCH Codes Using a New Error-Evaluation Algorithm, Electronics and Communications in Japan, Part 3, vol. 72, No. 12, 1989. |
Weishi Feng, On Decoding Reed-Solomon Codes up to and Beyond the Packing Radii, P.H.D. Thesis, University of Illinois at Urbana-Champaign, 1999. |
Yu-xin et al., Design and implementation of high speed Reed Solomon decoders, Jun. 2002, IEEE, p. 146-149. * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100011277A1 (en) * | 2008-07-10 | 2010-01-14 | Poeppelman Alan D | Adjustable error-correction for a reed solomon encoder/decoder |
US8151172B2 (en) * | 2008-07-10 | 2012-04-03 | Lsi Corporation | Adjustable error-correction for a reed solomon encoder/decoder |
TWI514778B (en) * | 2014-03-27 | 2015-12-21 | Storart Technology Co Ltd | Method and circuit for shortening latency of chien's search algorithm for bch codewords |
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US20070011592A1 (en) | 2007-01-11 |
US20040059990A1 (en) | 2004-03-25 |
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