US6963079B2 - Semiconductor calculation device - Google Patents

Semiconductor calculation device Download PDF

Info

Publication number
US6963079B2
US6963079B2 US10/488,925 US48892504A US6963079B2 US 6963079 B2 US6963079 B2 US 6963079B2 US 48892504 A US48892504 A US 48892504A US 6963079 B2 US6963079 B2 US 6963079B2
Authority
US
United States
Prior art keywords
arithmetic
qubit
computing device
states
processor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US10/488,925
Other languages
English (en)
Other versions
US20040266084A1 (en
Inventor
Minoru Fujishima
Shin-ichi O'Uchi
Koichiro Hoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
Original Assignee
Japan Science and Technology Agency
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Science and Technology Agency filed Critical Japan Science and Technology Agency
Assigned to JAPAN SCIENCE AND TECHNOLOGY AGENCY reassignment JAPAN SCIENCE AND TECHNOLOGY AGENCY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: O'UCHI, SHIN-ICHI, FUJISHIMA, MINORU, HOH, KOICHIRO
Publication of US20040266084A1 publication Critical patent/US20040266084A1/en
Application granted granted Critical
Publication of US6963079B2 publication Critical patent/US6963079B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S977/00—Nanotechnology
    • Y10S977/902—Specified use of nanostructure
    • Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
    • Y10S977/933—Spintronics or quantum computing

Definitions

  • the present invention relates to a semiconductor computing device, and is particularly suitable for use in a semiconductor computing device that simultaneously executes arithmetic operations for all logical values expressed by the number of bits operable in the semiconductor computing device.
  • Integration density (the number of elements (the number of transistors) that can be integrated) in an integrated circuit is growing exponentially according to “Moore's Law” saying that integration density is doubled every about one year and a half. With this increase in integration density, it is becoming possible to integrate on one semiconductor chip (hereinafter, simply referred to as a “chip”) circuits each constituted of a large number of circuit elements that have been thought to be impossible in prior arts to integrate on one chip.
  • a large-scale arithmetic operation has become executable in an integrated circuit of a semiconductor computing device such as a CPU, but since a conventionally adopted computational method (algorithm) is used in which computational processing, condition/branch processing, and so on are executed sequentially, using one data value, the time for the arithmetic operation increases in accordance with the scale of the arithmetic operation, which has posed a problem that a large-scale arithmetic operation is not executable at high speed.
  • a conventionally adopted computational method algorithm
  • the present invention is made in order to solve such problems, and an object thereof is to make it possible to execute a large-scale arithmetic operation at high speed without any increase in the time and effort required for designing an integrated circuit for a large-scale arithmetic operation.
  • a semiconductor computing device of the present invention is a semiconductor computing device configured to simultaneously execute arithmetic operations for states of all logical values expressable by (N+1) bits (N is a natural number) and retain results of the respective arithmetic operations, comprising: two N-qubit arithmetic circuit groups each having a plurality of arithmetic circuits and being configured to simultaneously execute arithmetic operations for states of all logical values expressable by N bits and retain results of the arithmetic operations; and an N th -qubit switch circuit for exchange of the states of the logical values between the two N-qubit arithmetic circuit groups.
  • FIG. 1 is a block diagram showing an example of the configuration of a parallel processor to which a semiconductor computing device according to an embodiment of the present invention is applied;
  • FIG. 2 is a block diagram showing an example of the configuration of a processor element
  • FIG. 3 is a block diagram showing an example of the configuration of an arithmetic part in the processor element in detail
  • FIG. 4 is a block diagram showing an example of the configuration of an exchange unit.
  • FIG. 5 is a view for explaining a method of constituting a semiconductor computing device that executes an arithmetic operation equivalent to an arbitrary number of qubits.
  • FIG. 1 is a block diagram showing an example of the configuration of a parallel processor to which a semiconductor computing device according to an embodiment of the present invention is applied.
  • a quantum computer technology is realized in a parallel processor 1 shown in FIG. 1 , using an integrated circuit.
  • the quantum computer is a new computational method that utilizes the superposition of states based on quantum mechanics constituted of units of qubits (quantum bits), and was proposed by Feynman as a new computer model.
  • quantum computer one device is used to execute an arithmetic operation utilizing the superposition of the states based on quantum mechanics, and therefore, theoretically, one-time arithmetic operations for all the possible states (data possible to exist as values) can give results of the arithmetic operations for all the aforesaid possible states simultaneously and instantly.
  • the quantum computer utilizes the superposition of the states based on quantum mechanics, it has been realized only in a physical system in which phenomena based on quantum mechanics are actually observable, for example, physical systems in which nuclear magnetic resonance, microwave, and laser are used, so that large-scale equipment is required.
  • an actual physical system in which 2 5 states exist simultaneously and up to 5 qubits are operable has been proposed in the quantum computer.
  • the quantum computer uses an actual physical system in which phenomena based on quantum mechanics are observable, it needs a complicated work of providing an interface for the exchange of data such as results of the arithmetic operations with an existing electronic circuit, and connectability thereof to the electronic circuit is poor.
  • quantum computer utilizes quantal physical phenomena (the superposition of the states based on quantum mechanics)
  • quantum computer utilizes classical physical phenomena (classical electromagnetics), as it is.
  • classical physical phenomena classical electromagnetics
  • a plurality of devices on an integrated circuit to respectively store a plurality of states superposed based on quantum mechanics and to execute arithmetic operations simultaneously for the stored states based on quantum mechanics.
  • the aforesaid parallel processor 1 shown in FIG. 1 is configured such that a plurality of processor elements (PE) are provided on an integrated circuit, and the plural processor elements store a plurality of states (probability amplitudes of logical values) superposed based on quantum mechanics respectively and simultaneously execute arithmetic operations.
  • the probability amplitude of a logical value is hereinafter referred to as a “state” for convenience of explanation.
  • the parallel processor 1 has the plural processor elements (PE) (represented by ⁇ drawn by the solid line in FIG. 1 ) and a plurality of exchange units (EU) (represented by ⁇ in FIG. 1 ).
  • PE processor elements
  • EU exchange units
  • each of the processor elements executes a predetermined arithmetic operation (unitary conversion) for one state out of the 32 states based on the plural states and stores the obtained result of the arithmetic operation.
  • each of the exchange units connects two processor elements to each other, or connects two processor element groups each constituted of the plural processor elements, to each other so that they can communicate with each other, and controls data exchange and so on between the processor elements or between the processor element groups.
  • the processor elements and the exchange units will be described later in detail.
  • a processor element 2 - 1 and a processor element 2 - 2 are connected via an exchange unit 3 - 1 in an H-shape arrangement. Consequently, a processor element group 4 - 1 that executes an arithmetic operation equivalent to one qubit is constituted.
  • a processor element group 4 - 2 that has the same structure as that of the processor element group 4 - 1 and the processor element group 4 - 1 are connected via an exchange unit 3 - 2 in an H-shape arrangement. Consequently, a processor element group 5 - 1 that executes an arithmetic operation equivalent to 2 qubits is constituted.
  • processor element group 5 - 1 and a processor element group 5 - 2 are connected via an exchange unit 3 - 3 in an H-shape arrangement to constitute a processor element group 6 - 1 that executes an arithmetic operation equivalent to 3 qubits
  • processor element group 6 - 1 and a processor element group 6 - 2 are connected via an exchange unit 3 - 4 in an H-shape arrangement to constitute a processor element group 7 - 1 that executes an arithmetic operation equivalent to 4 qubits.
  • processor element group 7 - 1 and a processor element group 7 - 2 are connected via an exchange unit 3 - 5 in an H-shape arrangement to constitute a processor element group that executes an arithmetic operation equivalent to 5 qubits, namely, the parallel processor 1 .
  • the aforesaid processor element functions as an arithmetic circuit of the present invention and the exchange unit functions as a switch circuit of the present invention. Further, the processor element group functions as an arithmetic circuit group of the present invention.
  • the parallel processor 1 has a controller 8 that controls the plural processor elements and the plural exchange units in the parallel processor 1 , and an interface 9 for data exchange or the like between the parallel processor 1 and external circuits (devices) and so on connected thereto.
  • processor elements provided in the above-described parallel processor 1 shown in FIG. 1 have the same structure, and therefore, the processor element 2 - 1 will be explained below as an example.
  • FIG. 2 is a block diagram showing an example of the configuration of the above-mentioned processor element 2 - 1 shown in FIG. 1 .
  • the processor element 2 - 1 is composed of an arithmetic part 11 and a register part 12 .
  • the arithmetic part 11 executes a predetermined arithmetic operation (unitary conversion) for any one state, out of 32 states, for which the processor element 2 - 1 is to execute an arithmetic operation.
  • the arithmetic part 11 is supplied from the register part 12 with internal data IDT indicating the one state, out of the 32 states, for which an arithmetic operation is to be executed, and is supplied with input data DTI indicating another state different from the above-mentioned one state from another processor element (processor element group) via the exchange unit 3 - 1 .
  • the above-mentioned internal data IDT and input data DTI are probability amplitudes of logical values as described above, and the probability amplitude is expressed using a complex number. Further, since the arithmetic operation executed in the arithmetic part 11 is unitary conversion, unitarity is constantly maintained in the arithmetic operation executed by the arithmetic part 11 .
  • the state for which the processor element 2 - 1 is to execute an arithmetic operation is a state of a logical value “00001” among the 32 states
  • the probability amplitude of the logical value “00001” is supplied to the arithmetic part 11 as the internal data IDT
  • the probability amplitude of a logical value different from the logical value “00001” is supplied to the arithmetic part 11 as the input data DTI.
  • a coefficient signal SC is supplied to the arithmetic part 11 from the controller 8 via the exchange unit 3 - 1 .
  • the arithmetic part 11 executes a product-sum operation of the complex numbers for the plural states (the probability amplitudes represented by the complex numbers) supplied as the internal data IDT and the input data DTI, using a coefficient value supplied as the aforesaid coefficient signal SC. Then, the arithmetic part 11 outputs states obtained as a result of the arithmetic operations (probability amplitudes expressed by complex numbers) to the register part 12 .
  • the register part 12 stores the results of the arithmetic operations outputted from the arithmetic part 11 , according to an instruction supplied from the controller 8 shown in FIG. 1 via a not-shown signal line.
  • the register part 12 also outputs the stored result of the arithmetic operations to the arithmetic part 11 as the internal data IDT, and to another processor element (processor element group) as output data DTO via the exchange unit 3 - 1 , according to the instruction supplied via the not-shown signal line.
  • FIG. 3 is a block diagram showing an example of the configuration of the above-described arithmetic part 11 shown in FIG. 2 in detail.
  • the arithmetic part 11 is constituted of four multipliers 21 - 1 to 21 - 4 and two adders 22 - 1 to 22 - 2 .
  • the multipliers 21 - 1 to 21 - 4 are supplied with the coefficient signal SC as well as the internal data IDT or the input data DTI.
  • the multipliers 21 - 1 to 21 - 4 multiply a coefficient value supplied as the coefficient signal SC by a real part and an imaginary part of the probability amplitude of one logical value, out of the 32 logical values, supplied as the internal data IDT, and by a real part and an imaginary part of the probability amplitude of the logical value supplied as the input data DTI (the logical value different from the aforesaid one logical value), respectively, and output the results thereof to the adders 22 - 1 , 22 - 2 on a subsequent stage that are connected thereto.
  • the adder 22 - 1 adds the multiplication results outputted from the multipliers 21 - 1 and 21 - 2 respectively. Further, the adder 22 - 2 adds the multiplication results outputted from the multipliers 21 - 3 and 21 - 4 respectively. Then, the adders 22 - 1 , 22 - 2 output the addition results to the aforesaid register part 12 shown in FIG. 2 .
  • the arithmetic part 11 is configured as described above, so that the arithmetic part 11 executes the product-sum operation of the plural states (probability amplitudes), which are supplied as the internal data IDT and the input data DTI, and the coefficient value supplied as the coefficient signal SC.
  • FIG. 4 is a block diagram showing an example of the configuration of the exchange unit (EU) 3 - 1 shown in FIG. 1 .
  • the exchange unit 3 - 1 is constituted of six switching elements SW 1 to SW 6 .
  • the switching elements SW 1 and SW 2 are connected in series between a data output terminal of the processor element 2 - 1 and a data input terminal of the processor element 2 - 2 , and between the data output terminal of the processor element 2 - 1 and a first data input terminal of the exchange unit 3 - 2 , respectively.
  • the switching elements SW 3 and SW 4 are connected in series between a data output terminal of the processor element 2 - 2 and a data input terminal of the processor element 2 - 1 , and between the data output terminal of the processor element 2 - 2 and a second data input terminal of the exchange unit 3 - 2 , respectively.
  • the switching elements SW 5 and SW 6 are connected in series between the first and second data output terminals of the exchange unit 3 - 2 and the data input terminals of the processor element 2 - 1 and 2 - 2 , respectively.
  • one state (probability amplitude of the logical value), out of the 32 states, outputted as the output data DTO from the processor element 2 - 1 is supplied or is not supplied to the processor element 2 - 2 and the exchange unit 3 - 2 respectively.
  • one state, out of the 32 states, outputted as the output data DTO from the processor element 2 - 2 is supplied or is not supplied to the processor element 2 - 1 and the exchange unit 3 - 2 respectively.
  • the switching operation of the switching elements SW 5 and SW 6 the remaining states outputted from the exchange unit 3 - 2 , out of the 32 states except the aforesaid states for which the arithmetic operations are to be executed in the processor elements 2 - 1 , 2 - 2 , are supplied or are not supplied to the processor elements 2 - 1 and 2 - 2 respectively.
  • the exchange unit 3 - 1 is configured as described above to control a data supply route by appropriately opening/closing the switching elements SW 1 to SW 6 , so that it is possible to supply the 32 states to the plural processor elements constituting the parallel processor 1 respectively.
  • FIG. 4 shows only data signal lines for mutual data exchange between the processor elements 2 - 1 , 2 - 2 and the exchange unit 3 - 2 , but signal lines for supplying instructions and for supplying a coefficient as the coefficient signal SC from the aforesaid controller 8 shown in FIG. 1 may be provided in the exchange unit (EU).
  • EU exchange unit
  • the state for which an arithmetic operation is executed in the processor element 2 - 1 shown in FIG. 1 is the state of a logical value “XXX00” (X is Don't care)
  • the state for which an arithmetic operation is executed in the processor element 2 - 2 is the state of a logical value “XXX01” (X is Don't care).
  • the switching elements SW 1 and SW 3 in the exchange unit 3 - 1 are closed and the other switching elements SW 2 , SW 4 to SW 6 are opened.
  • part of the states (probability amplitudes) of the logical values “XXX00” stored in the register part 12 in the processor element 2 - 1 (for example, that obtained by multiplying a predetermined coefficient value) is supplied to the arithmetic part 11 in the processor element 2 - 2 via the switching element SW 1 in the exchange unit 3 - 1 .
  • part of the states (probability amplitudes) of the logical values “XXX01” stored in the register part 12 in the processor element 2 - 2 is supplied to the arithmetic part 11 in the processor element 2 - 1 via the switching element SW 3 in the exchange unit 3 - 1 .
  • a coefficient value according to the arithmetic operations is supplied as the coefficient signal SC to each of the processor elements 2 - 1 , 2 - 2 from the controller 8 .
  • the arithmetic part 11 in the processor element 2 - 1 executes a product-sum operation for the states (probability amplitudes), using the state of the logical value “XXX00” stored in the own register part 12 , part of the states of the logical values “XXX01” supplied from the processor element 2 - 2 , and the coefficient value supplied as the coefficient signal SC. Consequently, the state of the logical value “XXX00” that has undergone the arithmetic operation is obtained as the result of the arithmetic operation.
  • the arithmetic part 11 in the processor element 2 - 2 also executes a similar product-sum operation simultaneously with the product-sum operation in the arithmetic part 11 in the processor element 2 - 1 , so that the state of the logical value “XXX01; ” that has undergone the arithmetic operation is obtained as the result of the arithmetic operation. Note that since qubits as objects of the arithmetic operations in the processor elements 2 - 1 , 2 - 2 are the same, the arithmetic operations of the states executed therein are the same.
  • the same arithmetic operation as that executed in the processor elements 2 - 1 , 2 - 2 as described above is executed simultaneously in all the processor elements included in the parallel processor 1 . Consequently, the parallel processor 1 simultaneously executes arithmetic operations for the least significant qubit regarding 32 states equivalent to 5 qubits, so that the results of all the arithmetic operations can be obtained quickly.
  • the basic operation is the same except that the open/close control over the switching elements SW 1 to SW 6 in the exchange unit is different, and that a processor element that supplies part of the state of the logical value is a corresponding processor element (to execute an arithmetic operation for a logical value in which only a logical value of the object qubit of the arithmetic operation is different) of a different processor element group, and therefore, explanation thereof will be omitted.
  • the processor element groups are connected recursively via an exchange unit, so that a parallel processor that executes an arithmetic operation equivalent to a predetermined number of qubits is constituted.
  • processor element groups equivalent to N qubits which simultaneously execute arithmetic operations for states of all 2 N logical values expressable by N bits to retain the results of the arithmetic operations, are used to constitute a processor element group equivalent to (N+1) qubits, so that it is possible to simultaneously execute arithmetic operations for states of all 2 N+1 logical values expressable by (N+1) bits to constantly retain the results of the arithmetic operations.
  • the results of the arithmetic operations for all the logical values can be obtained only by one-time simultaneous arithmetic operations for all the logical values without any sequential arithmetic operations using one data value, which has been conducted in a prior art, and consequently, high speed execution of a large-scale arithmetic operation is possible.
  • the processor element groups are arranged in an H shape with the exchange unit interposed therebetween when they are recursively connected to each other, but the present invention is not limited to this arrangement.
  • the symmetrical arrangement and connection of the processor element groups with respect to the exchange unit allows very easy and rational designing.
  • the semiconductor computing device that executes an arithmetic operation equivalent to 5 qubits is shown, but the present invention is not limited to the semiconductor computing device that executes an arithmetic operation equivalent to 5 qubits, and is applicable to a semiconductor computing device that executes an arithmetic operation equivalent to an arbitrary number of qubits in a manner shown in FIG. 5 .
  • FIG. 5 is a view for explaining a method of constituting a semiconductor computing device that executes an arithmetic operation equivalent to an arbitrary number of qubits.
  • 8 - 1 and 8 - 2 denote processor element groups each configured to execute an arithmetic operation equivalent to 5 qubits and constituted of the two processor element groups 7 - 1 , 7 - 2 shown in FIG. 1 each configured to execute an arithmetic operation equivalent to 4 qubits.
  • processor element groups 8 - 1 , 8 - 2 are connected via an exchange unit 3 - 6 in, for example, an H-shape arrangement to constitute a processor element group 9 - 1 that executes an arithmetic operation equivalent to 6 qubits, and the processor element group 9 - 1 and a processor element group 9 - 2 are connected via an exchange unit 3 - 7 in an H-shape arrangement to constitute a processor element group 10 - 1 that executes an arithmetic operation equivalent to 7 qubits.
  • processor element groups are recursively connected via an exchange unit to increase the number of operable qubits.
  • processor element groups 12 - 1 , 12 - 2 are connected to each other via an exchange unit 3 -N, each of the processor element groups 12 - 1 , 12 - 2 having processor element groups 11 - 1 , 11 - 2 each of which executes an arithmetic operation equivalent to (N ⁇ 2) qubits, and an exchange unit 3 ⁇ (N ⁇ 1), and being configured to execute an arithmetic operation equivalent to (N ⁇ 1) qubits, so that a processor element group 13 - 1 that executes an arithmetic operation equivalent to N qubits is constituted.
  • a semiconductor computing device that simultaneously executes arithmetic operations for states of all logical values expressable by (N+1) bits and retains the results of the respective arithmetic operations is constituted of two N-qubit arithmetic circuit groups, each of which simultaneously executes arithmetic operations for states of all logical values expressable by N bits and retains the results of the arithmetic operations, and an N th -qubit switch circuit for the exchange of the states of the logical values between the two N-qubit arithmetic circuit groups.
  • a semiconductor computing device configured to execute a large-scale arithmetic operation can be designed only by connecting arithmetic circuit groups recursively via a switch circuit, so that it is possible to easily design a semiconductor computing device configured to execute a large-scale arithmetic operation without any increase in time and effort required for designing.
  • the semiconductor computing device includes two N-qubit arithmetic circuit groups each configured to simultaneously execute arithmetic operations for the states of all the logical values expressable by N bits and retain the results of the arithmetic operation, so that it is possible to simultaneously execute arithmetic operations for the states of all the logical values expressable by (N+1) bits and constantly retain the results of the respective arithmetic operations, which makes it possible to obtain the results of the arithmetic operations for all the logical values only by one-time simultaneous arithmetic operations for all the logical values. Therefore, it is possible to execute a large-scale arithmetic operation at high speed.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Computer Hardware Design (AREA)
  • Nanotechnology (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Software Systems (AREA)
  • Evolutionary Computation (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Computational Mathematics (AREA)
  • Artificial Intelligence (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Complex Calculations (AREA)
US10/488,925 2001-09-14 2002-09-10 Semiconductor calculation device Expired - Fee Related US6963079B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001279286A JP3542342B2 (ja) 2001-09-14 2001-09-14 半導体演算装置
JP2001-279286 2001-09-14
PCT/JP2002/009187 WO2003025738A1 (fr) 2001-09-14 2002-09-10 Dispositif de calcul a semiconducteur

Publications (2)

Publication Number Publication Date
US20040266084A1 US20040266084A1 (en) 2004-12-30
US6963079B2 true US6963079B2 (en) 2005-11-08

Family

ID=19103512

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/488,925 Expired - Fee Related US6963079B2 (en) 2001-09-14 2002-09-10 Semiconductor calculation device

Country Status (8)

Country Link
US (1) US6963079B2 (zh)
EP (1) EP1426856A1 (zh)
JP (1) JP3542342B2 (zh)
CN (1) CN1568456A (zh)
AU (1) AU2002330511B2 (zh)
CA (1) CA2460483A1 (zh)
TW (1) TWI271774B (zh)
WO (1) WO2003025738A1 (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101118608B (zh) * 2007-08-23 2011-07-20 清华大学 任意量子比特门的分解方法
US7865650B2 (en) * 2008-04-01 2011-01-04 International Business Machines Corporation Processor with coherent bus controller at perpendicularly intersecting axial bus layout for communication among SMP compute elements and off-chip I/O elements
US7917730B2 (en) * 2008-04-01 2011-03-29 International Business Machines Corporation Processor chip with multiple computing elements and external i/o interfaces connected to perpendicular interconnection trunks communicating coherency signals via intersection bus controller
US9721209B2 (en) * 2013-10-14 2017-08-01 Microsoft Technology Licensing, Llc Method and system for efficient decomposition of single-qubit quantum gates into Fibonacci anyon braid circuits
US20190164959A1 (en) * 2016-09-29 2019-05-30 Intel Corporation On-chip control logic for qubits
US10275391B2 (en) * 2017-01-23 2019-04-30 International Business Machines Corporation Combining of several execution units to compute a single wide scalar result
US10333503B1 (en) 2018-11-26 2019-06-25 Quantum Machines Quantum controller with modular and dynamic pulse generation and routing
US10454459B1 (en) 2019-01-14 2019-10-22 Quantum Machines Quantum controller with multiple pulse modes
US10505524B1 (en) 2019-03-06 2019-12-10 Quantum Machines Synchronization in a quantum controller with modular and dynamic pulse generation and routing
CN110020727B (zh) * 2019-04-09 2021-06-08 合肥本源量子计算科技有限责任公司 一种基于mpi多进程的单量子逻辑门实现方法
US11164100B2 (en) 2019-05-02 2021-11-02 Quantum Machines Modular and dynamic digital control in a quantum controller
US10931267B1 (en) 2019-07-31 2021-02-23 Quantum Machines Frequency generation in a quantum controller
US11245390B2 (en) 2019-09-02 2022-02-08 Quantum Machines Software-defined pulse orchestration platform
US10862465B1 (en) 2019-09-02 2020-12-08 Quantum Machines Quantum controller architecture
US11043939B1 (en) 2020-08-05 2021-06-22 Quantum Machines Frequency management for quantum control
US11671180B2 (en) 2021-04-28 2023-06-06 Quantum Machines System and method for communication between quantum controller modules
US20220374378A1 (en) * 2021-05-10 2022-11-24 Quantum Machines System and method for processing between a plurality of quantum controllers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000068495A (ja) 1998-08-19 2000-03-03 Inst Of Physical & Chemical Res 量子コンピュータにおける量子ビット素子構造および量子相関ゲート素子構造
JP2001021932A (ja) 1999-07-02 2001-01-26 Fujitsu Ltd 量子コンピュータ

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000068495A (ja) 1998-08-19 2000-03-03 Inst Of Physical & Chemical Res 量子コンピュータにおける量子ビット素子構造および量子相関ゲート素子構造
JP2001021932A (ja) 1999-07-02 2001-01-26 Fujitsu Ltd 量子コンピュータ

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
F.A. Williams; "An expandable single-IC digital filter/Correlator"; Acoustics, Speech, and Signal Process IEEE International Conference on ICASSP '82; vol. 7; May 1982; pp. 1077-1080 with cover page.
J. R. Pasky, et al.; "Regular arrays of quantum-dot cellular automata "macrocells""; Journal of Applied Physics; vol. 87; No. 12; Jun. 15, 2000; pp. 8604-8609.

Also Published As

Publication number Publication date
US20040266084A1 (en) 2004-12-30
WO2003025738A1 (fr) 2003-03-27
CA2460483A1 (en) 2003-03-27
JP2003084966A (ja) 2003-03-20
EP1426856A1 (en) 2004-06-09
CN1568456A (zh) 2005-01-19
AU2002330511B2 (en) 2006-12-07
JP3542342B2 (ja) 2004-07-14
TWI271774B (en) 2007-01-21

Similar Documents

Publication Publication Date Title
US6963079B2 (en) Semiconductor calculation device
Thompson Fourier transforms in VLSI
Uzam The use of the Petri net reduction approach for an optimal deadlock prevention policy for flexible manufacturing systems
US5831883A (en) Low energy consumption, high performance fast fourier transform
CN103793199B (zh) 一种支持双域的快速rsa密码协处理器
EP0557997A2 (en) Information processing apparatus and information processing system
Liu et al. Design of quantum-dot cellular automata circuits using cut-set retiming
CA2438313A1 (en) Optimization method for quantum computing process
US20230316121A1 (en) Efficient quantum modular multiplier and quantum modular multiplication method
Ryan et al. An isma lee router accelerator
JP2022101472A (ja) 低レイテンシのモジュラ乗算のためのシステム及び方法
Sultana et al. Reversible implementation of square-root circuit
Bhoi et al. A redundant adder architecture in ternary quantum-dot cellular automata
Cavallaro et al. VLSI implementation of a CORDIC SVD processor
US7565387B1 (en) Systems and methods for configuring a programmable logic device to perform a computation using carry chains
TWI826040B (zh) 量子電路設計方法及裝置
Huang et al. A parallel FFT algorithm for transputer networks
Fujishima et al. Fractally-structured CMOS processor for quantum-circuit emulation
Chi Is there a universal quantum computer?
Skorupski et al. The Algorithm for Reversible Circuits Synthesis
Jamal et al. Towards Designing Optimized Low Power Reversible Demultiplexer for Emerging Nanocircuits
Na et al. A study on the highly parallel multiple-valued logic circuit design method based on the DTG
US5958001A (en) Output-processing circuit for a neural network and method of using same
JP3708072B2 (ja) 半導体演算装置
Renuka Implementation of N-Bit ALU using quantum dot cellular automata based reversible logic method

Legal Events

Date Code Title Description
AS Assignment

Owner name: JAPAN SCIENCE AND TECHNOLOGY AGENCY, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FUJISHIMA, MINORU;O'UCHI, SHIN-ICHI;HOH, KOICHIRO;REEL/FRAME:015775/0199;SIGNING DATES FROM 20040224 TO 20040301

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20091108