US6788787B1 - Pseudorandom number generator, stream encryption method, and stream encrypting communication method - Google Patents

Pseudorandom number generator, stream encryption method, and stream encrypting communication method Download PDF

Info

Publication number
US6788787B1
US6788787B1 US09/512,284 US51228400A US6788787B1 US 6788787 B1 US6788787 B1 US 6788787B1 US 51228400 A US51228400 A US 51228400A US 6788787 B1 US6788787 B1 US 6788787B1
Authority
US
United States
Prior art keywords
stream
dimensional mapping
converter
output
pseudorandom number
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US09/512,284
Other languages
English (en)
Inventor
Katsufusa Shono
Osamu Ueno
Tetsuya Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yazaki Corp
Original Assignee
Yazaki Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yazaki Corp filed Critical Yazaki Corp
Assigned to MICRO- TECHNOLOGY CORPORATION, YAZAKI CORPORATION reassignment MICRO- TECHNOLOGY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ISHIHARA, TETSUYA, UENO, OSAMU, SHONO, KATSUFUSA
Assigned to YAZAKI CORPORATION reassignment YAZAKI CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRO-TECHNOLOGY CORPORATION
Application granted granted Critical
Publication of US6788787B1 publication Critical patent/US6788787B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04K—SECRET COMMUNICATION; JAMMING OF COMMUNICATION
    • H04K1/00—Secret communication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator
    • H04L9/0668—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator producing a non-linear pseudorandom sequence
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/12—Transmitting and receiving encryption devices synchronised or initially set up in a particular manner
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry

Definitions

  • the present invention relates to a pseudorandom number generator that generates a chaotic stream of pseudorandom numbers, to a method for stream encrypting, and to a stream encrypting communication method.
  • pseudorandom number generators will be key devices. Because noise generated by actual physical mechanisms lacks repeatability, it is not usable as a practical technology in industry. In its place, there is a need for pseudorandom number generators capable of generating diverse and repeatable binary streams that can be treated as pseudorandom numbers.
  • pseudorandom noise is used interchangeably with the term pseudorandom number. Because true pseudorandom numbers, for example, as would be generated by tossing a coin, are not repeatable, they are not applicable to industrial technologies. On the other hand, unless a series of numbers can defy prediction, it cannot not be expected to offer sufficient scrambling or dispersion. Thus, the needs of industry require that these conflicting goals be met in developing an ideal pseudorandom number generator.
  • a chaotic stream is known to include all frequency components, and is extremely close to representing random numbers. For this reason, it is known that, if it is possible to make a chaotic stream periodic, it could be used as pseudorandom numbers.
  • Another object of the present invention is to provide a method for stream encrypting, which uses a binary stream obtained from a pseudorandom number generator to generate, for use, for example, in communication, encrypted text that achieves an optimal high level of security.
  • a first aspect of the present invention includes a one dimensional mapping circuit for generating chaos having non-linear input-output characteristics, an AD converter for converting an analog output of the one dimensional mapping circuit, a sample-and-hold circuit for holding and outputting a digitally converted value from the AD converter in response to an external clock, and a DA converter for outputting an analog converted value in response to the output of the sample-and-hold circuit as feedback to the one dimensional mapping circuit, (forming a chaos-generating loop), wherein the quantizing divisions of at least one of the AD converter and the DA converter are made non-linear, and a binary sequence is output responsive to the output of the sample-and-hold circuit.
  • the one dimensional mapping circuit (with non-linear input-output characteristics) forming a chaos-generating loop via a sample-and-hold circuit and the like, a mapping function whereby chaos is generated is provided.
  • the AD converter or the DA converter hereinafter collectively referred to as the non-linear quantizer
  • the input-output characteristics of this one dimensional mapping circuit having self-feedback (the mapping at each step is suppressed)
  • a periodic time series may be obtained from the generated chaos.
  • the output of the sample-and-hold circuit is applied, for example, to a general decoder, and a binary sequence ⁇ Y(t) ⁇ t ⁇ is extracted from the decoder output, where t is the discrete time.
  • the chaos contains all frequency components, and non-linear quantizing is used to observe its internal condition, the chaos is converted to a multiple-value integer sequence, which encompasses all combinations of integer sequences.
  • a non-linear quantizer within the chaos-generating loop, it is possible to simultaneously extract the period and random numbers, and it is intrinsically guaranteed to be possible to extract all combinations thereof.
  • a second aspect of the present invention is a variation of the first aspect, wherein the pseudorandom number generator has an AD converter with linear quantizing divisions and a DA converter with non-linear quantizing divisions.
  • a third aspect of the present invention is a variation on the pseudorandom number generator of the first aspect, wherein the one dimensional mapping circuit is implemented by a CMOS inverter, and wherein the AD converter is configured so as to include an AD weighting resistive array and a comparator array that compares the relative size of an output obtained from a synthesized resistance of the AD weighting resistive array and the analog output from the one dimensional mapping circuit.
  • the sample-and-hold circuit is implemented as a flip-flop array that captures and holds the digital output of the AD converter in response to an external clock, and wherein the DA converter is configured so as to include a DA weighting resistive array. Further, a switching array outputs an output obtained from the synthesized resistance of the DA weighting resistive array in response to the digital output from the sample-and-hold circuit as feedback to the one dimensional mapping circuit.
  • a fourth aspect of the present invention is a variation on the pseudorandom number generator of the third aspect, wherein an exclusive-OR array is inserted which takes the exclusive-OR of the outputs of each comparator making up the comparator array.
  • the exclusive-OR array is provided between the AD converter and the sample-and-hold circuit.
  • a fifth aspect of the present invention has a chaos-generating loop that includes a pair of one dimensional mapping circuits for generating chaos having non-linear input-output characteristics, a pair of CMOS switches which alternately open and close an output side path of the one dimensional mapping circuits, in synchronization with an external clock, and a pair of feedback loops that cross-connect the analog outputs of each of the one dimensional mapping circuits, via the CMOS switches, as feedback to the inputs of the other of the one dimensional mapping circuits, and a pair of AD converters that perform digital conversion of the analog outputs of the one dimensional mapping circuits that are extracted via the CMOS switches.
  • the outputs of the one dimensional mapping circuits are alternately mapped, so as to output, via each of the AD converters, a binary sequence that is a chaos sequence.
  • the binary stream extracted by the alternating method noted above is a random arrangement of data comprised of mixed 0 and 1 values.
  • the binary stream obtained exhibits a fine disturbance of 1 and 0 values, acting in combination with divergence and convergence of the analog outputs created by the pair of one dimensional mapping circuits and the initial value sensitivity characteristic of chaos. It is expected that the characteristic variation properties of chaos will contribute to the improvement of the robustness of stream encrypting.
  • a long time series is to be generated, this can be done by repeating mapping in the chaos-generating loop. If it is assumed that a time series of a PN signal will be extracted as a time series of a prescribed length from a long time series generated in this manner, it is necessary that the auto-correlation and cross-correlation functions of the extracted time series be sufficiently small. That is, it is required that there be no overlaps in the correlation if the phase is shifted one bit at a time. This is to assure the robustness of the code.
  • the sixth aspect of the present invention is a variation of the pseudorandom number generator of the fifth aspect, which further has a DA converter that performs an analog conversion of an initial value given in the form of a digital signal, and a CMOS switch, which performs opening and closing of an output side path of the DA converter, synchronized to an external clock.
  • an applied voltage is given via a DA converter, which corresponds to a real number.
  • initial value sensitivity is given via a DA converter, using a pair of binary streams that differ in their staring points, regardless of how these streams are phase shifted and overlapped, there is no coincidence therebetween, and it is possible to achieve a time series with a sufficiently low auto-correlation and cross-correlation function.
  • the design be such that the input-output characteristics of the one dimensional mapping circuits that are used as elements in the pseudorandom number generator can be adjusted from outside.
  • a seventh aspect of the present invention is a variation of the pseudorandom number generator of the fifth aspect, designed so that at least one of the pair of one dimensional mapping circuits has input-output characteristics that can be individually adjusted by means of an external adjustment voltage.
  • An eighth aspect of the present invention is a method for stream encrypting, whereby a binary stream generated by a pseudorandom number generator according to the first or fifth aspect of the present invention is used to perform stream encrypting, thereby obtaining an encrypted text code, whereby the above-noted stream encrypting is achieved by an exclusive-OR operation performed between a binary stream obtained from the pseudorandom number generator and the plain text to be encrypted.
  • the encrypted text is generated by performing stream encrypting using a binary stream obtained from a pseudorandom number generator. Further, according to the present invention, because the stream encrypting is done by an exclusive-OR operation between the binary stream and the plain text to be encrypted, it is possible to achieve a stream encrypting method capable of producing encrypted text with an extremely high degree of security for applications such as communications.
  • a ninth aspect of the present invention is a stream encrypting communications method that uses an encrypted text obtained by the stream encrypting method of the eighth aspect of the present invention.
  • FIG. 1 is a simplified block diagram showing a pseudorandom number generator according to the present invention
  • FIG. 2 is a circuit diagram showing an implementation of a pseudorandom number generator of the present invention
  • FIG. 3 is a distribution of an auto-correlation function
  • FIG. 4 is a simplified block diagram showing a pseudorandom number generator according to a second embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing an integrated circuit implementation of the pseudorandom number generator 41 of FIG. 4;
  • FIG. 6 is a functional block diagram showing a stream encrypted communication system.
  • FIG. 1 is a simplified block diagram of a pseudorandom number generator according to a first embodiment of the present invention.
  • the pseudorandom number generator 11 of the first embodiment which corresponds to the first aspect of the present invention has a one dimensional mapping circuit 13 for generating chaos having non-linear input-output characteristics, an AD converter 15 for digitally converting an analog output of the one dimensional mapping circuit 13 , a sample-and-hold circuit 17 for holding and outputting the digitally converted value of the AD converter 15 in response to an external clock C, and a DA converter 19 for outputting to the one dimensional mapping circuit 13 an analog converted value in response to the output of the sample-and-hold circuit 17 .
  • the sequence of a closed integer series when the weighting of AD and DA converters and the connectivity therebetween are both fixed is given as one type of time series. Changing the time series sequence is achieved by changing the connectivity between the AD and DA convertors.
  • FIG. 2 shows the circuit of the pseudorandom number generator 11 of the first embodiment of the present invention, as recited in claim 1 through claim 4 of the accompanying claims.
  • a first pseudorandom number generator 11 includes a one dimensional mapping circuit 13 comprising three stages of CMOS inverters, an AD weighting resistive array 25 , a comparator array 27 , an exclusive-OR array (hereinafter referred to as an EXOR array) 29 , a switch array 31 that gives an initial value, a D-type flip-flop array 17 that serves as a sample-and-hold circuit, a DA switch array 33 , a DA weighting resistive array 35 , and a decoder 37 .
  • the one dimensional mapping circuit 13 is described in detail in the Japanese Laid-open Patent Application publication 9-260952 of one of the inventors which has already been made public, it will only be described simply herein.
  • the first stage is a source follower which establishes an increasing function with respect to the input.
  • the second and third stages are inverters, which establish decreasing functions with respect to their inputs.
  • the third stage inverter input 23 is provided for adjusting the non-linearity of the non-linear mapping function.
  • the numbers affixed to the PMOS and NMOS transistors are the weights applied to the channel conductances.
  • the state decisions of the output with respect to the input must be performed at a high speed (up to a Megahertz) and also with high precision (up to the quantizing resolution).
  • the AD weighting resistive array 25 is an array of resistors of uniform resistances of, for example, 1.2 k ⁇ . That is, this embodiment shows that the AD converter is designed so as to have linear quantizing divisions.
  • the resistors on the ends (having resistance values of 4.5 k ⁇ and 28.7 k ⁇ ) are bias resistances provided for the purpose of making the dynamic range of the output of the input-output characteristics of the one dimensional mapping circuit 13 coincide with the operating region of the AD converter 15 .
  • the comparator array 27 performs a comparison between the quantizing reference voltage established by the synthesized resistance of the AD weighting resistive array 25 and the voltage output to the chaos-generating loop 14 by the one dimensional mapping circuit 13 , and outputs a Gray code. That is, the AD weighting resistive array 25 and the comparator array 27 operate collectively as an AD converter 15 .
  • the EXOR array 29 in the example shown in the drawing takes the exclusive-OR of the output bits from neighboring comparators of the comparator array 27 , outputting a 1 level for bits which do not coincide in the Gray code, and a 0 level for coinciding bits.
  • the switch S 5 which establishes the initial value y(0), is the only switch connected to the power supply voltage, with the all other switches being grounded. Additionally, there is a reset/startup button.
  • the D-type flip-flop array 17 which serves as a sample-and-hold circuit, captures the outputs of the EXOR array 29 , in synchronization with the timing of an external clock, which are held and output to the DA switch array 33 and decoder 37 . By doing this, the D-type flip-flop array 17 controls the signal output timing of the pseudorandom number generator 11 .
  • the DA switch array 33 operates so that only the switches for which the output of the flip-flop array 17 (this being the output of the EXOR array 29 ) is at the 1 level are closed.
  • the DA weighting resistive array 35 has resistance values that establish non-linear weighting. In the DA switch array 33 , therefore, if a switch for which the output of the flip-flop array 17 (this being the output of the EXOR array 29 ) is at the 1 level, is closed, a non-linear voltage is generated in the DA weighting resistive array 35 , and an input is applied to the one dimensional mapping circuit 13 via the feedback path 21 of the chaos-generating loop. Thus, the DA switch array 33 and the DA weighting resistive array 35 operate collectively as a DA converter 19 .
  • the dynamic ranges of the AD converter 15 and the DA converter 19 are adjusted so as to coincide, respectively, with the x-axis (input) and y-axis (output) of the input-output characteristics of the one dimensional mapping circuit 13 .
  • the decoder 37 is formed by a diode matrix arranged so as to represent a truth table, whereby 4-bit digital codes are output that are responsive to outputs of the flip-flop array (that is, EXOR array 29 ) that are at the 1 level.
  • the timing circuit for obtaining a binary stream ⁇ Y(t) (D ⁇ overscore (o) ⁇ , D 1 , D 2 , D 3 ) ⁇ t ⁇ is omitted from the drawing.
  • This embodiment of the present invention is a specific example, in which the quantizing resolution is 4 bits, and the binary stream Y(t) has a period of 64 bits.
  • FIG. 3 shows the result of performing the calculation after replacing bit 1 with +1 and bit 0 with ⁇ 1 in the binary stream ⁇ Y(t) (D 0 , D 1 , D 2 , D 3 ) ⁇ t ⁇ , from which it can be seen that complete synchronization is achieved at delay times ⁇ of 0 and 64. While there are peaks of approximately 1 ⁇ 4 at side lobes and it appears at first glance that the correlation is poor, this function is one which theoretically facilitates the establishment of synchronization.
  • the first embodiment is one in which the CMOS source follower is implemented by an enhancement mode MOS transistor, in executing a one-chip IC implementation, the use of a depletion mode MOS transistor as the CMOS source follower enables an increase of the clock frequency to the megahertz order.
  • FIG. 4 is a simplified block diagram of a pseudorandom number generator according to the second embodiment of the present invention.
  • the pseudorandom number generator 41 shown in FIG. 4 has a chaos-generating loop 63 that includes a pair of one-input/one-output one dimensional mapping circuits 43 and 51 for generating chaos having non-linear input-output characteristics, a pair of CMOS switches 45 and 53 for opening and closing the output-side paths in the pair of one dimensional mapping circuits 43 and 51 , in synchronization with an external clock, a pair of feedback loops 47 and 55 that cross-connect the analog outputs of each of the pair of one dimensional mapping circuits 43 and 51 , via the CMOS switches 45 and 53 , to the input sides of the one dimensional mapping circuits 43 and 51 , a pair of AD converters 49 and 57 for performing digital conversion of the analog outputs of the pair of one dimensional mapping circuits 43 and 51 that are extracted via the CMOS switches 45 and 53 , a DA converter 65 that converts to analog form the initial value x( 0 ) given in digital signal form, and a CMOS switch 67 that opens and
  • each of the pair of one dimensional mapping circuits 49 and 57 performs alternate mapping, thereby outputting, via each of the AD converters 49 and 57 , a binary series that is a chaos stream.
  • FIG. 5 An integrated circuit implementation of the second pseudorandom number generator 41 shown in FIG. 4 is shown in FIG. 5 .
  • FIG. 4 and FIG. 5 are depicted so that the correspondence therebetween can be seen, with corresponding elements assigned the same reference numerals in both drawings. Referring to FIG. 5, the internal configuration of each of the blocks of the second pseudorandom number generator 41 is described below.
  • Each of the pair of one dimensional mapping circuits 43 and 51 which has substantially N-shaped input-output characteristics, comprises 6 MOS transistors.
  • the width and length dimensions of the channel of each transistor are indicated numerically as weights.
  • the first stage CMOS inverter establishes an increasing function, while the second-stage CMOS inverter establishes a decreasing function.
  • the result is the substantially N-shape input-output characteristics shown in FIG. 6, for example.
  • the third-stage CMOS inverter receives the external adjustment voltages applied to the input terminals 71 and 73 , and modifies the input-output characteristics of the one dimensional mapping circuits 43 and 51 .
  • the values of the external adjustment voltages applied to the input terminals 71 and 73 can be either one and the same value of voltage or different voltage values. Additionally, it is possible to omit one of the external adjustment voltages applied to the input terminals 71 and 73 .
  • the external adjustment voltages applied to the input terminals 71 and 73 can be derived as analog voltages that are obtained by conversion of a digital code that is set by a computer beforehand by a DA converter to analog form, in which case the values of the external adjustment voltages change in stepwise fashion, according to the quantizing resolution of the DA converter.
  • the CMOS switches 45 , 53 , and 67 are formed by the combination of a transfer gate, made by connecting a PMOS transistor and an NMOS transistor in parallel, with a CMOS inverter.
  • the CMOS switches are opened and closed in response to control signals applied to input terminals 75 , 77 , and 79 .
  • there are 2 12 4096 different initial values x( 0 ) that can be given.
  • the external clocks (discrete time t) applied to the input terminals 77 and 79 are non-overlapping squarewaves.
  • the maximum clock frequency under this condition governs the processing speed of this pseudorandom number generator.
  • This processing speed is established by the internal state decision speed of the one dimensional mapping circuit. Upon building a breadboard circuit on a printed circuit board using discrete components, it was possible to raise the clock frequency as high as 20 kHz.
  • the mapping circuit used in this embodiment is intended to be implemented as a one-chip integrated circuit, using standard CMOS IC technology, and when a prototype assuming a minimum feature size of 0.8 ⁇ m was made, it was verified by testing that operation is possible using a 1-MHz clock frequency.
  • the binary code time series data extracted in this manner is data made up of randomly interspersed values of 0 and 1 and, when the input-output characteristics of the one dimensional mapping circuits 43 and 51 exhibit good symmetry, the frequency of occurrence of 0 and 1 is substantially the same. Under these conditions, the frequency of occurrence of an isolated 0 or 1 is twice the frequency of occurrence of a duplicated series of 00 or 11.
  • the initial value sensitivity is established by the DA converter 65 . That is, between a pair of binary coded time series outputs 59 and 61 that have mutually different starting points, regardless of how the phase of these outputs is changed and the outputs overlapped, there is no coincidence therebetween, and the time series obtained have sufficiently low auto-correlation and cross-correlation functions.
  • the symmetry of the individual input-output characteristics of the one dimensional mapping circuits 43 and 51 directly influences the output distribution of 0 and 1 values in the binary time series extracted from the output terminals 59 and 61 .
  • the output distribution ratio of 0 and 1 will be equal. If the second pseudorandom number generator 41 is to be operated in this manner, it is not only necessary to make the one dimensional mapping circuits 43 and 51 have the same input-output characteristics, but also to design the one dimensional mapping circuits 43 and 51 with the maintenance of good symmetry in mind.
  • the second pseudorandom number generator 41 can be implemented as a one-chip integrated circuit pseudorandom number generator of sufficiently small size, without including the DA converter and clock generator on the IC chip, as shown in FIG. 5 .
  • the analog circuit chaos-generating loop 63 which includes the pair of one dimensional mapping circuits 43 and 51 , which are the central parts of the pseudorandom number generator 41 , because the DA converter and clock generator are digital circuits, it is also easy to include all of these in a one-chip integrated circuit.
  • CMOS integrated circuit While the design of a CMOS integrated circuit is generally implemented with enhancement mode elements, it is desirable that the first stage CMOS source follower of the one dimensional mapping circuits 43 and 51 included in the second pseudorandom number generator 41 be designed using depletion mode elements. By doing this, it is possible to design the weighting of the MOS transistors to be smaller, thereby enabling a balance mask design for the one dimensional mapping circuits.
  • Parameters such as the symmetry of the input-output characteristics of the one dimensional mapping circuits 43 and 51 and a parameter that establishes whether or not the input-output characteristics of the one dimensional mapping circuits 43 and 51 are to coincide, along with the initial value sensitivity that is characteristics of chaos, impart fine disturbances to the occurrence balance in the binary time series of 0 and 1 values that is obtained. These characteristic variations of chaos attributed to such parameters contribute to the robustness of the chaos code stream.
  • FIG. 6 is a functional block diagram showing such a stream encrypted communication system.
  • the reference symbol a denotes the input-output pseudo characteristics of the one dimensional mapping circuit 43 included in the second pseudorandom number generator 41
  • the reference symbol b denotes the input-output characteristics of the one dimensional mapping circuit 51 included in the same generator 41 .
  • the reference symbol c denotes the input-output characteristics of the one dimensional mapping circuit 43 included in the second pseudorandom number generator 41
  • the reference symbol d denotes the input-output characteristics of the one dimensional mapping circuit 51 included in the same generator 41 .
  • stream code refers to a coding system for scrambling, using a time series that is artificially produced and treating a digital file as a time series, this term being used in contraposition to the term block code.
  • the artificially generated time series will be referred to as the PN (pseudorandom number) signal.
  • stream encrypted communication system refers to a coded communication system in which, on the transmitting side a stream encrypting system is used to encrypt a plain text, which is then transmitted to a receiving destination, and decoded on the receiving side to obtain the original plain text.
  • a stream encrypted communication system 81 includes a transmitting-side apparatus 83 , a receiving-side apparatus, and a communication line 87 , such as a common carrier telephone network connected so as to enable mutual exchange of data between the transmitting-side and receiving-side apparatuses 83 and 85 .
  • Each of the apparatuses 83 and 85 includes an internal second pseudorandom number generator 41 or is connected thereto, pseudorandom numbers (a PN signal) generated by the pseudorandom number generators 41 being sent to each of the apparatuses 83 and 85 .
  • pseudorandom numbers a PN signal
  • the stream encrypted communication system 81 operates as follows. First, on the transmitting side, a plain text is encrypted into an encrypted text using a stream encrypting system. This encrypting is achieved by taking the exclusive-OR of the binary stream (PN signal) obtained by the pseudorandom number generator 41 and plain text code that includes the plain text code to be encrypted. The encrypted text obtained in this manner is transmitted to the receiving destination. According to this stream encryption method, it is possible to obtain an encrypted text with an optimum and high degree of security for use, for example, in communications.
  • the encrypted text is decrypted to obtain the original plain text.
  • the decryption is performed by taking the exclusive-OR of the binary stream (PN signal) obtained by the second pseudorandom number generator 41 and the encrypted text.
  • a required condition for enabling the above-described encrypted text to be decrypted with synchronization between the two apparatuses is that the binary stream (PN signal) for encryption be the same as the binary stream (PN signal) used for decryption.
  • PN signal binary stream
  • the second pseudorandom number generator 41 was described using an exemplary application to a stream encrypted communication system, the present invention is not restricted in this manner, and can be embodied as well by applying the first pseudorandom number generator 11 to a stream encrypted communication system.
  • a non-linear quantizer is inserted in a chaos-generating loop for analog mapping by a one dimensional mapping circuit, thereby enabling the provision of a pseudorandom number generator that is capable of repeated extraction of the same binary stream ⁇ Y(t) ⁇ t ⁇ .
  • the present invention as recited in the third aspect, it is possible to implement the pseudorandom number generator of the present invention with a CMOS integrated circuit, and to provide a novel technology for replacing the known feedback shift register circuit.
  • the pseudorandom number generator of the present invention it is possible for the pseudorandom number generator of the present invention to output not only a binary stream ⁇ Y(t) ⁇ t ⁇ , but also an integer series signal ⁇ y(t) ⁇ t ⁇ having a period of 2 n , where n is the resolution, and because all combinations of integer series are guaranteed, it is possible to contribute to the improvement in calculating power of a digital computer. Additionally, because solution to a travelling salesman problem (TSP) is assured, it is possible to provide a basic technology applicable not only to communications, but also to advancements in computers.
  • TSP travelling salesman problem
  • initial value sensitivity is given via a DA converter, between a pair of binary streams having the same initial value as a starting point, regardless of how the streams are phase shifted and overlapped, there is no coincidence therebetween, and it is possible to achieve a time series with a sufficiently low auto-correlation and cross-correlation function.
  • the present invention as recited in the ninth aspect, it is possible to achieve stream encrypted communication with an extremely high degree of security. More specifically, it is possible to implement an asynchronous multiple user stream encrypted communication system in which a user possessing the same pseudorandom number generator as was used in encrypting can achieve synchronous playback, expansion, mixing, and transfer of the encrypted text.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Analogue/Digital Conversion (AREA)
US09/512,284 1999-02-25 2000-02-24 Pseudorandom number generator, stream encryption method, and stream encrypting communication method Expired - Fee Related US6788787B1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP11-048957 1999-02-25
JP4895799 1999-02-25
JP2000040899A JP2000310942A (ja) 1999-02-25 2000-02-18 疑似乱数発生器、ストリーム暗号化方法、及びストリーム暗号通信方法
JP2000-040899 2000-02-18

Publications (1)

Publication Number Publication Date
US6788787B1 true US6788787B1 (en) 2004-09-07

Family

ID=26389303

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/512,284 Expired - Fee Related US6788787B1 (en) 1999-02-25 2000-02-24 Pseudorandom number generator, stream encryption method, and stream encrypting communication method

Country Status (3)

Country Link
US (1) US6788787B1 (ja)
JP (1) JP2000310942A (ja)
KR (1) KR100396243B1 (ja)

Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030059046A1 (en) * 2001-07-20 2003-03-27 Stmicroelectronics S.R.I. Hybrid architecture for realizing a random numbers generator
EP1313259A2 (en) * 2001-11-16 2003-05-21 Yazaki Corporation Cryptographic key, encryption/decryption device, cryptographic key management device using a chaotic function
US20030219119A1 (en) * 2001-12-13 2003-11-27 Stmicroelectronics S.R.L. Method for generating a random number sequence and a relative random bit generator
US20050002531A1 (en) * 2003-04-23 2005-01-06 Michaelsen David L. Randomization-based encryption apparatus and method
US20050184888A1 (en) * 2004-02-25 2005-08-25 Peter Lablans Generation and detection of non-binary digital sequences
US20050194993A1 (en) * 2004-02-25 2005-09-08 Peter Lablans Single and composite binary and multi-valued logic functions from gates and inverters
US20060021003A1 (en) * 2004-06-23 2006-01-26 Janus Software, Inc Biometric authentication system
US20060031278A1 (en) * 2004-08-07 2006-02-09 Peter Lablans Multi-value digital calculating circuits, including multipliers
US20060045309A1 (en) * 2004-06-14 2006-03-02 Shan Suthaharan Systems and methods for digital content security
US20080304664A1 (en) * 2007-06-07 2008-12-11 Shanmugathasan Suthaharan System and a method for securing information
US20090128190A1 (en) * 2004-02-25 2009-05-21 Peter Lablans Implementing Logic Functions with Non-Magnitude Based Physical Phenomena
US7548092B2 (en) 2004-02-25 2009-06-16 Ternarylogic Llc Implementing logic functions with non-magnitude based physical phenomena
US20100164548A1 (en) * 2004-09-08 2010-07-01 Ternarylogic Llc Implementing Logic Functions With Non-Magnitude Based Physical Phenomena
US20110249814A1 (en) * 2010-04-08 2011-10-13 Nagravision S.A. Device and a method for performing a cryptographic function
US20120250783A1 (en) * 2010-07-26 2012-10-04 John David Terry Method and Apparatus for Communicating Data in a Digital Chaos Communication System
US8374289B2 (en) 2004-02-25 2013-02-12 Ternarylogic Llc Generation and detection of non-binary digital sequences
US8873604B2 (en) * 2012-03-26 2014-10-28 John David Terry Method and apparatus for multiple signal aggregation and reception in digital chaos network
US20150002064A1 (en) * 2013-06-28 2015-01-01 Samsung Electro-Mechanics Co., Ltd. Circuit for detecting rotor position, apparatus and method for motor driving control using the same
WO2016099724A1 (en) * 2014-12-18 2016-06-23 Cryptography Research, Inc. A self-timed random number generator
US9479217B1 (en) 2015-07-28 2016-10-25 John David Terry Method and apparatus for communicating data in a digital chaos cooperative network
CN111538476A (zh) * 2020-04-20 2020-08-14 佳缘科技股份有限公司 一种提高输出序列随机性的细粒度校正方法
CN112328203A (zh) * 2020-10-16 2021-02-05 郑州信大捷安信息技术股份有限公司 一种随机数发生器及发生方法

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100362781C (zh) * 2002-12-06 2008-01-16 中国电子科技集团公司第三十研究所 利用模数器件的专用设备产生消息密钥的方法
KR100594292B1 (ko) 2004-09-09 2006-06-30 삼성전자주식회사 저 전력 무작위 비트 생성기 및 난수생성기
KR100633709B1 (ko) * 2004-10-22 2006-10-16 이익수 디지털 카오스 셀을 이용한 이진 코드분할다중접속 카오스음성비화시스템
KR100745828B1 (ko) * 2005-10-18 2007-08-03 노 길 용 의사난수코드 방식에 따른 위치인식용 측정자를 이용한위치인식 시스템
KR100739121B1 (ko) 2006-04-19 2007-07-13 삼성전자주식회사 신호 발생기 및 그 신호 발생방법 및 이를 채용한 ｒｆ통신 시스템
JP5014678B2 (ja) * 2006-06-13 2012-08-29 新日本無線株式会社 乱数発生回路
KR100738394B1 (ko) 2006-08-14 2007-07-12 삼성전기주식회사 카오스 신호 발생장치 및 그 발생방법
JP2017118560A (ja) * 2017-02-06 2017-06-29 株式会社 エヌティーアイ データ処理装置、データ処理システム、及びデータ処理方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3999129A (en) * 1975-04-16 1976-12-21 Rolm Corporation Method and apparatus for error reduction in digital information transmission systems
US4398062A (en) * 1976-11-11 1983-08-09 Harris Corporation Apparatus for privacy transmission in system having bandwidth constraint
US4853884A (en) * 1987-09-11 1989-08-01 Motorola, Inc. Random number generator with digital feedback
US4905176A (en) * 1988-10-28 1990-02-27 International Business Machines Corporation Random number generator circuit
US5059982A (en) * 1989-04-20 1991-10-22 Harris Corporation Back-sampling analog to digital converter
US5295188A (en) * 1991-04-04 1994-03-15 Wilson William J Public key encryption and decryption circuitry and method
US5923760A (en) * 1996-07-05 1999-07-13 Applied Nonlinear Sciences, Llc Chaotic communication apparatus and method for use with a wired or wireless transmission link
US6195669B1 (en) * 1997-09-12 2001-02-27 Kabushiki Kaisha Toshiba Physical random number generator, method of generating physical random numbers and physical random number storing medium

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3999129A (en) * 1975-04-16 1976-12-21 Rolm Corporation Method and apparatus for error reduction in digital information transmission systems
US4398062A (en) * 1976-11-11 1983-08-09 Harris Corporation Apparatus for privacy transmission in system having bandwidth constraint
US4853884A (en) * 1987-09-11 1989-08-01 Motorola, Inc. Random number generator with digital feedback
US4905176A (en) * 1988-10-28 1990-02-27 International Business Machines Corporation Random number generator circuit
US5059982A (en) * 1989-04-20 1991-10-22 Harris Corporation Back-sampling analog to digital converter
US5295188A (en) * 1991-04-04 1994-03-15 Wilson William J Public key encryption and decryption circuitry and method
US5923760A (en) * 1996-07-05 1999-07-13 Applied Nonlinear Sciences, Llc Chaotic communication apparatus and method for use with a wired or wireless transmission link
US6195669B1 (en) * 1997-09-12 2001-02-27 Kabushiki Kaisha Toshiba Physical random number generator, method of generating physical random numbers and physical random number storing medium

Cited By (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030059046A1 (en) * 2001-07-20 2003-03-27 Stmicroelectronics S.R.I. Hybrid architecture for realizing a random numbers generator
US7139397B2 (en) * 2001-07-20 2006-11-21 Stmicroelectronics S.R.L. Hybrid architecture for realizing a random numbers generator
US7269258B2 (en) * 2001-11-16 2007-09-11 Yazaki Corporation Cryptographic key, encryption device, encryption/decryption device, cryptographic key management device, and decryption device
US20030095659A1 (en) * 2001-11-16 2003-05-22 Yazaki Corporation Cryptographic key, encryption device, encryption/decryption device, cryptographic key management device, and decryption device
EP1313259A2 (en) * 2001-11-16 2003-05-21 Yazaki Corporation Cryptographic key, encryption/decryption device, cryptographic key management device using a chaotic function
EP1313259A3 (en) * 2001-11-16 2010-10-06 Yazaki Corporation Cryptographic key, encryption/decryption device, cryptographic key management device using a chaotic function
US20030219119A1 (en) * 2001-12-13 2003-11-27 Stmicroelectronics S.R.L. Method for generating a random number sequence and a relative random bit generator
US20050002531A1 (en) * 2003-04-23 2005-01-06 Michaelsen David L. Randomization-based encryption apparatus and method
US7346160B2 (en) 2003-04-23 2008-03-18 Michaelsen David L Randomization-based encryption apparatus and method
US20050194993A1 (en) * 2004-02-25 2005-09-08 Peter Lablans Single and composite binary and multi-valued logic functions from gates and inverters
US8374289B2 (en) 2004-02-25 2013-02-12 Ternarylogic Llc Generation and detection of non-binary digital sequences
US7218144B2 (en) 2004-02-25 2007-05-15 Ternarylogic Llc Single and composite binary and multi-valued logic functions from gates and inverters
US7580472B2 (en) 2004-02-25 2009-08-25 Ternarylogic Llc Generation and detection of non-binary digital sequences
US20050184888A1 (en) * 2004-02-25 2005-08-25 Peter Lablans Generation and detection of non-binary digital sequences
US7696785B2 (en) 2004-02-25 2010-04-13 Ternarylogic Llc Implementing logic functions with non-magnitude based physical phenomena
US20090128190A1 (en) * 2004-02-25 2009-05-21 Peter Lablans Implementing Logic Functions with Non-Magnitude Based Physical Phenomena
US7548092B2 (en) 2004-02-25 2009-06-16 Ternarylogic Llc Implementing logic functions with non-magnitude based physical phenomena
US20060045309A1 (en) * 2004-06-14 2006-03-02 Shan Suthaharan Systems and methods for digital content security
US20060021003A1 (en) * 2004-06-23 2006-01-26 Janus Software, Inc Biometric authentication system
US20060031278A1 (en) * 2004-08-07 2006-02-09 Peter Lablans Multi-value digital calculating circuits, including multipliers
US7562106B2 (en) 2004-08-07 2009-07-14 Ternarylogic Llc Multi-value digital calculating circuits, including multipliers
US20100164548A1 (en) * 2004-09-08 2010-07-01 Ternarylogic Llc Implementing Logic Functions With Non-Magnitude Based Physical Phenomena
US20080304664A1 (en) * 2007-06-07 2008-12-11 Shanmugathasan Suthaharan System and a method for securing information
US20110249814A1 (en) * 2010-04-08 2011-10-13 Nagravision S.A. Device and a method for performing a cryptographic function
US8355500B2 (en) * 2010-04-08 2013-01-15 Nagravision S.A. Device and a method for performing a cryptographic function
US10277438B2 (en) * 2010-07-26 2019-04-30 John David Terry Method and apparatus for communicating data in a digital chaos communication system
US20120250783A1 (en) * 2010-07-26 2012-10-04 John David Terry Method and Apparatus for Communicating Data in a Digital Chaos Communication System
US8873604B2 (en) * 2012-03-26 2014-10-28 John David Terry Method and apparatus for multiple signal aggregation and reception in digital chaos network
US20150002064A1 (en) * 2013-06-28 2015-01-01 Samsung Electro-Mechanics Co., Ltd. Circuit for detecting rotor position, apparatus and method for motor driving control using the same
WO2016099724A1 (en) * 2014-12-18 2016-06-23 Cryptography Research, Inc. A self-timed random number generator
US10095477B2 (en) 2014-12-18 2018-10-09 Cryptography Research Inc. Self-timed random number generator
US10503476B2 (en) 2014-12-18 2019-12-10 Cryptography Research, Inc. Self-timed random number generator
US10754620B2 (en) 2014-12-18 2020-08-25 Cryptography Research Inc. Self-timed random number generator
US11301216B2 (en) 2014-12-18 2022-04-12 Cryptography Research, Inc. Self-timed random number generator
US9479217B1 (en) 2015-07-28 2016-10-25 John David Terry Method and apparatus for communicating data in a digital chaos cooperative network
CN111538476A (zh) * 2020-04-20 2020-08-14 佳缘科技股份有限公司 一种提高输出序列随机性的细粒度校正方法
CN112328203A (zh) * 2020-10-16 2021-02-05 郑州信大捷安信息技术股份有限公司 一种随机数发生器及发生方法
CN112328203B (zh) * 2020-10-16 2022-02-22 郑州信大捷安信息技术股份有限公司 一种随机数发生器及发生方法

Also Published As

Publication number Publication date
JP2000310942A (ja) 2000-11-07
KR20000062620A (ko) 2000-10-25
KR100396243B1 (ko) 2003-09-02

Similar Documents

Publication Publication Date Title
US6788787B1 (en) Pseudorandom number generator, stream encryption method, and stream encrypting communication method
CA2474856C (en) Method and apparatus for generating a stream cipher
Dachselt et al. Chaos and cryptography
CA1289640C (en) Nonlinear random sequence generators
KR101393806B1 (ko) 다단계 물리적 복제 불가 함수 시스템
US20070019811A1 (en) Cryptographic key, encryption device, encryption/decryption device, cryptographic key management device, and decryption device
JPH09509748A (ja) 非決定論的公開キー暗号化システム
KR100800468B1 (ko) 저전력 고속 동작을 위한 하드웨어 암호화/복호화 장치 및그 방법
AU762617B2 (en) Duty cycle corrector for a random number generator
Tang et al. Encrypted physical layer communications using synchronized hyperchaotic maps
Upadhyay et al. Randomness analysis of A5/1 Stream Cipher for secure mobile communication
KR20010041202A (ko) 이산 데이터 블록 암호화 방법
Brosas et al. Modified OTP based Vernam Cipher algorithm using multilevel encryption method
JP2864813B2 (ja) 暗号化装置及び復号化装置
Abumuala et al. A new method for generating cryptographically strong sequences of pseudo random bits for stream cipher
Jassim et al. Using a Hybrid Pseudorandom Number Generator for Cryptography in the Internet of Things
Albeer et al. Key stream cipher based on coloured petri nets
Saraswathy et al. Randomness properties of sequence generated using logistic map with novel permutation and substitution techniques
Prajapat et al. Implementation of Enhanced A5/1 Stream Cipher and its Randomness Analysis by NIST Test Suite
Brock Linear Feedback Shift Registers and Cyclic Codes in SAGE
Prajapat et al. Information security enhancement by increased randomness of stream ciphers in GSM
Brock Linear Feedback Shift Registers in SAGE
Prajapat et al. Information Security Enhancement by Increasing Randomness of Stream Ciphers in GSM
Kholosha Investigations in the Design and Analysis of Key-stream Generators
Wagaj et al. Implementation of RC4 stream cipher using FPGA

Legal Events

Date Code Title Description
AS Assignment

Owner name: MICRO- TECHNOLOGY CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHONO, KATSUFUSA;UENO, OSAMU;ISHIHARA, TETSUYA;REEL/FRAME:010884/0199;SIGNING DATES FROM 20000508 TO 20000509

Owner name: YAZAKI CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHONO, KATSUFUSA;UENO, OSAMU;ISHIHARA, TETSUYA;REEL/FRAME:010884/0199;SIGNING DATES FROM 20000508 TO 20000509

AS Assignment

Owner name: YAZAKI CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRO-TECHNOLOGY CORPORATION;REEL/FRAME:012960/0120

Effective date: 20020326

CC Certificate of correction
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20080907