US6717450B1 - Monolithic I-load architecture for automatic test equipment - Google Patents

Monolithic I-load architecture for automatic test equipment Download PDF

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Publication number
US6717450B1
US6717450B1 US10/144,175 US14417502A US6717450B1 US 6717450 B1 US6717450 B1 US 6717450B1 US 14417502 A US14417502 A US 14417502A US 6717450 B1 US6717450 B1 US 6717450B1
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voltage
output voltage
pin output
buffered
current
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Lloyd F. Linder
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Microelectronics Technology Inc
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TelASIC Communications Inc
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Priority to PCT/US2003/014456 priority patent/WO2003098231A2/fr
Priority to AU2003269419A priority patent/AU2003269419A1/en
Priority to TW092112787A priority patent/TW200402541A/zh
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Assigned to MICROELECTRONICS TECHNOLOGY, INC. reassignment MICROELECTRONICS TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TELASIC COMMUNICATIONS, INC.
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers

Definitions

  • the disclosed invention relates generally to automatic test equipment (ATE) used for automated production line testing of multi-pin integrated circuits, and particularly to active load circuits employed in such test equipment.
  • An active load circuit is connected to a pin that is being monitored for response to test signals applied to other pins of the integrated circuit device under test (DUT).
  • DUT integrated circuit device under test
  • Pin cards that include circuitry for connection to a corresponding pin of an integrated circuit device under test.
  • Each pin card includes a pin driver circuit that supplies a test signal to the associated pin, and an active load circuit that sources or sinks a current depending upon the output voltage of the pin.
  • the pin driver and the active circuit are switchably connectable to a corresponding pin of the device under test, such that the pin is connected to either the pin driver or the active load at any given time.
  • an active load can be considered as being in the ACTIVE mode when it is connected to the pin, and in the INHIBIT mode when it is disconnected from the pin.
  • the circuitry employed to switch a pin between the active load and the pin driver commonly includes Schottky diodes arranged in a bridge.
  • One or more of the Schottky diodes is subjected to relatively large levels of reverse bias as the output voltage on a pin swings over a typical range such as ⁇ 2 to 7 volts.
  • the large reverse bias can cause leakage currents as well as degradation of the forward action characteristics.
  • the leakage currents must be extremely low in the INHIBIT mode, but can be acceptable in the ACTIVE mode so long as the leakage does not affect the functionality of the active load circuit.
  • An active load circuit includes a current source; a current sink; a current switching switching circuit having current source and current sink nodes respectively connected to the current source and the current sink; and a control circuit for controlling the current switching circuit with a differential voltage that is limited in amplitude and of the same polarity as the difference between a fixed reference voltage and a pin output voltage of a device under test.
  • FIG. 1 is a schematic diagram of an active load circuit that employs the invention.
  • FIG. 2 is a schematic diagram of another active load circuit that employs the invention.
  • FIG. 3 is a schematic diagram of a further active load circuit that employs the invention.
  • FIG. 1 illustrates an active load circuit that includes a Schottky diode ring or bridge formed of diodes D 1 -D 4 .
  • a differential switch pair of NPN transistors Q 1 , Q 2
  • a differential switch pair of PNP transistors Q 3 , Q 4
  • the node between the Schottky diodes D 1 , D 2 is connected to the device pin which provides a pin output voltage VDUT.
  • Each of the switch pairs (Q 1 , Q 2 ), (Q 3 , Q 4 ) is controlled by differential inhibit mode control signals INH′ and INH, and each of the currents I L and I H can be in the order of 0-50 mA.
  • the buffer B 1 limits leakage current when the active load circuit is in the INHIBIT mode.
  • NPN transistors Q 13 , 014 provide current from a current source I 1 to NPN transistors Q 5 and Q 6
  • PNP transistors Q 17 and Q 18 provide current from a current source I 1 to PNP transistors Q 7 and Q 8 .
  • the transistors Q 13 , Q 14 , Q 17 , Q 18 receive the inhibit control signal INH at their base terminals, and in the ACTIVE mode (i.e., INH and INH′ are inactive and active, respectively), are off, such that the transistors Q 5 -Q 8 are resultantly off in the ACTIVE mode. Also, this action causes NPN transistor Q 9 , PNP transistor Q 10 , NPN transistor Q 21 , and PNP transistor Q 22 to be off in the ACTIVE mode.
  • PNP transistor Q 16 and NPN transistor Q 15 receive the inverted inhibit mode control signal INH′ at their base terminals, and thus are on in the ACTIVE mode, thereby supplying current to a PNP transistor Q 19 and an NPN transistor Q 20 .
  • the transistors Q 19 , Q 20 , Q 11 , and Q 12 form a complementary class AB unity gain buffer that provides a buffered version of VCOM′ to drive the Schottky diode bridge.
  • VCOM′ is a voltage that tracks the magnitude of the pin output voltage VDUT relative to a fixed reference voltage VCOM in such a manner that (VDUT ⁇ VCOM′) is limited in amplitude and is of the same polarity as (VDUT ⁇ VCOM).
  • VCOM′ does not have the same value as VCOM in voltage, but must be able to sink and source the load currents I H and I L in the range of 0-50 mA at the transistors Q 11 and Q 12 .
  • This architecture is to provide a low reverse bias for the Schottky diode bridge in both ACTIVE and INHIBIT modes.
  • an additional circuit comprised of NPN transistors Q 23 -Q 26 , a resistor RE, Schottky diodes D 5 -D 8 , current sources I O and I E , and a buffer B 2 provides VCOM′.
  • the buffer B 2 provides a buffered version of the pin output voltage VDUT voltage that serves as a reference for VCOM′.
  • the additional circuit allows VCOM′ and the Schottky diode bridge to track VDUT, which prevents the Schottky diode bridge from experiencing large voltage excursions.
  • VDUT In the ACTIVE mode, when VDUT is substantially equal to VCOM, the differentially coupled pair of transistors Q 23 , Q 26 is balanced, and the voltage VCOM′ presented to the Schottky diode bridge is substantially equal to VDUT.
  • VCOM′ As VDUT increases relative to VCOM, VCOM′ decreases non-linearly as a function of VDUT, and will clamp two Schottky diode drops below VDUT, while VDUT is greater than VCOM.
  • the voltage applied to the Schottky diode bridge will be on the order of one Schotkky diode drop V D , which will be the worst case reverse bias, as opposed to (9 ⁇ V D ) volts in known active load circuits.
  • VCOM′ will increase to a maximum of two Schottky diode drops above VDUT, which will provide a Schottky diode worst case reverse bias.
  • This circuitry is provided to assure that the Schottky diodes in the bridge don't get overstressed.
  • the complexity is made difficult by the fact that no matter whether VDUT greater than or less than VCOM, it would be advantageous for VCOM′ to track VDUT, so that the voltage drops across the Schottky bridge for the off diodes are kept low.
  • the transistors Q 23 -Q 26 and the associated current sources compare the pin output voltage VDUT to the reference voltage VCOM.
  • VDUT goes above or below VCOM
  • the Schottky diodes (D 5 , D 7 ) or (D 6 , D 8 ) turn on, and provide a voltage that tracks, or is bootstrapped to, VDUT so that the Schottky diode bridge (D 1 -D 4 ) is protected from breakdown in the ACTIVE mode.
  • the resistor RE is included in the differential pair Q 23 , Q 26 and is sufficiently large so that the differential pair operates in a linear region and never fully switches. In this manner, the transistors Q 23 , Q 26 do not experience reverse base emitter voltages that exceed the reverse base emitter breakdown voltage.
  • VCOM′ tracks VDUT as follows:
  • the inhibit mode control signals (INH, INH′) are active and inactive, respectively, and transistors Q 2 , Q 4 , Q 13 , Q 14 , Q 17 , Q 18 are on, while transistors Q 1 , Q 3 , Q 15 , Q 16 are off.
  • the current to the Schottky bridge is accordingly turned off.
  • the currents in transistors Q 13 , Q 14 , Q 17 , and Q 18 turn on the transistors Q 5 , Q 6 , Q 7 , and Q 8 , respectively.
  • These devices turning on turn on the transistors Q 9 , Q 10 , Q 21 , and Q 22 .
  • the transistors Q 6 , Q 7 , Q 9 and Q 10 comprise a class AB buffer that bootstraps VCOM′ and the top and bottom of the Schottky bridge to VDUT with unity gain.
  • VDUT swings +7 to ⁇ 2 volts (worst case)
  • each of the Schottky diodes D 1 -D 4 is bootstrapped and reverse-biased, by one base-emitter diode drop, relative to the VDUT voltage.
  • the VCOM′ buffer is also shut off and reverse-biased through the action of Q 21 , Q 22 , Q 5 , Q 8 which comprise a class AB buffer.
  • the worst case reverse bias is one base-emitter voltage.
  • the diodes (D 5 , D 7 ) and (D 6 , D 8 ) will resultantly have zero bias across them and are bootstrapped relative to VDUT in the INHIBIT mode.
  • Q 22 will absorb the current I O , as well as the signal current out of the collector of Q 26 . If it is determined that this signal current is a problem, the Q 23 -Q 26 circuitry can be inhibited in the INHIBIT mode.
  • the diodes D 7 and D 8 can be replaced by resistors, or a Schottky diode and resistor network.
  • An advantage of the architecture of FIG. 1 is that the Schottky diode bridge never experiences large voltage excursions, relative to VDUT, in either the ACTIVE or INHIBIT modes.
  • a significant portion of the circuitry of FIG. 1 is included as a precaution to insure that there are no large signal swings in the Schottky diode bridge or the VCOM′ buffer in the INHIBIT mode. It is possible that through bootstrapping action such circuitry is not required, and can be omitted to provide the active load circuit of FIG. 2 .
  • the VCOM buffer (transistors Q 19 , Q 20 , Q 11 , Q 12 ) is bootstrapped to VDUT, above it by 2 Schottky diodes, or below it by 2 Schottky diode drops.
  • Q 1 and Q 3 are off, and Q 2 and Q 4 are on, and the programmable currents I H and I L flow through these transistors.
  • the Schottky diode bridge is off in the INHIBIT mode and there will be a worst case voltage difference of two Schottky diodes between the VDUT node and the buffered VCOM′ node.
  • the active load circuit of FIG. 2 basically comprises the ACTIVE mode circuitry of the active load circuit of FIG. 1 but wherein INHIBIT is accomplished by shutting off the Schottky diode bridge currents only.
  • the active load circuit of FIG. 1 is a more conservative implementation, and considerations in determining whether to implement the active load circuit of FIG. 1 or FIG. 2 can include INHIBIT mode leakage, speed, settling, and/or power requirements.
  • FIG. 3 schematically depicted therein is a complementary bipolar only active load circuit that avoids the use of Schottky diodes, for example to avoid leakages associated with parasitic devices in a Schottky diode.
  • the reverse-bias stress that can be applied to a Schottky diode may be too low for a particular application, or the reverse-bias leakage current of the schottky diode may be unacceptably high for the INHIBIT mode.
  • the pin output voltage VDUT and the fixed reference voltage VCOM are the same voltages as in FIGS. 1 and 2.
  • the voltage difference between VCOM and VDUT can be as large as 9 volts.
  • the circuitry comprised of a differentially coupled NPN transistor switch pair (Q 61 , Q 62 ), a differentially coupled PNP transistor switch pair (Q 63 , Q 64 ), resistors R 1 -R 6 , and current sources I 11 reduces and level shifts the voltage difference between VDUT and VCOM through attenuation of the signal swing to drive a differential NPN transistor switch pair (Q 65 , Q 66 ) and a differential PNP transistor switch pair (Q 71 , Q 72 ) via suitable buffers.
  • transistors Q 61 -Q 64 attenuate the large swing on VDUT by having a gain that is less than 1, such that the differential NPN transistor switch pair (Q 65 , Q 66 ) and the differential PNP transistor switch pair (Q 71 , Q 72 ) are driven with a version of the voltage difference between VDUT and VCOM having a reduced or attenuated voltage swing as compared to the voltage swing of the voltage difference between VDUT and VCOM.
  • This can also be accomplished by a resistive attenuator before the differential switch pairs.
  • the active load circuit of FIG. 3 also includes a zero input current buffer B 1 at the VDUT pin so that the leakage is low in the INHIBIT mode. It should be noted that VCOM no longer has to source and sink the I H and I L currents. This is now accomplished by the VREF function in this architecture.
  • the switch pairs (Q 65 , Q 66 ) and (Q 71 , Q 72 ) will switch I L or I H , depending on the value of VDUT, into or out of the pin, respectively.
  • Differential switch pairs (Q 67 , Q 68 ) and (Q 69 , Q 70 ) receive differential inhibit control mode signals (INH, INH′) and function to isolate the I H and I L currents from VDUT during the INHIBIT mode.
  • VDUT in the INHIBIT mode, VDUT will still be switching, worst case, and the collector-base breakdown of the transistors Q 67 and Q 69 must be greater than 10V, with the resulting leakage currents on the order of zero amps. If for a given complementary bipolar process the voltage swing exceeds the collector-base breakdown voltage, this can be addressed by bootstrapping the differential signals INH and INH′ to VDUT. This bootstrapped signal is an attenuated version of VDUT which will not only protect the differential switch pairs (Q 67 , Q 68 ) and (Q 69 , Q 70 ), but also the transistors Q 65 , Q 66 , Q 71 , Q 72 .
  • a PNP switch pair will drive switch pair (Q 67 , Q 68 ) as is the case for (Q 63 , Q 64 ) driving (Q 65 , Q 66 ).
  • an NPN switch pair will drive (Q 69 , Q 70 ) as is the case for (Q 61 , Q 62 ) driving (Q 71 , Q 72 ). If the devices are sized properly, the current responses will be symmetrical.
  • this architecture provides the same functionality as the Schottky bridge implementation without the use of Schottky diodes.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Amplifiers (AREA)
  • Tests Of Electronic Circuits (AREA)
US10/144,175 2002-05-13 2002-05-13 Monolithic I-load architecture for automatic test equipment Expired - Lifetime US6717450B1 (en)

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Application Number Priority Date Filing Date Title
US10/144,175 US6717450B1 (en) 2002-05-13 2002-05-13 Monolithic I-load architecture for automatic test equipment
PCT/US2003/014456 WO2003098231A2 (fr) 2002-05-13 2003-05-09 Architectures a courants de charge i monolithiques pour equipement de test automatique
AU2003269419A AU2003269419A1 (en) 2002-05-13 2003-05-09 Monolithic i-load architectures for automatic test equipment
TW092112787A TW200402541A (en) 2002-05-13 2003-05-12 Monolithic I-load architectures for automatic test equipment

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US10/144,175 US6717450B1 (en) 2002-05-13 2002-05-13 Monolithic I-load architecture for automatic test equipment

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AU (1) AU2003269419A1 (fr)
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WO (1) WO2003098231A2 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030227318A1 (en) * 2002-02-22 2003-12-11 Cord-Heinrich Kohsiek Circuit arrangement for a current-controlled resistor having an enlarged linear range
US20050146320A1 (en) * 2003-12-31 2005-07-07 Gohel Tushar K. Differential active load
US20060123301A1 (en) * 2004-10-19 2006-06-08 James Wey Transconductance stage operating as an active load for pin electronics
US20160149560A1 (en) * 2014-11-21 2016-05-26 Keithley Instruments, Inc. Voltage clamp
US10209307B2 (en) 2016-05-23 2019-02-19 Analog Devices, Inc. Multiple-level driver circuit with non-commutating bridge
CN110291410A (zh) * 2017-01-06 2019-09-27 艾利维特半导体公司 低功率有源负载

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111090036B (zh) * 2019-12-30 2022-01-25 上海华岭集成电路技术股份有限公司 一种基于ate的芯片动态负载测试方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5010297A (en) 1989-12-01 1991-04-23 Analog Devices, Incorporated Automatic test equipment with active load having high-speed inhibit mode switching
US5350952A (en) 1992-07-06 1994-09-27 Hughes Aircraft Company Sample and hold circuit with push-pull output charging current
US5745003A (en) * 1996-09-11 1998-04-28 Schlumberger Technologies Inc. Driver circuits for IC tester
US6157224A (en) 1998-12-23 2000-12-05 Raytheon Company High speed pin driver integrated circuit architecture for commercial automatic test equipment applications
US6211723B1 (en) * 1999-01-20 2001-04-03 Ltx Corporation Programmable load circuit for use in automatic test equipment

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5010297A (en) 1989-12-01 1991-04-23 Analog Devices, Incorporated Automatic test equipment with active load having high-speed inhibit mode switching
US5350952A (en) 1992-07-06 1994-09-27 Hughes Aircraft Company Sample and hold circuit with push-pull output charging current
US5745003A (en) * 1996-09-11 1998-04-28 Schlumberger Technologies Inc. Driver circuits for IC tester
US6157224A (en) 1998-12-23 2000-12-05 Raytheon Company High speed pin driver integrated circuit architecture for commercial automatic test equipment applications
US6211723B1 (en) * 1999-01-20 2001-04-03 Ltx Corporation Programmable load circuit for use in automatic test equipment

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030227318A1 (en) * 2002-02-22 2003-12-11 Cord-Heinrich Kohsiek Circuit arrangement for a current-controlled resistor having an enlarged linear range
US6861893B2 (en) * 2002-02-22 2005-03-01 Koninklijke Philips Electronics N.V. Circuit arrangement for a current-controlled resistor having an enlarged linear range
US20050146320A1 (en) * 2003-12-31 2005-07-07 Gohel Tushar K. Differential active load
US20060123301A1 (en) * 2004-10-19 2006-06-08 James Wey Transconductance stage operating as an active load for pin electronics
US20160149560A1 (en) * 2014-11-21 2016-05-26 Keithley Instruments, Inc. Voltage clamp
EP3026442A1 (fr) * 2014-11-21 2016-06-01 Keithley Instruments, Inc. Limiteur de tension
US9742379B2 (en) * 2014-11-21 2017-08-22 Keithley Instruments, Llc Voltage clamp
US10209307B2 (en) 2016-05-23 2019-02-19 Analog Devices, Inc. Multiple-level driver circuit with non-commutating bridge
CN110291410A (zh) * 2017-01-06 2019-09-27 艾利维特半导体公司 低功率有源负载
EP3566063A4 (fr) * 2017-01-06 2020-09-09 Elevate Semiconductor, Inc. Charge active de faible puissance
CN110291410B (zh) * 2017-01-06 2021-10-26 艾利维特半导体公司 低功率有源负载
US11209485B2 (en) 2017-01-06 2021-12-28 Elevate Semiconductor, Inc. Low power active load

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TW200402541A (en) 2004-02-16
AU2003269419A8 (en) 2003-12-02
WO2003098231A3 (fr) 2004-04-29
AU2003269419A1 (en) 2003-12-02
WO2003098231A2 (fr) 2003-11-27

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