US6551900B1 - Trench gate oxide formation method - Google Patents

Trench gate oxide formation method Download PDF

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US6551900B1
US6551900B1 US09/547,730 US54773000A US6551900B1 US 6551900 B1 US6551900 B1 US 6551900B1 US 54773000 A US54773000 A US 54773000A US 6551900 B1 US6551900 B1 US 6551900B1
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oxide layer
trench
thickness
corners
oxide
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US09/547,730
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Yifu Chung
Leon Chang
Ping-Wei Lin
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Promos Technologies Inc
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    • H10D64/0134—
    • H10D64/01342—
    • H10D64/01346—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/683—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being parallel to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors

Definitions

  • the present invention pertains to a semiconductor device process, and more specifically, to method of improving the gate oxide thinning issue at the trench corner.
  • trench structure in the semiconductor structure to increase the integrity has become more and more popular.
  • the trench structure can be applied to a variety of semiconductor processes.
  • the trench structure can use as trench capacitor to increase the integrity of the IC.
  • Either deep trench or stacked structure can increase the electrode plate area so as to increase the capacitance.
  • the trench isolation technology is widely used to semiconductor device isolation so as to improve the bird beak, which occupies larger planar area.
  • the trench diffused MOS transistor (DMOS) is a MOS transistor formed in the trench for the application to the high power IC.
  • a problem about the gate oxide thinning issue at the trench corners will occur when a thermal oxidation is carried out to form a gate oxide on the sidewall and the bottom of trench.
  • the corner denoted by 30 between the sidewall 10 and the bottom 20 shows the thinning gate oxide.
  • the thinning corner gate oxide will result in leakage current issue. If the problem is not solved, the benefits associated with the recessed channel will be significantly canceled.
  • the present invention disclosed a method for improving gate oxide thinning issue at trench corners to prevent leakage current therefrom.
  • the method comprises steps as follows. Firstly, a silicon substrate having a trench therein is provided. A HDPCVD technology to form a first oxide layer on the sidewall and the bottom of the trench is carried out. After performing an etchback to leave the first oxide layer on the bottom of the trench, a second oxide layer is formed on the first oxide layer and on sidewalls of the trench by a LPCVD technology. Thereafter, an isotropic etching is performed so as to remove a substantially portion of the second oxide layer and leave a remnant portion of second oxide layer on the trench corners. Consequently, the trench corners are smooth. Finally, a thermal oxidation to form a third oxide layer on the sidewall of the trench is carried to accomplish the gate oxide formation.
  • FIG. 1 is a cross-sectional view of a silicon substrate with a thinning gate oxide at the trench corners according to the prior art.
  • FIG. 2 is a cross-sectional view of a silicon substrate with silicon nitride hard mask to define a trench according to the present invention.
  • FIG. 3 is a cross-sectional view of the step of forming a first oxide layer on the sidewall and bottom of the trench by HDPCVD method and then etch back to left first oxide layer on the bottom according to the present invention.
  • FIG. 4 is a cross-sectional view of forming a second oxide layer on the sidewall and bottom of the trench by LPCVD method according to the present invention
  • FIG. 5 is a cross-sectional view of performing an etchback to left portions of the second oxide on the trench corners according to the present invention.
  • FIG. 6 is a cross-sectional view of forming a gate oxide layer by performing thermal oxidation process according to the present invention.
  • the trench structure increases the integrity of the IC while applying in the trench transistor or trench capacitor as is depicted in the forgoing prior art.
  • a thinning gate oxide in the corner of the trench is easily generated as the gate oxide is formed by a thermal process.
  • the thinning gate oxide problem may cause current leakage that requires to be overcome.
  • the present invention is in terms of one HDPCVD (high density plasma CVD) process to deposited an oxide layer incorporated with an etchback process and one LPCVD (low pressure CVD) to form another conformal oxide layer and then perform etchback again before performing the thermal oxidation to solve aforementioned issue.
  • HDPCVD high density plasma CVD
  • LPCVD low pressure CVD
  • FIG.2 shows a results of cross-sectional view.
  • a thin pad oxide layer 110 is thermally grown or deposited by CVD method on a ⁇ 001 > orientation silicon substrate 100 ; thereafter a thick silicon nitride layer 120 deposited by PECVD or LPCVD process is followed.
  • a photoresist pattern (not shown) and an etching process are followed to pattern the silicon nitride layer 120 in a desired position.
  • an anisotropic etching process using nitride layer as a hard mask is conducted to form a recessed trench region 130 (see FIG. 3) in the silicon substrate 100 .
  • Using hot H 3 PO 4 solution to remove the silicon nitride layer 120 and BOE or diluted HF solution to remove the pad oxide layer 110 are subsequently performed.
  • the trench 130 has a depth of about 1.8-2.2 ⁇ m.
  • FIG. 2 to FIG. 5 shows the pretreatment processes before performing thermal oxidation to alleviate the thinning oxide of trench corner issue.
  • a first oxide layer is deposited on the sidewalls and the bottom of the trench 130 .
  • the first oxide layer is about 360 to 440 nm by a high density plasma CVD (HDPCVD) process at a temperature of about 390 to 440° C.
  • HDPCVD high density plasma CVD
  • an etchback is performed so that there is only bottom of the trench left with the first oxide layer 140 .
  • the remaining oxide layer is about 160 to 240 nm in thickness.
  • FIG. 3 shows the results of above processes.
  • a conformal second oxide layer 150 by a low pressure CVD is formed on the sidewalls and the bottom of the trench 130 .
  • the second oxide layer 150 is deposited at a temperature of about 700 to 740° C. and the thickness of the second oxide layer is about 135-165 nm.
  • an anneal process at a temperature of about 850-950° C. is done. The anneal process is performed to improve the uniform coverage of the second oxide layer 150 and to reduce the etching rate to the second oxide layer 150 so as to increase the process window.
  • an isotropic etching process such as a wet etching, is performed to etch back a main portion of the second oxide layer 150 and leave a portion of second oxide layer 150 on the corner of the trench 130 .
  • an isotropic etching process such as a wet etching
  • 0.5% to 1% HF can provide a good process window which is about 30 second.
  • the remnant second oxide layer 150 is about 50-100 nm in thickness.
  • the smooth corners are resulted as denoted by arrow 160 .
  • a thermal oxidation is achieved to form a third oxide layer 170 at a temperature of about 840-860° C.
  • the third oxide layer 170 is about 45-55 nm in thickness. There is no thinning corner gate oxide issue to occur.

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Abstract

A method for improving gate oxide thinning issue at trench corners is disclosed. The method comprises steps as follows. Firstly, a silicon substrate having a trench therein is provided. HDPCVD technology to form a first oxide layer on the sidewall and the bottom of the trench is carried out. After performing an etchback to leave the first oxide layer on the bottom of the trench, a second oxide layer is formed on the first oxide layer and on sidewalls of the trench by LPCVD technology. Thereafter, an isotropic etching is performed so as to remove a substantially portion of the second oxide layer and leave a remnant portion of second oxide layer on the trench corners. As a consequently, the trench corners are smooth. Finally, a thermal oxidation to form a third oxide layer on the sidewall of the trench is carried achieved to accomplish the gate oxide formation.

Description

RELATED APPLICATIONS
This application claims priority from Taiwan Patent Application No. 88121607, filed Dec. 9, 1999, incorporated herein by reference.
1. Field of the Invention
The present invention pertains to a semiconductor device process, and more specifically, to method of improving the gate oxide thinning issue at the trench corner.
2. Background of the Invention
With the advent of the integrated circuit (IC), forming trench structure in the semiconductor structure to increase the integrity has become more and more popular. The trench structure can be applied to a variety of semiconductor processes. For instance, the trench structure can use as trench capacitor to increase the integrity of the IC. Either deep trench or stacked structure can increase the electrode plate area so as to increase the capacitance. Furthermore, the trench isolation technology is widely used to semiconductor device isolation so as to improve the bird beak, which occupies larger planar area. Still, the trench diffused MOS transistor (DMOS) is a MOS transistor formed in the trench for the application to the high power IC.
However, a problem about the gate oxide thinning issue at the trench corners will occur when a thermal oxidation is carried out to form a gate oxide on the sidewall and the bottom of trench. As shown in FIG. 1, the corner denoted by 30 between the sidewall 10 and the bottom 20 shows the thinning gate oxide. As is known skilled in the art, the thinning corner gate oxide will result in leakage current issue. If the problem is not solved, the benefits associated with the recessed channel will be significantly canceled.
SUMMARY OF THE INVENTION
The present invention disclosed a method for improving gate oxide thinning issue at trench corners to prevent leakage current therefrom. The method comprises steps as follows. Firstly, a silicon substrate having a trench therein is provided. A HDPCVD technology to form a first oxide layer on the sidewall and the bottom of the trench is carried out. After performing an etchback to leave the first oxide layer on the bottom of the trench, a second oxide layer is formed on the first oxide layer and on sidewalls of the trench by a LPCVD technology. Thereafter, an isotropic etching is performed so as to remove a substantially portion of the second oxide layer and leave a remnant portion of second oxide layer on the trench corners. Consequently, the trench corners are smooth. Finally, a thermal oxidation to form a third oxide layer on the sidewall of the trench is carried to accomplish the gate oxide formation.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIG. 1 is a cross-sectional view of a silicon substrate with a thinning gate oxide at the trench corners according to the prior art.
FIG. 2 is a cross-sectional view of a silicon substrate with silicon nitride hard mask to define a trench according to the present invention.
FIG. 3 is a cross-sectional view of the step of forming a first oxide layer on the sidewall and bottom of the trench by HDPCVD method and then etch back to left first oxide layer on the bottom according to the present invention.
FIG. 4 is a cross-sectional view of forming a second oxide layer on the sidewall and bottom of the trench by LPCVD method according to the present invention;
FIG. 5 is a cross-sectional view of performing an etchback to left portions of the second oxide on the trench corners according to the present invention.
FIG. 6 is a cross-sectional view of forming a gate oxide layer by performing thermal oxidation process according to the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Although the trench structure increases the integrity of the IC while applying in the trench transistor or trench capacitor as is depicted in the forgoing prior art. A thinning gate oxide in the corner of the trench is easily generated as the gate oxide is formed by a thermal process. The thinning gate oxide problem may cause current leakage that requires to be overcome. The present invention is in terms of one HDPCVD (high density plasma CVD) process to deposited an oxide layer incorporated with an etchback process and one LPCVD (low pressure CVD) to form another conformal oxide layer and then perform etchback again before performing the thermal oxidation to solve aforementioned issue.
The detailed processes will be described as follows.
Referring to FIG.2; shows a results of cross-sectional view. A thin pad oxide layer 110 is thermally grown or deposited by CVD method on a <001> orientation silicon substrate 100; thereafter a thick silicon nitride layer 120 deposited by PECVD or LPCVD process is followed. A photoresist pattern (not shown) and an etching process are followed to pattern the silicon nitride layer 120 in a desired position. After stripping the photoresist, an anisotropic etching process using nitride layer as a hard mask is conducted to form a recessed trench region 130 (see FIG. 3) in the silicon substrate 100. Using hot H3PO4 solution to remove the silicon nitride layer 120 and BOE or diluted HF solution to remove the pad oxide layer 110 are subsequently performed. In a preferred embodiment, the trench 130 has a depth of about 1.8-2.2 μm.
FIG. 2 to FIG. 5 shows the pretreatment processes before performing thermal oxidation to alleviate the thinning oxide of trench corner issue. Please refer to FIG. 3, a first oxide layer is deposited on the sidewalls and the bottom of the trench 130. Preferably, the first oxide layer is about 360 to 440 nm by a high density plasma CVD (HDPCVD) process at a temperature of about 390 to 440° C. Thereafter, an etchback is performed so that there is only bottom of the trench left with the first oxide layer 140. The remaining oxide layer is about 160 to 240 nm in thickness. FIG. 3 shows the results of above processes.
Referring to FIG. 4, a conformal second oxide layer 150 by a low pressure CVD (LPCVD) is formed on the sidewalls and the bottom of the trench 130. In a preferred embodiment, the second oxide layer 150 is deposited at a temperature of about 700 to 740° C. and the thickness of the second oxide layer is about 135-165 nm. Subsequently, an anneal process at a temperature of about 850-950° C. is done. The anneal process is performed to improve the uniform coverage of the second oxide layer 150 and to reduce the etching rate to the second oxide layer 150 so as to increase the process window. Thereafter, an isotropic etching process such as a wet etching, is performed to etch back a main portion of the second oxide layer 150 and leave a portion of second oxide layer 150 on the corner of the trench 130. Preferably, 0.5% to 1% HF can provide a good process window which is about 30 second. The remnant second oxide layer 150 is about 50-100 nm in thickness. The smooth corners are resulted as denoted by arrow 160.
Finally, referring to FIG.6, a thermal oxidation is achieved to form a third oxide layer 170 at a temperature of about 840-860° C. The third oxide layer 170 is about 45-55 nm in thickness. There is no thinning corner gate oxide issue to occur.
As is understood by a person skilled in the art, the foregoing preferred embodiment of the present invention is an illustration of the present invention rather than limitation thereon. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.

Claims (12)

What is claimed is:
1. A method for improving thinner gate oxide at trench corners, said method comprising the steps of:
providing a silicon substrate having a trench therein;
forming a first oxide layer on the sidewalls and bottom of said trench;
performing an etchback process to leave said first oxide layer on the bottom of said trench;
performing a LPCVD process to form a second oxide layer on said first oxide layer and the sidewalls of said trench;
performing an anneal process to make uniform said second oxide layer;
performing an isotropic etching to remove a substantially portion of said second oxide layer and to leave a remnant portion of said second oxide layer on said trench corners; and
performing a thermal oxidation process to form a third oxide layer on the sidewalls of said trench.
2. The method of claim 1, wherein said first oxide layer is formed by a HDPCVD process to a thickness of about 360-440 nm at a temperature of about 390-410° C.
3. The method of claim 1, wherein the thickness of said first oxide layer is about 160-240 nm in thickness after said etchback process.
4. The method of claim 1, wherein said second oxide is formed at a temperature of about 700-740° C. to about 135-165 nm.
5. The method of claim 1, wherein said step of performing annealing process is done at a temperature of about 850-950° C.
6. The method of claim 1, wherein said isotropic etching is performed by 0.5% to 1% HF as etchant so that only a thickness about 50-100 nm of said second oxide layer is left on said trench corners.
7. The method of claim 1, wherein said third oxide layer is formed at a temperature of about 840-860° C. to a thickness of about 45-55 nm.
8. A method for improving thinner gate oxide at trench corners, said method comprising the steps of:
providing a silicon substrate having a trench therein;
performing a LPCVD process to form a first oxide layer on sidewalls and a bottom of said trench;
performing an etchback process to leave said first oxide layer on the bottom of said trench;
forming a second oxide layer on said first oxide layer and the sidewalls of said trench by a LPCVD process,
performing an anneal process to uniform said second oxide layer;
performing an isotropic etching to remove a substantial portion of said second oxide layer and to leave a remnant portion of said second oxide layer on said trench corners; and
performing a thermal oxidation process to form a third oxide layer on the sidewall of said trench.
9. The method of claim 8, wherein said first oxide layer is formed at a temperature of about 390-410° C. to a thickness of about 160-240 nm.
10. The method of claim 8, wherein said second oxide layer is formed at a temperature of about 700-740° C. to about 135-165 nm in thickness.
11. The method of claim 8, wherein said third oxide layer is formed at a temperature of about 840-860° C. to a thickness of about 45-55 nm.
12. The method of claim 8, wherein said isotropic etching is performed by 0.5% to 1% HF as etchant so that only a thickness about 50-100 nm of said second oxide layer is left on said trench corners.
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US20040058507A1 (en) * 2002-09-25 2004-03-25 Nanya Technology Corporation Manufacturing method for a shallow trench isolation region with high aspect ratio
US20090302382A1 (en) * 2006-06-07 2009-12-10 Adan Alberto O Power Ic Device and Method of Manufacturing Same
US20190259764A1 (en) * 2018-02-17 2019-08-22 Varian Semiconductor Equipment Associates, Inc. Uniform gate dielectric for dram device
CN112466933A (en) * 2021-02-04 2021-03-09 中芯集成电路制造(绍兴)有限公司 Shielded gate field effect transistor and forming method thereof

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Cited By (8)

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Publication number Priority date Publication date Assignee Title
US20040058507A1 (en) * 2002-09-25 2004-03-25 Nanya Technology Corporation Manufacturing method for a shallow trench isolation region with high aspect ratio
US6833311B2 (en) * 2002-09-25 2004-12-21 Nanya Technology Corporation Manufacturing method for a shallow trench isolation region with high aspect ratio
US20090302382A1 (en) * 2006-06-07 2009-12-10 Adan Alberto O Power Ic Device and Method of Manufacturing Same
US7902595B2 (en) * 2006-06-07 2011-03-08 Sharp Kabushiki Kaisha Power IC device and method of manufacturing same
US20190259764A1 (en) * 2018-02-17 2019-08-22 Varian Semiconductor Equipment Associates, Inc. Uniform gate dielectric for dram device
US10522549B2 (en) * 2018-02-17 2019-12-31 Varian Semiconductor Equipment Associates, Inc. Uniform gate dielectric for DRAM device
CN112466933A (en) * 2021-02-04 2021-03-09 中芯集成电路制造(绍兴)有限公司 Shielded gate field effect transistor and forming method thereof
CN112466933B (en) * 2021-02-04 2021-04-30 中芯集成电路制造(绍兴)有限公司 Shielded gate field effect transistor and method of forming the same

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