US6530005B2 - Circuit arrangement and method for creating and retrieving patch data from memory - Google Patents

Circuit arrangement and method for creating and retrieving patch data from memory Download PDF

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Publication number
US6530005B2
US6530005B2 US09/753,494 US75349401A US6530005B2 US 6530005 B2 US6530005 B2 US 6530005B2 US 75349401 A US75349401 A US 75349401A US 6530005 B2 US6530005 B2 US 6530005B2
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Prior art keywords
patch
address
data
value
circuit arrangement
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US09/753,494
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US20010013091A1 (en
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Dietmar Koschella
Joerg Franke
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TDK Micronas GmbH
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TDK Micronas GmbH
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/66—Updates of program code stored in read-only memory [ROM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching

Definitions

  • the present invention relates to a programmable integrated circuit device, and in particular to a integrated device that facilitates modifying executable program instructions and/or data stored on the integrated circuit device.
  • Microprocessors, signal processors, and the like have been known for many years in the various designs. These program-controlled units are often designed to execute programs stored in a program memory that is located within the program-controlled unit.
  • Non-volatile memory devices such as a ROM
  • a ROM is frequently used as program memory, and may be external to or integral with the program controlled unit.
  • a problem with the use of a ROM is that it is difficult to change the contents of the memory device when the executable instructions and/or data stored therein need to be updated. For example, when a new version of software/firmware is released. Replacing the ROM in its entirety with a new ROM that includes the updated firmware is often difficult and expensive.
  • One technique for updating the firmware is to use a transfer instruction that modifies the old/defective program code (i.e., a patch).
  • This transfer instruction is executed when the program accesses this defective program code at a pre-specified address assigned to this program code.
  • a certain amount of storage space in an internal or external non-volatile memory device i.e., a RAM
  • the follow-on instruction associated with the transfer instruction i.e., interrupt service routine.
  • Modified or corrected transfer follow-on instructions of this kind are often referred to as error correction instructions or patches and the associated memory is referred to as patch memory.
  • the data for the transfer follow-on instructions can be loaded into the system RAM from a system EEPROM or through an external interface.
  • an erroneous program code cannot be corrected or manipulated directly, but rather only through the detour of a transfer instruction and its associated follow-on instruction.
  • a single erroneous byte appears in a program table that is used in many program sequences, all these program sequences must be corrected and/or manipulated. Since a separate interrupt is needed for this every time, for which a correspondingly large amount of storage space must be made available on the system RAM, this technique quickly becomes rather complicated.
  • a circuit arrangement for replacement of executable program instructions and data includes a data bus, an address bus, a memory device that is coupled to the address and data buses to store executable program instructions and data, and a programmable patch-memory module also coupled to the address and data buses.
  • the patch memory module includes a patch address data storage device that stores and provides a patch address value indicative of an address within the memory device the contents of which is being updated, and a comparator that is coupled to the address bus and compares an address signal value on the address bus with the patch address value. The comparator provides a comparator status signal indicative of whether or not there is a match.
  • the patch memory module also includes a patch data storage device that stores a patch data value, and outputs the patch data value onto the data bus when the comparator status signal indicates a match.
  • the present invention facilitates correction of erroneous instructions or program sequences. For example, an address belonging to the datum that needs to be replaced is read in by the memory device via the data/address bus (as usual) and also, at the same time, by the patch-memory module.
  • the patch-memory module compares the addresses forwarded via the data/address bus to the memory with a given address pattern stored in the patch address data storage device within the module. If the address pattern in the patch-memory module agrees with the address on the address bus, the patch memory module outputs a patch data value onto the data bus, rather than allowing the memory device to output data in response to the address on the address bus.
  • the circuit arrangement preferably is an integrated circuit (i.e., the memory device and the patch-memory module are integrated on one semiconductor chip).
  • the address/data bus is an internal bus. Consequently, the patch-memory module accesses the internal address/data bus quickly and is synchronized with access to the memory.
  • the RAM essentially can be dispensed with for error correction. Only if correcting large erroneous program sequences, which are larger than the number of implemented patch data memories, does it make sense to branch off into the RAM. This can be implemented, for example, by a transfer instruction that branches off to a new, improved program sequence in the RAM. Thus even complex software or program modules can be inserted or replaced.
  • An advantage of using patch-data memories and patch-address memories structured as registers is the relatively delay-free access.
  • the data that needs to be replaced or corrected are typically stored in a RAM or ROM.
  • access to the patch-data memory is required thus significantly reducing the data read-out speed, especially if the data needing to be replaced occurs very frequently during the program execution. Structuring the patch-data memory and patch-address memory respectively as a hard-wired logic circuit and as registers assures that the data can be read out and replaced almost without delay.
  • Data can also be replaced. For example, if a single byte needs to be changed in a table that is used simultaneously in several program sequences, this may be performed by simply changing this one byte.
  • FIG. 1 is a block diagram illustration of a program-controlled unit that includes a patch-memory module, structured as a microcontroller;
  • FIG. 2 is a block diagram illustration of the patch-memory module of FIG. 1;
  • FIG. 3 illustrates a timing diagram, which shows the time sequence for creating and retrieving error correction instructions and/or data from the patch-memory module.
  • FIG. 1 is a block diagram illustration of a program-controlled unit 1 . Only the units necessary to describe the invention are shown in the program-controlled unit 1 , which in this embodiment is structured as a microcontroller. Therefore, in this embodiment the program-control unit is preferably monolithically integrated on a single chip.
  • the program-controlled unit 1 includes a central computing unit (CPU) 2 that is coupled through an address bus 3 and a data bus 4 , to the system memory 5 (e.g., a ROM). A transfer gate 6 is switched onto the data bus 4 .
  • the programmed control unit 1 also includes a patch-memory module 7 that is connected to the address bus 3 and the data bus 4 .
  • FIG. 1 does not illustrate the control bus that is typically present in the program-controlled unit 1 , and that controls the bus and bus arbitrations.
  • Such a control bus may be implemented separately or also by an address bus in multiplex operation.
  • FIG. 2 is a block diagram of the patch-memory module 7 .
  • the module 7 preferably includes a plurality of patch-memory cells 8 (e.g., ten). For the sake of clarity, only one such patch-memory cell 8 is illustrated in FIG. 2 .
  • Each patch-memory cell 8 includes a patch-address register 9 , a patch-data register 10 , and a comparator circuit 11 situated between the registers 9 , 10 .
  • the patch-memory module 7 also includes a patch-enable register 12 that actuates the patch-memory cells 8 .
  • each patch-memory cell 8 may be activated through a patch-mode control signal (PMEN) and a patch-memory-cell enable signal (PSEL) from the patch enable register 12 .
  • PMEN patch-mode control signal
  • PSEL patch-memory-cell enable signal
  • the input of the patch-address register 9 is connected to the 24-bit address bus 3 (ADB[ 23 : 0 ]), and the patch-address register generates and outputs three one-byte addresses.
  • the patch-data register 10 is connected to both the address bus 3 and the eight-bit data bus 4 (DB[ 7 : 0 ]).
  • the comparison circuit 11 receives the address outputs of the patch-address register 9 and the address bus 3 , and provides a data-register enable signal on a line 13 that controls the patch-data register 10 .
  • the output of the patch-data register 10 may be connected to the data bus 4 either directly or through a data-bus driver circuit 14 .
  • the data-bus driver circuit 14 is preferably configured as an open-drain driver circuit.
  • the driver circuit 14 is controlled by a sequence control unit 15 .
  • the sequence control unit 15 controls the data-bus arbitration through a control signal PATOE on a line 20 , and ensures that at any moment no more than one patch-data register 10 has access rights and thus can write data on the data bus 4 .
  • one comparison circuit 11 is associated with each patch-memory cell 8 . However, it is contemplated that a single comparison circuit 11 may be provided for all the patch-memory cells 8 .
  • the comparator 11 is preferably configured and arranged to have the same address width as the address bus 3 . However, the comparator 11 may be configured to process the addresses of the address bus 3 and the patch-address register 9 byte-by-byte.
  • FIG. 3 illustrates a timing diagram associated with the sequence of retrieving error correction instructions from the patch-memory module 7 .
  • the operation of the patch-memory module 7 shall be discussed in the context of several operating modes.
  • the system is initialized following a power-up, a restart (RESET), or in a special mode (e.g., supervisor or service) of the program-controlled unit 1 .
  • the patch-memory cells 8 are actuated in a write mode (WRITE) through the patch-mode control signal PMEN.
  • WRITE write mode
  • PMEN patch-mode control signal
  • the corresponding patch-address register 9 is enabled through a patch-memory cell enable signal PSELx.
  • a single 24-bit address may then be written into the patch-address register 9 , and the error correction instruction (Patch) associated with this address may be written to and stored in the patch-data register 10 . This process may be repeated for the remaining or individual patch-memory cells.
  • the particular patch-memory cells 8 to be written to may be addressed by an address pointer (not shown).
  • the 24-bit addresses may be written into the patch-address registers 9 sequentially byte-wise (8-bit), 4-bitwise, or the like.
  • the addresses or data (error correction instructions) that are written into the patch-address register 9 and patch-data register 10 during system initialization can be loaded from an external memory via an internal memory or via an external interface.
  • the patch-memory cells 8 are actuated in the patch mode (COMPARE) through the patch mode control signal PMEN. In one state this signal commands the cell to the write/initialize mode, and it its opposite state to the compare/patch mode.
  • the desired patch-memory cell 8 is enabled through the patch-memory-cell enable signal PSELx.
  • the comparison circuit 11 then begins to compare the current addresses on the address bus 3 with the addresses stored in the enabled patch-address registers 9 . If an address on the address bus 3 agrees with the address of an enabled patch-address register 9 , the instruction assigned to this address in the ROM is replaced by the appropriate error correction instruction from the respective patch-data register 10 and the value within the patch data register 10 is switched onto the data bus 4 .
  • the sequence control unit 15 issues a wait signal RDY on a line 22 .
  • the wait signal RDY on the line 22 sets the central computing unit 2 (FIG. 1) into a wait state for the duration of at least one clock cycle CLK. Therefore, the central computing unit delays the data processing during this wait state.
  • the sequence control unit 15 provides a control signal (ROMEN) on a line 24 that deactivates the ROM data bus output drivers, and in their place the error correction instruction of the respective patch-data register 10 is switched onto the data bus 4 .
  • ROMEN control signal
  • the patch-memory module 7 is driven from patch mode to write mode by the patch-mode control signal PMEN from the patch enable register.
  • System reconfiguration then takes place in a manner similar to system initialization discussed above.
  • inventive circuit arrangement is suitable for any ROM that includes data programmed on the device, and now requires error correction data (patches).
  • the present invention is clearly applicable to units that employ non-volatile memories such as PROM and/or EPROM.
  • the invention also is not necessarily limited to the replacement of erroneous data or instructions. Rather, the inventive patch-memory module may be used to facilitate easily updating the software/firmware within the unit. Significantly, this allows updates/modifications to the executable code/data of the program-controlled unit 1 without replacing the ROMs within the unit.
  • the invention is especially useful in connection with program-controlled units designed as microcontrollers, microprocessors, signal processors, etc., which have a system ROM integrated on the chip of the program-controlled units.
  • program-controlled units designed as microcontrollers, microprocessors, signal processors, etc.
  • system ROM integrated on the chip of the program-controlled units.
  • the entire program-controlled unit need not be replaced because of an erroneous ROM instruction.
  • only the erroneous ROM instruction is replaced on the data bus by an error correction instruction stored in the patch-memory module.
  • the invention naturally can also be used for program-controlled units with a different structure, for example clock-pulse controlled sequence controls and/or state machines.

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Stored Programmes (AREA)
  • Debugging And Monitoring (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
US09/753,494 1999-12-30 2001-01-02 Circuit arrangement and method for creating and retrieving patch data from memory Expired - Fee Related US6530005B2 (en)

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DE19964003 1999-12-30
DE19964003.3 1999-12-30
DE19964003A DE19964003A1 (de) 1999-12-30 1999-12-30 Schaltungsanordnung und Verfahren zur Erzeugung und zum Auslesen von Ersatzdaten

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6779131B2 (en) * 2001-05-01 2004-08-17 Sun Microsystems, Inc. Reconfigurable multi-chip modules
US20040205318A1 (en) * 2003-04-14 2004-10-14 Arm Limited Remapping of data access requests
US20050102550A1 (en) * 2003-10-23 2005-05-12 International Business Machines Corporation Method and structure for replacing faulty operating code contained in a ROM for a processor
US20090043957A1 (en) * 2007-08-08 2009-02-12 Zerog Wireless, Inc. Method and Apparatus for Updating Data in ROM Using a CAM
US7596721B1 (en) * 2004-01-09 2009-09-29 Maxtor Corporation Methods and structure for patching embedded firmware
US20100146332A1 (en) * 2008-12-10 2010-06-10 Kabushiki Kaisha Toshiba Data correction circuit and semiconductor integrated circuit

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DE10251477B4 (de) * 2002-11-05 2006-03-02 Siemens Ag Vorrichtung und Verfahren zum selektiven Ändern von ROM-Daten für Test- und Diagnosezwecke
GB0311506D0 (en) * 2003-05-20 2003-06-25 Microbus Designs Ltd Initial boot device for embedded processors
JP4546177B2 (ja) 2003-07-28 2010-09-15 パナソニック株式会社 無線通信装置および無線通信方法
EP1686467B1 (de) * 2005-01-31 2008-03-12 STMicroelectronics S.r.l. Verfahren, System und Computerprogrammprodukt zur Korrektur von Fehlern in einem Festwertspeicher
DE102010039021B4 (de) * 2010-08-06 2023-02-23 Robert Bosch Gmbh Verfahren zur Rekonfiguration von Softwareparametern in einem Mikrocontroller sowie Mikrocontroller und Steuergerät
CN104793964B (zh) * 2014-01-16 2018-10-02 国民技术股份有限公司 java卡及其应用更新方法、应用于java卡的终端、智能卡系统
US20200004697A1 (en) * 2018-06-29 2020-01-02 Qualcomm Incorporated Patchable hardware for access control
CN112231136A (zh) * 2020-11-04 2021-01-15 炬芯科技股份有限公司 SoC芯片、获取修复信息的方法、存储介质及电子设备
US20230280909A1 (en) * 2022-03-01 2023-09-07 Nxp B.V. System and method for managing memory errors in integrated circuits

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US5796746A (en) * 1995-12-22 1998-08-18 Micron Technology, Inc. Device and method for testing integrated circuit dice in an integrated circuit module
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US6260157B1 (en) * 1999-02-16 2001-07-10 Kurt Schurecht Patching of a read only memory

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US4982360A (en) * 1983-09-22 1991-01-01 Digital Equipment Corporation Memory subsystem
US5796746A (en) * 1995-12-22 1998-08-18 Micron Technology, Inc. Device and method for testing integrated circuit dice in an integrated circuit module
US5901225A (en) 1996-12-05 1999-05-04 Advanced Micro Devices, Inc. System and method for performing software patches in embedded systems
US6037803A (en) * 1997-12-12 2000-03-14 Micron Electronics, Inc. Integrated circuit having two modes of I/O pad termination
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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6779131B2 (en) * 2001-05-01 2004-08-17 Sun Microsystems, Inc. Reconfigurable multi-chip modules
US20040205318A1 (en) * 2003-04-14 2004-10-14 Arm Limited Remapping of data access requests
GB2400701A (en) * 2003-04-14 2004-10-20 Advanced Risc Mach Ltd Remapping of data access requests
US7243206B2 (en) 2003-04-14 2007-07-10 Arm Limited Method and apparatus for using a RAM memory block to remap ROM access requests
GB2400701B (en) * 2003-04-14 2007-10-10 Advanced Risc Mach Ltd Remapping of data access requests
US20050102550A1 (en) * 2003-10-23 2005-05-12 International Business Machines Corporation Method and structure for replacing faulty operating code contained in a ROM for a processor
US7302605B2 (en) 2003-10-23 2007-11-27 International Business Machines Corporation Method and structure for replacing faulty operating code contained in a ROM for a processor
US7596721B1 (en) * 2004-01-09 2009-09-29 Maxtor Corporation Methods and structure for patching embedded firmware
US20090043957A1 (en) * 2007-08-08 2009-02-12 Zerog Wireless, Inc. Method and Apparatus for Updating Data in ROM Using a CAM
US7861030B2 (en) 2007-08-08 2010-12-28 Microchip Technology Incorporated Method and apparatus for updating data in ROM using a CAM
US20100146332A1 (en) * 2008-12-10 2010-06-10 Kabushiki Kaisha Toshiba Data correction circuit and semiconductor integrated circuit

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EP1118935A3 (de) 2004-01-28
EP1118935A2 (de) 2001-07-25
US20010013091A1 (en) 2001-08-09
DE19964003A1 (de) 2001-07-12

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