US6401193B1 - Dynamic data prefetching based on program counter and addressing mode - Google Patents

Dynamic data prefetching based on program counter and addressing mode Download PDF

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Publication number
US6401193B1
US6401193B1 US09/178,052 US17805298A US6401193B1 US 6401193 B1 US6401193 B1 US 6401193B1 US 17805298 A US17805298 A US 17805298A US 6401193 B1 US6401193 B1 US 6401193B1
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instruction
data
indicator
data prefetch
prefetch
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Muhammad Afsar
Klaus Oberlaender
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Infineon Technologies North America Corp
SMI Holding LLC
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G06F9/3832—Value prediction for operands; operand history buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions

Definitions

  • assembly language instructions are delivered to the processor from memory and then executed by the processor.
  • a typical assembly language instruction 26 includes an opcode portion 28 and an operand portion 30 .
  • the opcode for operation code, informs the processor of what operation is to be performed.
  • Opcode instructions include, for example, load instructions, add instructions, and subtract instructions.
  • a typical instruction 32 includes an opcode 38 that is referenced by a program counter (PC) 36 .
  • the program counter is an instruction location indicator that identifies the address within the memory of the desired instruction and the instruction directs the performance of functions, such as loading data, adding data, or subtracting data.
  • cache memory cannot store the total volume of information that is stored in the main memory 18 , all of the information required by the processor 10 cannot be stored in the L 0 cache 14 at the same time and cache misses will result when the processor fetches data that is not stored in the L 0 cache.
  • instructions and/or data can be prefetched from the main memory to the L 0 cache 14 or L 1 cache 16 in anticipation of a data fetch by the processor. Prefetching of instructions to the cache is made easier by the sequential nature of computer program instruction execution.
  • Branch target buffers can be used for prefetching instructions that do not exhibit sequential characteristics.
  • prefetching data In contrast to prefetching instructions, data is often accessed in more of a random nature, such that prefetching is more difficult to perform.
  • One common technique used in prefetching data is that when a cache miss occurs, the current cache line is filled from the main memory with the desired prefetch data and a next cache line is filled with a block of data from the main memory that is spatially close to the missed data.
  • the block caching approach may work well for some applications, it has disadvantages.
  • a method and apparatus for prefetching data to a low level memory of a computer system utilize an instruction location indicator related to an upcoming instruction to identify a next data prefetch indicator and then utilize the next data prefetch indicator to locate the corresponding prefetch data within the main memory of the computer system.
  • the prefetch data is located so that the prefetch data can be transferred to the low level memory, where the data can be quickly accessed by a processor before the upcoming instruction is executed.
  • the next data prefetch indicator is generated by carrying out the addressing mode function that is embedded in an instruction only when the addressing mode of the instruction is a deterministic addressing mode such as a sequential addressing mode.
  • the next data prefetch indicator is identified by the instruction location indicator by relating corresponding next data prefetch indicators to instruction location indicators in a searchable table.
  • a data prefetch prediction table is generated that enables the next data prefetch indicator to be identified based on the program counter of an instruction that is soon to be executed. Entries in the data prefetch prediction table are formed from instructions that utilize deterministic addressing modes for identifying the effective address of the source data.
  • the data prefetch prediction table entries include a program counter tag and a next data prefetch indicator.
  • the program counter tag is the program counter related to the present instruction and the program counter tag allows the data prefetch prediction table to be searched by the program counter that is related to a particular instruction.
  • the next data prefetch indicator is the effective address of the data that is likely to be required the next time the same instruction is executed.
  • the next data prefetch indicator is calculated by carrying out the addressing mode function that is associated with the instruction. Since the addressing mode function is a deterministic function, there is a high likelihood that the calculated next effective address will be the actual effective address that is fetched the next time the instruction with the same program counter value is executed.
  • the elements of a computer system in accordance with a preferred embodiment of the invention include a processor, a level zero cache, a level one cache, a main memory, and a data prefetch engine.
  • the processor is any conventional processor having a program counter that identifies the address of instructions that are to be executed.
  • the level zero cache is preferably SRAM that provides the fastest data transfer rate to the processor and that is located physically close to the processor.
  • the level one cache is preferably SRAM that provides a slower data transfer rate to the processor and that is located on a system mother-board connected to the processor by a system bus.
  • the main memory is a large capacity memory that provides a relatively slow transfer of data to the processor.
  • the main memory may include DRAM, flash memory or other suitable memory types.
  • the main memory is connected to the processor by a system bus.
  • the data prefetch engine is preferably integrated with the processor and manages the prefetching of data between the level zero cache, the level one cache, and the main memory.
  • the data prefetch engine utilizes a next data prefetch controller, a data prefetch predictor, and a refill manager to predict the effective address of the next desired data memory reference and to transfer the data corresponding to the predicted data memory reference to the lowest level cache in order to create the best chance for a cache hit upon the execution of a particular instruction.
  • the next data prefetch controller screens out instructions having non-deterministic addressing modes and uses instructions having deterministic addressing modes such as sequential addressing modes to build a data prefetch prediction table that is used to predict the next prefetch.
  • Generation of a data prefetch prediction table entry involves calculating the next effective address related to the present instruction by carrying out the addressing mode function related to the present instruction.
  • the data prefetch predictor utilizes the data prefetch prediction table formed by the next data prefetch controller to rapidly identify the next effective address for a data prefetch related to an upcoming instruction.
  • the data prefetch predictor maintains the data prefetch prediction table in a content-addressable memory that can be quickly searched by program counter tag.
  • a refill manager of the data prefetch engine is responsible for transferring prefetch data that is not found in the lowest level cache to the lowest level cache when a prefetch miss occurs at the lowest level cache.
  • the refill manager generates prefetch requests for higher level memory until the desired prefetch data is located and transferred to the lowest level cache.
  • the next data prefetch controller In operation, the next data prefetch controller generates the data prefetch prediction table utilizing executed instructions that exhibit deterministic addressing modes.
  • the data prefetch prediction table is located in the data prefetch predictor and is constantly updated by the next data prefetch controller.
  • the program counter related to the instruction is forwarded to the data prefetch predictor.
  • the program counter related to the instruction is used by the data prefetch predictor to search the program counter tag column of the data prefetch prediction table for a matching program counter tag.
  • next data prefetch indicator is extracted from the table entry and the indicator is used to search the lowest level cache in the computer system for a cache line that matches the effective address of the next data prefetch indicator. If a cache hit occurs in the lowest level cache, no further prefetching is required. On the other hand, if a cache miss occurs in the lowest level cache, then the refill manager generates a prefetch request utilizing the next data prefetch indicator that enables the higher level memories to be searched for data with the corresponding effective address. Once the data with the corresponding next effective address is located, the refill manager transfers the located data to the lowest level cache in the computer system.
  • the prefetch process related to the current instruction is complete.
  • the current instruction is finally executed by the processor, there is a higher probability that the data requested by the current instruction will be located in the lowest level cache, thereby allowing the fastest data access time possible.
  • FIG. 1 is a depiction of a processor and multilevel memory in accordance with the prior art.
  • FIG. 2 is a depiction of an assembly-language instruction in accordance with the prior art.
  • FIG. 3 is a depiction of specific parts of an assembly-language instruction in accordance with the prior art.
  • FIG. 4 is a depiction of a processor, a multilevel memory, and a data prefetch engine in accordance with the invention.
  • FIG. 5 is a depiction of a data prefetch prediction table entry in accordance with the invention.
  • FIG. 6 is a depiction of a data prefetch prediction table in accordance with the invention.
  • FIG. 7 is a flow diagram of the interaction between elements of the system of FIG. 4 in accordance with the invention.
  • FIG. 8 is a process flow diagram of a preferred method of the invention.
  • FIG. 4 is a depiction of the preferred architecture of a computer system 50 in accordance with the invention.
  • the preferred architecture includes a processor 52 , a data prefetch engine 56 , a level zero (L 0 ) cache 60 , a level one (L 1 ) cache 64 and a main memory 68 .
  • the processor is any conventional processor, including a processor that can generate one or more data memory references in a single clock cycle.
  • the processor includes a program counter that identifies the address of instructions that are to be executed, an instruction decoder that separates the operand from the opcode and converts the opcode into a series of electronic signals that execute the command represented by the opcode, an address decoder that determines the physical location of required data within the memory, an accumulator that temporarily stores values, and an arithmetic logic unit that performs the mathematical functions of the processor.
  • the preferred architecture of the computer system 50 includes a memory subsystem 54 , with a multilevel cache arrangement where the levels of cache memory are differentiated by size and latency.
  • the L 0 cache 60 (also known as the primary cache) provides the fastest data transfer rate to the processor 52 .
  • the L 0 cache is located physically close to the processor and is preferably SRAM. Although for description purposes the L 0 cache is shown as connected to the processor by a bus 72 , the L 0 cache is preferably integrated onto the processor chip and connected to the processor by on-chip high bandwidth circuitry.
  • the L 1 cache 64 (also known as the secondary cache) has a larger storage capacity than the L 0 cache, but provides a slower data transfer rate to the processor.
  • the L 1 cache is preferably on-chip SRAM, although it may be another form of memory such as SRAM that is integrated into the system RAM located on a system motherboard.
  • the L 0 cache memory and the L 1 cache memory store only operand data that is needed by the processor and opcode instructions needed by the processor are stored in a separate cache that is not depicted.
  • a split cache arrangement is described, a unified cache which combines both data and instructions can also be implemented.
  • the L 0 cache typically ranges from 1 Kb to 64 Kb and the L 1 cache typically ranges from 64 Kb to 1 Mb, although this is not critical.
  • the two level cache arrangement is described other cache arrangements are possible, including for example, multiple cache levels (1 to x) and/or cache memory that is connected to a processor in some other manner.
  • the exact cache configuration is not critical to the invention.
  • the main memory 68 is a large capacity memory that provides a relatively slow data transfer rate to the processor 52 .
  • the main memory may include DRAM, SRAM, flash memory and FRAM.
  • the memory subsystem may be further connected to input/output devices, such as magnetic memory.
  • the main memory is also connected to the processor by the bus 72 .
  • the preferred architecture of the computer system 50 includes the data prefetch engine 56 that manages the prefetching of data between the L 0 cache 60 , the L 1 cache 64 , and the main memory 68 .
  • the data prefetch engine is the focus of the invention and utilizes a next data prefetch controller 76 , a data prefetch predictor 80 , and a refill manager 84 to predict the effective address of the next desired data memory reference and to transfer the data corresponding to the predicted data memory reference to the lowest level cache in order to create the best chance for a cache hit upon the execution of a given instruction.
  • the addressing mode is identified by a 3-bit vector and the addressing mode vector of the instruction is fed through a hardwired comparator to determine if the addressing mode vector matches any pre-established deterministic addressing mode vectors that have been identified through a system setup.
  • deterministic addressing modes include sequential addressing modes such as pre and post incrementing, circular addressing, and bit reverse addressing modes.
  • a data prefetch prediction table entry 90 is depicted in FIG. 5 and includes the following vectors; a program counter tag 92 , a next data prefetch indicator 94 , the source addressing mode 96 , and a valid entry vector 98 .
  • the program counter tag is the program counter related to the present instruction. The program counter tag allows the data prefetch prediction table to be searched by the program counter that is related to a particular instruction.
  • next data prefetch indicator vector The number of bits in the next data prefetch indicator vector required to identify an effective address is a function of the memory organization of the computer system. In the preferred embodiment, the next data prefetch indicator vector is 12 bits.
  • the next unit in the data prefetch engine 56 is the refill manager 84 .
  • the refill manager is responsible for transferring prefetch data that is found in higher level memory to the lowest level cache.
  • the refill manager recognizes when a prefetch miss occurs at the lowest level cache and then generates prefetch requests for higher level memory until the target prefetch data is located and transferred to the lowest level cache.
  • the functions of the data prefetch engine are depicted as separate from the processor 52 for description purposes, in the preferred embodiment the subunits of the data prefetch engine are integrated onto the same chip as the processor.
  • a program counter is transferred from the processor 52 to the data prefetch predictor 80 .
  • the program counter is a look-ahead program counter that represents an upcoming instruction that is soon to be executed.
  • the program counter is fed into the data prefetch predictor and is used to search the program counter tag column of the data prefetch prediction table for a matching program counter tag. If the current program counter from the processor matches a program counter tag of the data prefetch prediction table, then the data prefetch prediction table supplies the next effective address that is used to search the highest priority cache, for example the L 0 cache 60 , for a matching cache line. On the other hand, if no matching table entry is found in the data prefetch prediction table, then the prefetch can be continued under another approach, such as block prefetching, or the prefetch can be discontinued.
  • the refill manager 84 When a prefetch miss occurs in the L 0 cache 60 , the refill manager 84 generates a prefetch request and forwards the prefetch request to the next lower level memory 104 , for example the L 1 cache. If the desired prefetch data exists in a cache line of the L 1 cache, then the cache line identified by the calculated effective address is transferred to the L 0 cache and the prefetch is complete. If, on the other hand, the prefetch data does not exist in a cache line of the L 1 cache, then the refill manager forwards a prefetch request to the next lower level memory, in this case the main memory. Once the prefetch data is found in the main memory, the data can be transferred to the L 0 or L 1 cache as needed.
  • the system may incur cycle penalties in spite of the prefetch effort. However, if the prefetch is able to bring the predicted data to the L 0 cache and the processor 52 does end up fetching the predicted data, then the efficiency of the processor is enhanced by the prefetching process because the data access time for data supplied to the processor has been minimized. If the prefetched data is not requested by the instruction execution, then the prefetch algorithm has been unsuccessful at predicting the data required by the current instruction. The prefetch process is rapidly repeated during the operation of the processor.
  • a scheme can also be implemented where the prefetch could be canceled if it is recognized that the entry in the prediction table doesn't match the real address of the instruction with the same program counter tag, thereby lowering the penalty for misprediction. Further, the reason for the misprediction can be determined and the table entry can be removed before it creates another misprediction.
  • a calculated next data prefetch indicator in the form of an effective address, is extracted from the matching data prefetch prediction table entry in order to search the computer memory subsystem for the desired data.
  • the computer memory subsystem is searched for data identified by the extracted next data prefetch indicator.
  • the desired data is transferred to the lowest level cache, if the data is not already present in the lowest level cache.
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