US6316837B1 - Area array type semiconductor package and fabrication method - Google Patents

Area array type semiconductor package and fabrication method Download PDF

Info

Publication number
US6316837B1
US6316837B1 US09/200,937 US20093798A US6316837B1 US 6316837 B1 US6316837 B1 US 6316837B1 US 20093798 A US20093798 A US 20093798A US 6316837 B1 US6316837 B1 US 6316837B1
Authority
US
United States
Prior art keywords
chip
lead frame
package
die paddle
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US09/200,937
Inventor
Chi-Jung Song
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Assigned to LG SEMICON CO., LTD. reassignment LG SEMICON CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SONG, CHI-JUNG
Assigned to HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. reassignment HYUNDAI ELECTRONICS INDUSTRIES CO., LTD. MERGER (SEE DOCUMENT FOR DETAILS). Assignors: LG SEMICON CO., LTD.
Priority to US09/970,876 priority Critical patent/US7122401B2/en
Application granted granted Critical
Publication of US6316837B1 publication Critical patent/US6316837B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07352—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in structures or sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to a chip package, and more particularly, to a chip package having a lead frame serving as a heat sink.
  • the invention also relates to a method of forming the chip package.
  • a ball grid array (BGA) semiconductor package is widely used since the package is capable of having a large number of pins in a predetermined area. Also, the external terminals of the device are short, which helps to prevent them from being bent. Such a semiconductor package may be quickly mounted on a mother board through a reflow process, thereby reducing a manufacturing time.
  • BGA ball grid array
  • a background art BGA semiconductor package includes a printed circuit board (PCB) 1 having a plurality of metal patterns (not illustrated) formed therethrough.
  • a semiconductor chip 2 having a plurality of bonding pads (not illustrated) is adhered on the PCB 1 by an adhesive 1 a .
  • Metal wires 3 electrically connect each bonding pad with a corresponding metal pattern in the PCB, and a molding epoxy 4 molds a predetermined area on the PCB 1 including the semiconductor chip 2 and the metal wire 3 .
  • a plurality of solder balls 5 which serve as external terminals, are adhered on the lower surface of the PCB 1 .
  • the metal patterns provide an electric path through the PCB to electrically connect the wires 3 on the upper side to the solder balls 5 on the lower side of the PCB 1 .
  • FIG. 2 is a flow chart illustrating steps of a fabrication method for a background art BGA semiconductor package. As shown therein, the process includes: a sawing process for dividing a plurality of semiconductor devices which are formed in a wafer into individual semiconductor chips. Next, a die bonding process is performed to attach individual semiconductor chips on a PCB. A wire bonding process is performed for connecting a plurality of bonding pads of each semiconductor chip to a plurality of metal patterns of the PCB with a plurality of wires. Next, a molding process is performed to mold a predetermined area formed on the PCB, including the semiconductor chip and the wires with a molding epoxy. Finally, a ball bonding process is performed to bond solder balls on a lower surface of the PCB to serve as external output terminals.
  • a sawing process for dividing a plurality of semiconductor devices which are formed in a wafer into individual semiconductor chips.
  • a die bonding process is performed to attach individual semiconductor chips on a PCB.
  • a wire bonding process is performed for
  • solder balls of the above-described BGA semiconductor package are located opposite to an active surface of the semiconductor chip (i.e., the upper surface of the semiconductor chip having bond pads), there is a limitation on the minimum size of the semiconductor package due to the height necessary to allow the wires to bend from the top of the chip down to the PCB.
  • heat generated in the semiconductor chip is not effectively radiated outside the package. Accordingly, such a package is not suitable for a high-powered semiconductor device.
  • a further object of the present invention is to provide a packaging for a high-powered semiconductor device which radiates high temperature heat.
  • a fabrication method for an area array type semiconductor package embodying the invention includes the steps of forming solder bumps on bonding pads of a semiconductor chip, bonding said semiconductor chip to a lead frame; packaging a predetermined area of the lead frame and the semiconductor chip with a molding resin; and trimming and forming said lead frame.
  • the lead frame may include a plurality of die paddles which are attached to a corresponding plurality of semiconductor chips by a thermal conductive adhesive.
  • a plurality of leads are attached to each of the die paddles at a certain interval and serve to radiate heat to an exterior of the package.
  • a chip is attached to a lead frame having a plurality of leads.
  • a plurality of conductive media are formed on bond pads of the chip.
  • a molding resin packages portions of the chip and the lead frame.
  • FIG. 1 is a vertical cross-sectional view illustrating a background art ball grid array semiconductor package
  • FIG. 2 is a flow chart illustrating a background art fabrication method for the ball grid array semiconductor package shown in FIG. 1;
  • FIG. 3 is a plan view illustrating a lead frame of an area array type semiconductor package according to the present invention.
  • FIG. 4 is a vertical cross-sectional view of an area array type semiconductor package according to the present invention.
  • FIGS. 5A to 5 E are plan and cross-sectional views illustrating the results of steps of a fabrication method for the area array type semiconductor package according to the present invention.
  • FIG. 6 is a cross-sectional view illustrating an area array type semiconductor package according to the present invention mounted on a printed circuit board;
  • FIG. 7 is a cross-sectional view illustrating an alternate embodiment of an area array type semiconductor package according to the present invention mounted on the printed circuit board.
  • FIG. 3 is a plan view illustrating a lead frame of an area array type semiconductor package according to the present invention.
  • the lead frame 10 includes a plurality of square shaped die paddles 11 , to which semiconductor chips are adhered.
  • a plurality of leads 12 are attached to and extend away from each die paddle 11 at a certain interval.
  • a lead supporting member 13 supports the plurality of leads 12 .
  • the lead frame 10 may be made of copper, a copper alloy, a tungsten alloy or any other suitable material.
  • Each of the die paddles 11 may also have a hole, depression or dimple for receiving a chip.
  • FIG. 4 is a cross-sectional view of an area array type semiconductor package according to the present invention which utilizes the lead frame shown in FIG. 3 .
  • the package includes a semiconductor chip 20 , having a plurality of bonding pads (not illustrated) thereon.
  • the chip 20 is attached to the paddle 11 via a thermal conductive adhesive 30 .
  • a plurality of conductive media such as solder bumps or solder balls 40 , which serve as external output terminals, are formed on respective bonding pads of the semiconductor chip 20 .
  • a molding resin 50 covers portions of the semiconductor chip 20 and lead frame 11 .
  • the lead frame 10 operates as a heat sink which radiates heat generated by the semiconductor chip 20 .
  • a thermal conductive epoxy is used as the adhesive 30 .
  • FIGS. 5A to 5 E show the results of steps of a fabrication method for an area array type semiconductor package according to the present invention.
  • a semiconductor chip 20 is first adhered to a die paddle 11 of the lead frame 10 using an adhesive 30 .
  • a plurality of conductive media 40 are then formed on bond pads of the semiconductor chip 20 .
  • the conductive media 40 could be formed on the chip 20 before the chip 20 is bonded to the die paddle 11 .
  • a predetermined area formed on the lead frame 10 including the semiconductor chip 20 , is packaged with a molding epoxy 50 .
  • the conductive media 40 formed on the bonding pads of the above semiconductor chip 20 are externally exposed.
  • Each lead 12 of the lead frame is divided into two parts, an outer lead 12 a which is externally exposed and an inner lead 12 b which is at least partially packaged by the molding epoxy 50 .
  • the exposed outer lead 12 a is then trimmed and formed, thus completing an area array type semiconductor package according to the present invention.
  • FIG. 6 illustrates how an area array type semiconductor package according to the present invention is mounted on a printed circuit board (PCB) 60 using the conductive media 40 , preferably, solder balls.
  • a reflow process can be used to attach the conductive media 40 to conductive pads on the PCB 60 .
  • the space S between the chip 20 and the PCB 60 may be filled with a molding compound 70 , or any other suitable material, as is well known to those skilled in the art. Also, in the embodiment shown in FIG. 7, a plurality of cooling fins 10 extend away from the top surface of the lead frame 10 .
  • an area array type semiconductor package uses a lead frame, to which the semiconductor chip is bonded, as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates heat at a high temperature.
  • the area array type semiconductor package according to the present invention includes conductive media such as solder bumps or solder balls directly attached to the bond pads of a chip.
  • the conductive media act as external output terminals. This configuration allows the dimensions of the semiconductor package to be minimized.
  • the bonding pad arrangement can easily be planned, and electrical characteristics of the semiconductor package can be improved.
  • the space between the semiconductor chip and the PCB can be underfilled with a molding compound or resin, a reliability of the solder joint can be improved.

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

An area array type semiconductor package includes a plurality of conductive media, such as solder bumps or solder balls, attached to respective bond pads of a chip. The conductive media act as external output terminals. The chip is attached to a lead frame by a thermal conductive adhesive, and a predetermined area of the lead frame and the semiconductor chip are packaged with a molding resin. Leads of the lead frame are then trimmed and formed so that the lead frame, to which the semiconductor chip is adhered, acts as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates a high temperature heat. Also, because conductive media such as solder bumps or solder balls can be used to directly connect bond pads of the chip to conductive regions of a circuit board, a size of the semiconductor package can be minimized, the arrangement of the bonding pads on the chip can be easily planned, and electrical characteristics of the semiconductor package can be improved.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a chip package, and more particularly, to a chip package having a lead frame serving as a heat sink. The invention also relates to a method of forming the chip package.
2. Background of the Related Art
A ball grid array (BGA) semiconductor package is widely used since the package is capable of having a large number of pins in a predetermined area. Also, the external terminals of the device are short, which helps to prevent them from being bent. Such a semiconductor package may be quickly mounted on a mother board through a reflow process, thereby reducing a manufacturing time.
As shown in FIG. 1, a background art BGA semiconductor package includes a printed circuit board (PCB) 1 having a plurality of metal patterns (not illustrated) formed therethrough. A semiconductor chip 2 having a plurality of bonding pads (not illustrated) is adhered on the PCB 1 by an adhesive 1 a. Metal wires 3 electrically connect each bonding pad with a corresponding metal pattern in the PCB, and a molding epoxy 4 molds a predetermined area on the PCB 1 including the semiconductor chip 2 and the metal wire 3. A plurality of solder balls 5, which serve as external terminals, are adhered on the lower surface of the PCB 1. The metal patterns provide an electric path through the PCB to electrically connect the wires 3 on the upper side to the solder balls 5 on the lower side of the PCB 1.
FIG. 2 is a flow chart illustrating steps of a fabrication method for a background art BGA semiconductor package. As shown therein, the process includes: a sawing process for dividing a plurality of semiconductor devices which are formed in a wafer into individual semiconductor chips. Next, a die bonding process is performed to attach individual semiconductor chips on a PCB. A wire bonding process is performed for connecting a plurality of bonding pads of each semiconductor chip to a plurality of metal patterns of the PCB with a plurality of wires. Next, a molding process is performed to mold a predetermined area formed on the PCB, including the semiconductor chip and the wires with a molding epoxy. Finally, a ball bonding process is performed to bond solder balls on a lower surface of the PCB to serve as external output terminals.
Since the solder balls of the above-described BGA semiconductor package are located opposite to an active surface of the semiconductor chip (i.e., the upper surface of the semiconductor chip having bond pads), there is a limitation on the minimum size of the semiconductor package due to the height necessary to allow the wires to bend from the top of the chip down to the PCB.
Also, heat generated in the semiconductor chip is not effectively radiated outside the package. Accordingly, such a package is not suitable for a high-powered semiconductor device.
SUMMARY OF THE INVENTION
It is an object of the present invention to solve the problems and disadvantages of the related art.
It is another object of the present invention to more efficiently radiate heat.
It is a further object of the invention to enable a lead frame to serve as a heat sink.
A further object of the present invention is to provide a packaging for a high-powered semiconductor device which radiates high temperature heat.
To achieve the above objects, a fabrication method for an area array type semiconductor package embodying the invention, includes the steps of forming solder bumps on bonding pads of a semiconductor chip, bonding said semiconductor chip to a lead frame; packaging a predetermined area of the lead frame and the semiconductor chip with a molding resin; and trimming and forming said lead frame.
The lead frame may include a plurality of die paddles which are attached to a corresponding plurality of semiconductor chips by a thermal conductive adhesive. A plurality of leads are attached to each of the die paddles at a certain interval and serve to radiate heat to an exterior of the package.
In a chip package embodying the invention, a chip is attached to a lead frame having a plurality of leads. A plurality of conductive media are formed on bond pads of the chip. A molding resin packages portions of the chip and the lead frame.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be described in detail with reference to the following drawings in which like reference numerals refer to like elements, and wherein:
FIG. 1 is a vertical cross-sectional view illustrating a background art ball grid array semiconductor package;
FIG. 2 is a flow chart illustrating a background art fabrication method for the ball grid array semiconductor package shown in FIG. 1;
FIG. 3 is a plan view illustrating a lead frame of an area array type semiconductor package according to the present invention;
FIG. 4 is a vertical cross-sectional view of an area array type semiconductor package according to the present invention;
FIGS. 5A to 5E are plan and cross-sectional views illustrating the results of steps of a fabrication method for the area array type semiconductor package according to the present invention;
FIG. 6 is a cross-sectional view illustrating an area array type semiconductor package according to the present invention mounted on a printed circuit board; and
FIG. 7 is a cross-sectional view illustrating an alternate embodiment of an area array type semiconductor package according to the present invention mounted on the printed circuit board.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
FIG. 3 is a plan view illustrating a lead frame of an area array type semiconductor package according to the present invention. As shown therein, the lead frame 10 includes a plurality of square shaped die paddles 11, to which semiconductor chips are adhered. A plurality of leads 12 are attached to and extend away from each die paddle 11 at a certain interval. A lead supporting member 13 supports the plurality of leads 12. As can be appreciated, the lead frame 10 may be made of copper, a copper alloy, a tungsten alloy or any other suitable material. Each of the die paddles 11 may also have a hole, depression or dimple for receiving a chip.
FIG. 4 is a cross-sectional view of an area array type semiconductor package according to the present invention which utilizes the lead frame shown in FIG. 3. As shown therein, the package includes a semiconductor chip 20, having a plurality of bonding pads (not illustrated) thereon. The chip 20 is attached to the paddle 11 via a thermal conductive adhesive 30. A plurality of conductive media such as solder bumps or solder balls 40, which serve as external output terminals, are formed on respective bonding pads of the semiconductor chip 20. A molding resin 50 covers portions of the semiconductor chip 20 and lead frame 11. In the above-described semiconductor package, the lead frame 10 operates as a heat sink which radiates heat generated by the semiconductor chip 20. Preferably, a thermal conductive epoxy is used as the adhesive 30.
FIGS. 5A to 5E show the results of steps of a fabrication method for an area array type semiconductor package according to the present invention. As shown in FIGS. 5A and 5B, a semiconductor chip 20 is first adhered to a die paddle 11 of the lead frame 10 using an adhesive 30. A plurality of conductive media 40 are then formed on bond pads of the semiconductor chip 20. Of course, the conductive media 40 could be formed on the chip 20 before the chip 20 is bonded to the die paddle 11.
Next, as shown in FIGS. 5C and 5D, a predetermined area formed on the lead frame 10, including the semiconductor chip 20, is packaged with a molding epoxy 50. The conductive media 40 formed on the bonding pads of the above semiconductor chip 20 are externally exposed. Each lead 12 of the lead frame is divided into two parts, an outer lead 12 a which is externally exposed and an inner lead 12 b which is at least partially packaged by the molding epoxy 50. As shown in FIG. 5E, the exposed outer lead 12 a is then trimmed and formed, thus completing an area array type semiconductor package according to the present invention.
FIG. 6 illustrates how an area array type semiconductor package according to the present invention is mounted on a printed circuit board (PCB) 60 using the conductive media 40, preferably, solder balls. A reflow process can be used to attach the conductive media 40 to conductive pads on the PCB 60.
In an alternate embodiment, as shown in FIG. 7, the space S between the chip 20 and the PCB 60 may be filled with a molding compound 70, or any other suitable material, as is well known to those skilled in the art. Also, in the embodiment shown in FIG. 7, a plurality of cooling fins 10 extend away from the top surface of the lead frame 10.
As described above, an area array type semiconductor package according to the present invention uses a lead frame, to which the semiconductor chip is bonded, as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates heat at a high temperature.
Also, unlike the background art semiconductor package which communicates with bond pads of a chip through metal wires and conductive regions passing through a PCB, the area array type semiconductor package according to the present invention includes conductive media such as solder bumps or solder balls directly attached to the bond pads of a chip. The conductive media act as external output terminals. This configuration allows the dimensions of the semiconductor package to be minimized. Also, the bonding pad arrangement can easily be planned, and electrical characteristics of the semiconductor package can be improved. In addition, because the space between the semiconductor chip and the PCB can be underfilled with a molding compound or resin, a reliability of the solder joint can be improved.
The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatus. Many alternatives, modifications, and variations will be apparent to those skilled in the art. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. For example, although a wire and a solder ball may not be structural equivalents in that a wire can be routed in various ways over a substantial distance to electrically connect two elements, whereas a solder bump must be sandwiched between the elements being connected, in the environment of making electrical connections, a wire and a solder bump may be equivalent structures.

Claims (21)

What is claimed is:
1. A chip package, comprising:
a lead frame including a plurality of leads and a die paddle;
an integrated chip having a plurality of bonding pads, wherein the chip is attached to the die paddle of the lead frame, and wherein the die paddle and adjoining portions of the leads are substantially co-planar;
a plurality of conductive media formed on the bonding pads of the chip; and
a molding resin that packages a predetermined area on the lead frame and the chip.
2. The package of claim 1, wherein certain portions of the leads of the lead frame are bent in an upward or downward direction.
3. The package of claim 1, wherein the chip is attached to a die paddle of the lead frame, and wherein an area of the die paddle is larger than an attachment surface area of the chip.
4. The package of claim 3, wherein a portion of said die paddle is bent or recessed.
5. The package of claim 1, wherein the chip is attached to a die paddle of the lead frame, and wherein an area of the die paddle is approximately the same size as an attachment area of the chip.
6. The package of claim 1, wherein a thermal-conducting adhesive attaches the chip to the lead frame.
7. The package of claim 1, wherein portions of the plurality of conductive media are exposed outside the resin.
8. The package of claim 1, wherein the bonding pads are formed on a first side of the chip, and the lead frame is attached to a second side of the chip.
9. A chip package, comprising:
a lead frame comprising a plurality of leads and a die paddle;
an integrated chip comprising a plurality of bonding pads, wherein the chip is attached to the die paddle of the lead frame, and wherein an area of the die paddle is approximately the same size as an attachment area of the chip;
a plurality of conductive media formed on the bonding pads of the chip; and
a molding resin that packages a predetermined area on the lead frame and the chip wherein a portion of the die paddle is exposed outside of the molding resin.
10. A chip package, comprising:
a lead frame comprising a plurality of leads and a die paddle;
an integrated chip comprising a plurality of bonding pads, wherein the chip is attached to the die paddle of the lead frame, and wherein a portion of said die paddle is bent or recessed;
a plurality of conductive media formed on the bonding pads of the chip; and
a molding resin that packages a predetermined area on the lead frame and the chip.
11. A chip package, comprising:
a lead frame having a plurality of leads and a die paddle;
an integrated chip having a plurality of bonding pads formed on a first surface of the chip, wherein a second surface of the chip is attached to the die paddle of the lead frame, the first and second surfaces being opposing surfaces;
a plurality of solder bumps or balls formed on the bonding pads of the first surface of the chip; and
a molding resin that packages a predetermined area on the lead frame and the chip.
12. The package of claim 11, wherein a portion of said die paddle is bent or recessed.
13. The package of claim 11, wherein an area of the die paddle is approximately the same size as an attachment area of the chip.
14. The package of claim 11, wherein the die paddle and adjoining portions of the leads are substantially co-planar.
15. The package of claim 11, wherein the die paddle has a hole, depression or dimple for receiving the chip.
16. The package of claim 11, wherein the lead frame further comprises a lead supporting member for supporting the plurality of leads.
17. The package of claim 11, wherein the lead frame comprises copper, a copper alloy or a tungsten alloy.
18. The package of claim 11, wherein the solder bumps or balls are substantially spherical.
19. The package of claim 11, wherein the solder bumps or balls are exposed outside the resin.
20. The package of claim 11, wherein an area of the die paddle is larger than an attachment surface area of the chip.
21. The package of claim 11, wherein the first surface of the integrated chip is exposed.
US09/200,937 1997-12-04 1998-11-30 Area array type semiconductor package and fabrication method Expired - Fee Related US6316837B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/970,876 US7122401B2 (en) 1997-12-04 2001-10-05 Area array type semiconductor package fabrication method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019970065912A KR100246366B1 (en) 1997-12-04 1997-12-04 Area array type semiconductor package and fabrication method of the same
KR97-65912 1997-12-04

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/970,876 Division US7122401B2 (en) 1997-12-04 2001-10-05 Area array type semiconductor package fabrication method

Publications (1)

Publication Number Publication Date
US6316837B1 true US6316837B1 (en) 2001-11-13

Family

ID=19526461

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/200,937 Expired - Fee Related US6316837B1 (en) 1997-12-04 1998-11-30 Area array type semiconductor package and fabrication method
US09/970,876 Expired - Fee Related US7122401B2 (en) 1997-12-04 2001-10-05 Area array type semiconductor package fabrication method

Family Applications After (1)

Application Number Title Priority Date Filing Date
US09/970,876 Expired - Fee Related US7122401B2 (en) 1997-12-04 2001-10-05 Area array type semiconductor package fabrication method

Country Status (3)

Country Link
US (2) US6316837B1 (en)
JP (1) JPH11312764A (en)
KR (1) KR100246366B1 (en)

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030026556A1 (en) * 2001-08-03 2003-02-06 National Semiconductor Corporation Optical sub-assembly for optoelectronic modules
US20030057535A1 (en) * 2001-09-24 2003-03-27 National Semiconductor Corporation Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package
US6551859B1 (en) 2001-02-22 2003-04-22 National Semiconductor Corporation Chip scale and land grid array semiconductor packages
US20030165303A1 (en) * 2000-05-09 2003-09-04 National Semiconductor Corporation, A Delaware Corporation Ceramic optical sub-assembly for opto-electronic module utilizing LTCC ( low-temperature co-fired ceramic ) technology
US6624507B1 (en) 2000-05-09 2003-09-23 National Semiconductor Corporation Miniature semiconductor package for opto-electronic devices
US6642613B1 (en) 2000-05-09 2003-11-04 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US6683368B1 (en) * 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
US6689640B1 (en) 2000-10-26 2004-02-10 National Semiconductor Corporation Chip scale pin array
US6707140B1 (en) * 2000-05-09 2004-03-16 National Semiconductor Corporation Arrayable, scaleable, and stackable molded package configuration
US6765275B1 (en) 2000-05-09 2004-07-20 National Semiconductor Corporation Two-layer electrical substrate for optical devices
US20050013560A1 (en) * 2003-07-15 2005-01-20 National Semiconductor Corporation Opto-electronic module form factor having adjustable optical plane height
US20050013581A1 (en) * 2003-07-15 2005-01-20 National Semiconductor Corporation Multi-purpose optical light pipe
US7023705B2 (en) 2001-08-03 2006-04-04 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US20060140534A1 (en) * 2001-08-03 2006-06-29 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US7095096B1 (en) 2004-08-16 2006-08-22 National Semiconductor Corporation Microarray lead frame
US20070035021A1 (en) * 2005-08-10 2007-02-15 Daigo Suzuki Printed circuit board and electronic apparatus including printed circuit board
US7846775B1 (en) 2005-05-23 2010-12-07 National Semiconductor Corporation Universal lead frame for micro-array packages
US20140225222A1 (en) * 2013-02-11 2014-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US10702099B2 (en) 2018-06-27 2020-07-07 Ohc Ip Holdings, Llc Grill and side cart attachment systems and methods
US10772466B2 (en) 2018-06-27 2020-09-15 Ohc Ip Holdings, Llc Grill assembly with foldable cart
US10966569B2 (en) 2018-06-27 2021-04-06 Ohc Ip Holdings, Llc Grill system with decorative panels
US11033147B2 (en) 2018-06-27 2021-06-15 Ohc Ip Holdings, Llc Gas tank guard in grill cart
US11045049B2 (en) 2018-06-27 2021-06-29 Ohc Ip Holdings, Llc Securing of panels to grill system
USD924002S1 (en) 2019-06-24 2021-07-06 Ohc Ip Holdings, Llc Grill cart
USD923996S1 (en) 2019-06-24 2021-07-06 Ohc Ip Holdings, Llc Grill
USD926519S1 (en) 2019-06-24 2021-08-03 Ohc Ip Holdings, Llc Grill side assembly
USD928544S1 (en) 2019-06-24 2021-08-24 Ohc Ip Holdings, Llc Grill assembly
US11096521B2 (en) 2018-06-27 2021-08-24 Ohc Ip Holdings, Llc Side cart locking mechanism
US11352038B2 (en) 2017-03-27 2022-06-07 Ohc Ip Holdings, Llc Collapsible cart

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001217340A (en) 2000-02-01 2001-08-10 Nec Corp Semiconductor device and manufacturing method thereof
US7323361B2 (en) * 2002-03-29 2008-01-29 Fairchild Semiconductor Corporation Packaging system for semiconductor devices
US7514769B1 (en) * 2005-08-13 2009-04-07 National Semiconductor Corporation Micro surface mount die package and method
JP2008153305A (en) * 2006-12-14 2008-07-03 Nec Electronics Corp Semiconductor device
US8435837B2 (en) * 2009-12-15 2013-05-07 Silicon Storage Technology, Inc. Panel based lead frame packaging method and device
US8076181B1 (en) * 2010-10-22 2011-12-13 Linear Technology Corporation Lead plating technique for singulated IC packages
US8872321B2 (en) * 2012-02-24 2014-10-28 Broadcom Corporation Semiconductor packages with integrated heat spreaders
WO2014013848A1 (en) * 2012-07-19 2014-01-23 日産自動車株式会社 Semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241133A (en) 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
US5355283A (en) 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5834831A (en) * 1994-08-16 1998-11-10 Fujitsu Limited Semiconductor device with improved heat dissipation efficiency
US5965936A (en) * 1997-12-31 1999-10-12 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182631A (en) * 1988-04-15 1993-01-26 Nippon Telegraph And Telephone Corporation Film carrier for RF IC
US5253010A (en) * 1988-05-13 1993-10-12 Minolta Camera Kabushiki Kaisha Printed circuit board
US5053852A (en) * 1990-07-05 1991-10-01 At&T Bell Laboratories Molded hybrid IC package and lead frame therefore
EP0468379B1 (en) * 1990-07-21 1999-11-17 Mitsui Chemicals, Inc. Semiconductor device having a package
DE69117891T2 (en) * 1990-11-20 1996-07-25 Sumitomo Electric Industries Method of assembling semiconductor elements
US5157480A (en) * 1991-02-06 1992-10-20 Motorola, Inc. Semiconductor device having dual electrical contact sites
US5197183A (en) * 1991-11-05 1993-03-30 Lsi Logic Corporation Modified lead frame for reducing wire wash in transfer molding of IC packages
US5387554A (en) * 1992-09-10 1995-02-07 Vlsi Technology, Inc. Apparatus and method for thermally coupling a heat sink to a lead frame
JP2531382B2 (en) * 1994-05-26 1996-09-04 日本電気株式会社 Ball grid array semiconductor device and manufacturing method thereof
US5666003A (en) * 1994-10-24 1997-09-09 Rohm Co. Ltd. Packaged semiconductor device incorporating heat sink plate
US5677566A (en) * 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
US5963796A (en) * 1996-07-29 1999-10-05 Lg Semicon Co., Ltd. Fabrication method for semiconductor package substrate and semiconductor package
KR0157899B1 (en) * 1995-09-22 1998-12-01 문정환 Coupling structure for bonding semiconductor device of subsrate
US5790378A (en) * 1995-09-22 1998-08-04 National Semiconductor Corporation High density integrated circuit package including interposer
JP3429921B2 (en) * 1995-10-26 2003-07-28 三菱電機株式会社 Semiconductor device
KR0179802B1 (en) * 1995-12-29 1999-03-20 문정환 Semiconductor package
JP2734443B2 (en) * 1996-03-19 1998-03-30 日本電気株式会社 Resin-sealed semiconductor device
JPH09260568A (en) * 1996-03-27 1997-10-03 Mitsubishi Electric Corp Semiconductor device and manufacturing method thereof
KR980006174A (en) * 1996-06-18 1998-03-30 문정환 Rip Lead Package
KR100239695B1 (en) * 1996-09-11 2000-01-15 김영환 Chip size semiconductor package and its manufacturing method
US5817540A (en) * 1996-09-20 1998-10-06 Micron Technology, Inc. Method of fabricating flip-chip on leads devices and resulting assemblies
KR100246333B1 (en) * 1997-03-14 2000-03-15 김영환 Ball grid array package and method for manufacturing thereof
US5879965A (en) * 1997-06-19 1999-03-09 Micron Technology, Inc. Plastic lead frames for semiconductor devices, packages including same, and methods of fabrication
US5869883A (en) * 1997-09-26 1999-02-09 Stanley Wang, President Pantronix Corp. Packaging of semiconductor circuit in pre-molded plastic package
US6476481B2 (en) * 1998-05-05 2002-11-05 International Rectifier Corporation High current capacity semiconductor device package and lead frame with large area connection posts and modified outline
US6448110B1 (en) * 1999-08-25 2002-09-10 Vanguard International Semiconductor Corporation Method for fabricating a dual-chip package and package formed
US6374675B1 (en) * 2000-03-20 2002-04-23 Advanced Micro Devices, Inc, Acoustic microscopy die crack inspection for plastic encapsulated integrated circuits
US6525413B1 (en) * 2000-07-12 2003-02-25 Micron Technology, Inc. Die to die connection method and assemblies and packages including dice so connected
US6566164B1 (en) * 2000-12-07 2003-05-20 Amkor Technology, Inc. Exposed copper strap in a semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5241133A (en) 1990-12-21 1993-08-31 Motorola, Inc. Leadless pad array chip carrier
US5355283A (en) 1993-04-14 1994-10-11 Amkor Electronics, Inc. Ball grid array with via interconnection
US5834831A (en) * 1994-08-16 1998-11-10 Fujitsu Limited Semiconductor device with improved heat dissipation efficiency
US5965936A (en) * 1997-12-31 1999-10-12 Micron Technology, Inc. Multi-layer lead frame for a semiconductor device

Cited By (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7247942B2 (en) 2000-05-09 2007-07-24 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US7199440B2 (en) 2000-05-09 2007-04-03 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US6642613B1 (en) 2000-05-09 2003-11-04 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US20040048417A1 (en) * 2000-05-09 2004-03-11 National Semiconductor Corporation, A Delaware Corp. Techniques for joining an opto-electronic module to a semiconductor package
US6707140B1 (en) * 2000-05-09 2004-03-16 National Semiconductor Corporation Arrayable, scaleable, and stackable molded package configuration
US7086786B2 (en) 2000-05-09 2006-08-08 National Semiconductor Corporation Ceramic optical sub-assembly for opto-electronic module utilizing LTCC (low-temperature co-fired ceramic) technology
US20050117835A1 (en) * 2000-05-09 2005-06-02 National Semiconductor Corporation, A Delaware Corp. Techniques for joining an opto-electronic module to a semiconductor package
US6765275B1 (en) 2000-05-09 2004-07-20 National Semiconductor Corporation Two-layer electrical substrate for optical devices
US6767140B2 (en) 2000-05-09 2004-07-27 National Semiconductor Corporation Ceramic optical sub-assembly for opto-electronic module utilizing LTCC (low-temperature co-fired ceramic) technology
US20050100294A1 (en) * 2000-05-09 2005-05-12 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US6624507B1 (en) 2000-05-09 2003-09-23 National Semiconductor Corporation Miniature semiconductor package for opto-electronic devices
US6838317B2 (en) 2000-05-09 2005-01-04 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US20040213525A1 (en) * 2000-05-09 2004-10-28 National Semiconductor Corporation Ceramic optical sub-assembly for opto-electronic module utilizing LTCC (low-temperature co-fired ceramic) technology
US6858468B2 (en) 2000-05-09 2005-02-22 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US7432575B2 (en) 2000-05-09 2008-10-07 National Semiconductor Corporation Two-layer electrical substrate for optical devices
US20030165303A1 (en) * 2000-05-09 2003-09-04 National Semiconductor Corporation, A Delaware Corporation Ceramic optical sub-assembly for opto-electronic module utilizing LTCC ( low-temperature co-fired ceramic ) technology
US20040216918A1 (en) * 2000-05-09 2004-11-04 National Semiconductor Corporation, A Delaware Corp. Two-layer electrical substrate for optical devices
US6740961B1 (en) 2000-06-09 2004-05-25 National Semiconductor Corporation Lead frame design for chip scale package
US6683368B1 (en) * 2000-06-09 2004-01-27 National Semiconductor Corporation Lead frame design for chip scale package
US6975038B1 (en) 2000-10-26 2005-12-13 National Semiconductor Corporation Chip scale pin array
US6689640B1 (en) 2000-10-26 2004-02-10 National Semiconductor Corporation Chip scale pin array
US6551859B1 (en) 2001-02-22 2003-04-22 National Semiconductor Corporation Chip scale and land grid array semiconductor packages
US7086788B2 (en) 2001-08-03 2006-08-08 National Semiconductor Corporation Optical sub-assembly for opto-electronic modules
US20030026556A1 (en) * 2001-08-03 2003-02-06 National Semiconductor Corporation Optical sub-assembly for optoelectronic modules
US7023705B2 (en) 2001-08-03 2006-04-04 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US20060140534A1 (en) * 2001-08-03 2006-06-29 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US6916121B2 (en) 2001-08-03 2005-07-12 National Semiconductor Corporation Optical sub-assembly for optoelectronic modules
US7269027B2 (en) 2001-08-03 2007-09-11 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US6973225B2 (en) 2001-09-24 2005-12-06 National Semiconductor Corporation Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package
US20030057535A1 (en) * 2001-09-24 2003-03-27 National Semiconductor Corporation Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package
US20050013560A1 (en) * 2003-07-15 2005-01-20 National Semiconductor Corporation Opto-electronic module form factor having adjustable optical plane height
US7156562B2 (en) 2003-07-15 2007-01-02 National Semiconductor Corporation Opto-electronic module form factor having adjustable optical plane height
US20050013581A1 (en) * 2003-07-15 2005-01-20 National Semiconductor Corporation Multi-purpose optical light pipe
US6985668B2 (en) 2003-07-15 2006-01-10 National Semiconductor Corporation Multi-purpose optical light pipe
US7095096B1 (en) 2004-08-16 2006-08-22 National Semiconductor Corporation Microarray lead frame
US7846775B1 (en) 2005-05-23 2010-12-07 National Semiconductor Corporation Universal lead frame for micro-array packages
US20070035021A1 (en) * 2005-08-10 2007-02-15 Daigo Suzuki Printed circuit board and electronic apparatus including printed circuit board
CN100444374C (en) * 2005-08-10 2008-12-17 株式会社东芝 Printed circuit boards and electronic equipment including printed circuit boards
US9263511B2 (en) * 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US20140225222A1 (en) * 2013-02-11 2014-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US10153205B2 (en) 2013-02-11 2018-12-11 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US11667314B2 (en) 2017-03-27 2023-06-06 Ohc Ip Holdings, Llc Collapsible cart
US11352038B2 (en) 2017-03-27 2022-06-07 Ohc Ip Holdings, Llc Collapsible cart
US10966569B2 (en) 2018-06-27 2021-04-06 Ohc Ip Holdings, Llc Grill system with decorative panels
US11464363B2 (en) 2018-06-27 2022-10-11 Ohc Ip Holdings, Llc Grill and side cart attachment systems and methods
US11045049B2 (en) 2018-06-27 2021-06-29 Ohc Ip Holdings, Llc Securing of panels to grill system
US12295525B2 (en) 2018-06-27 2025-05-13 Ohc Ip Holdings, Llc Grill and side cart attachment systems and methods
US12053120B2 (en) 2018-06-27 2024-08-06 Ohc Ip Holdings, Llc Securing of panels to grill system
US11786074B2 (en) 2018-06-27 2023-10-17 Ohc Ip Holdings, Llc Grill assembly with foldable cart
US10702099B2 (en) 2018-06-27 2020-07-07 Ohc Ip Holdings, Llc Grill and side cart attachment systems and methods
US11096521B2 (en) 2018-06-27 2021-08-24 Ohc Ip Holdings, Llc Side cart locking mechanism
US10772466B2 (en) 2018-06-27 2020-09-15 Ohc Ip Holdings, Llc Grill assembly with foldable cart
US11457770B2 (en) 2018-06-27 2022-10-04 Ohc Ip Holdings, Llc Grill assembly with foldable cart
US11033147B2 (en) 2018-06-27 2021-06-15 Ohc Ip Holdings, Llc Gas tank guard in grill cart
USD928544S1 (en) 2019-06-24 2021-08-24 Ohc Ip Holdings, Llc Grill assembly
USD926519S1 (en) 2019-06-24 2021-08-03 Ohc Ip Holdings, Llc Grill side assembly
USD923996S1 (en) 2019-06-24 2021-07-06 Ohc Ip Holdings, Llc Grill
USD924002S1 (en) 2019-06-24 2021-07-06 Ohc Ip Holdings, Llc Grill cart

Also Published As

Publication number Publication date
KR100246366B1 (en) 2000-03-15
KR19990047477A (en) 1999-07-05
US20020038904A1 (en) 2002-04-04
US7122401B2 (en) 2006-10-17
JPH11312764A (en) 1999-11-09

Similar Documents

Publication Publication Date Title
US7122401B2 (en) Area array type semiconductor package fabrication method
US6781242B1 (en) Thin ball grid array package
US5684330A (en) Chip-sized package having metal circuit substrate
US6563217B2 (en) Module assembly for stacked BGA packages
US7351610B2 (en) Method of fabricating a semiconductor multi-package module having a second package substrate with an exposed metal layer wire bonded to a first package substrate
US6790710B2 (en) Method of manufacturing an integrated circuit package
US7691681B2 (en) Chip scale package having flip chip interconnect on die paddle
US6232213B1 (en) Method of making a semiconductor chip package
US6122171A (en) Heat sink chip package and method of making
US5747874A (en) Semiconductor device, base member for semiconductor device and semiconductor device unit
US20040046241A1 (en) Method of manufacturing enhanced thermal dissipation integrated circuit package
EP0729183A2 (en) Thin packaging of multi-chip modules with enhanced thermal/power management
US20030214049A1 (en) Heat dissipating flip-chip ball grid array
JP2003249607A (en) Semiconductor device and its manufacturing method, circuit board, and electronic equipment
KR20080052482A (en) Multilayer Semiconductor Package
US6245598B1 (en) Method for wire bonding a chip to a substrate with recessed bond pads and devices formed
US6650015B2 (en) Cavity-down ball grid array package with semiconductor chip solder ball
US20060091516A1 (en) Flexible leaded stacked semiconductor package
KR100260996B1 (en) Array type semiconductor package using a lead frame and its manufacturing method
KR19990056764A (en) Ball grid array package
KR100444175B1 (en) ball grid array of stack chip package
JP3073536U (en) Area array type semiconductor package
WO2003017328A2 (en) Encapsulated integrated circuit package and method of manufacturing an integrated circuit package
KR20020057516A (en) Method for manufacturing ball grid array package with thermal emissive plate
JPH09298253A (en) Semiconductor device and mounting structure thereof

Legal Events

Date Code Title Description
AS Assignment

Owner name: LG SEMICON CO., LTD., KOREA, REPUBLIC OF

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SONG, CHI-JUNG;REEL/FRAME:009617/0559

Effective date: 19981103

AS Assignment

Owner name: HYUNDAI ELECTRONICS INDUSTRIES CO., LTD., KOREA, R

Free format text: MERGER;ASSIGNOR:LG SEMICON CO., LTD.;REEL/FRAME:011014/0462

Effective date: 20000621

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20091113