US6043143A - Ohmic contact and method of manufacture - Google Patents

Ohmic contact and method of manufacture Download PDF

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US6043143A
US6043143A US09/072,197 US7219798A US6043143A US 6043143 A US6043143 A US 6043143A US 7219798 A US7219798 A US 7219798A US 6043143 A US6043143 A US 6043143A
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doping
interface
substrate
growing
delta
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US09/072,197
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Kumar Shiralagi
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NXP USA Inc
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Motorola Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28575—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/934—Sheet resistance, i.e. dopant parameters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/938—Lattice strain control or utilization

Definitions

  • This invention relates generally to the field of contacts and, more particularly, to an ohmic contact and methods of manufacture.
  • GaAs gallium arsenide
  • InGaAs indium gallium arsenide
  • InAs indium arsenide
  • the only way to achieve low contact resistance has been to grade the contact layer with In.sub.(1-x) Ga x As, where X varies from 1 to 0, i.e. the layer varies from GaAs to InAs. The problem is that this graded growth introduces substantial complexity in the growth process and is not suitable for selectively grown contacts.
  • the above problems and others are at least partially solved and the above purposes and others are realized in a method of fabricating an ohmic contact and of providing substantial continuity at a crystalline material/substrate interface.
  • the method is generally comprised of the steps of providing a substrate, growing a crystalline material on the substrate and delta doping close to an interface of the substrate and the crystalline material with n-silicon to provide substantial continuity at the interface.
  • FIG. 1 illustrates an energy band diagram at a normal interface of indium arsenide and gallium arsenide
  • FIG. 2 illustrates an energy band diagram at an interface of indium arsenide changed gradually to gallium arsenide using indium gallium arsenide
  • FIG. 3 illustrates an energy band diagram at a silicon doped interface of indium arsenide and gallium arsenide, in accordance with the present invention.
  • the present invention provides, among other things, an ohmic contact, a method of fabricating an ohmic contact, a method of improving contact resistance in a multi-layer heterostructure, and a method of introducing continuity at an interface of indium arsenide and gallium arsenide in an ohmic contact.
  • the present invention is easy to implement, efficient and exemplary for facilitating good contact resistance to allow electron tunneling.
  • FIG. 1 illustrates an energy band diagram, including a conduction band 10 and valence band 11, of a structure 12 with an interface 13 of an indium arsenide (InAs) layer 14 and a gallium arsenide (GaAs) substrate 15. Further shown is a barrier 16 for carriers at interface 13. Barrier 16 prevents good ohmic contact at interface 13 thus inhibiting tunneling along path 17 traversing barrier 16 from InAs 14 to GaAs 15, an anomaly commonly referred to be a result of Fermi level pinning. For the purposes of orientation, path 17 substantially defines the Fermi level.
  • InAs indium arsenide
  • GaAs gallium arsenide
  • FIG. 2 illustrates an energy band diagram, including a conduction band 20 and a valence band 21, of a structure 22 with an interface 23 of an InAs layer 24 and a GaAs substrate 25 using indium gallium arsenide (InGaAs) 26.
  • InGaAs indium gallium arsenide
  • FIG. 2 illustrates an energy band diagram, including a conduction band 20 and a valence band 21, of a structure 22 with an interface 23 of an InAs layer 24 and a GaAs substrate 25 using indium gallium arsenide (InGaAs) 26.
  • InGaAs indium gallium arsenide
  • FIG. 3 illustrates an energy band diagram, including a conduction band 30 and a valence band 31, of a structure 32 with a multiple silicon delta doped interface 33 of an InAs layer 34 and a GaAs substrate 35, in accordance with the present invention.
  • delta doping very close to interface 33 with n-silicon eliminates or otherwise substantially reduces the formation of a barrier and therefore eliminates Fermi level pinning thus providing for a good quality ohmic contact and wide continuity at interface 33.
  • a single delta doping close to interface 33 will reduce the barrier, generally a plurality of delta dopings, illustrated as notches 38 in FIG. 3, provide a more satisfactory interface match.
  • the delta doping farthest from interface 33 will generally be within approximately 1000 ⁇ from interface 33, since delta dopings farther than that have little effect, and the delta doping nearest to interface 33 will generally be within approximately 20 ⁇ to 30 ⁇ from interface 33.
  • the delta doping closest to interface 33 should be as close as possible without being exposed by subsequent process steps, e.g. the formation of layer 34.
  • Structure 32 operative as a non-alloyed ohmic contact, can be used to make single step metalization processes for forming, in addition, a gate contact to the GaAs devices.
  • multiple delta-doped n-silicon close to interface 33 of InAs layer 34 and GaAs layer 35 provides for wide continuity at interface 33 and prevents formation of a wide barrier at the pinned GaAs/InAs interface thus allowing tunneling due to an effective decrease in barrier height and a narrowing of the depletion region.
  • very good contact resistance 3-4 E-7 ohm-cm 2 is possible, Fermi level pinning at the interface is substantially eliminated, the formation of non-alloyed ohmic contacts is possible, and the process can easily be incorporated in epitaxial growth, such as by molecular/chemical beam epitaxy, while eliminating the need to grow compositionally graded InGaAs.
  • delta doping n-silicon has not been herein discussed in great detail, such doping techniques and details are disclosed in exemplary detail in Si Atomic-Planar-Doping in GaAs Made by Molecular Beam Epitaxy, JAPANESE JOURNAL OF APPLIED PHYSICS, Vol. 24, No. 8, August, 1985, pp. L602-L604, of which is incorporated herein by reference.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A method of improving contact resistance in a multi-layer heterostructure comprising the steps of providing a substrate, growing a crystalline material on the substrate, and doping close to an interface of the substrate and the crystalline material with n-silicon to provide continuity at the interface.

Description

FIELD OF THE INVENTION
This invention relates generally to the field of contacts and, more particularly, to an ohmic contact and methods of manufacture.
BACKGROUND OF THE INVENTION
Traditionally, AuGeNi ohmic contacts are used for GaAs based FETs and HEMTs. This requires annealing the device after contacts to temperatures greater than 300-400° C. Non-alloyed ohmic contacts to gallium arsenide (GaAs) have been demonstrated in the past by growing indium gallium arsenide (InGaAs) on GaAs and utilizing the contact to indium arsenide (InAs) to achieve low resistance. In the past the only way to achieve low contact resistance has been to grade the contact layer with In.sub.(1-x) Gax As, where X varies from 1 to 0, i.e. the layer varies from GaAs to InAs. The problem is that this graded growth introduces substantial complexity in the growth process and is not suitable for selectively grown contacts.
Accordingly, it would be highly desirable to provide improved fabrication methods for ohmic contacts.
It is a purpose of the present invention to provide improved fabrication methods for multi-layer heterostructures.
It is another purpose of the present invention to decrease contact resistance in a multi-layer heterostructure.
It is still another purpose of the present invention to provide a new and improved method of providing continuity at a crystalline/substrate interface of an ohmic contact.
It is a further purpose of the present invention to provide a new and improved fabrication method for non-alloyed ohmic contacts.
SUMMARY OF THE INVENTION
The above problems and others are at least partially solved and the above purposes and others are realized in a method of fabricating an ohmic contact and of providing substantial continuity at a crystalline material/substrate interface. The method is generally comprised of the steps of providing a substrate, growing a crystalline material on the substrate and delta doping close to an interface of the substrate and the crystalline material with n-silicon to provide substantial continuity at the interface.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and further and more specific objects and advantages of the instant invention will become readily apparent to those skilled in the art from the following detailed description thereof taken in conjunction with the drawings in which:
FIG. 1 illustrates an energy band diagram at a normal interface of indium arsenide and gallium arsenide;
FIG. 2 illustrates an energy band diagram at an interface of indium arsenide changed gradually to gallium arsenide using indium gallium arsenide; and
FIG. 3 illustrates an energy band diagram at a silicon doped interface of indium arsenide and gallium arsenide, in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT
The present invention provides, among other things, an ohmic contact, a method of fabricating an ohmic contact, a method of improving contact resistance in a multi-layer heterostructure, and a method of introducing continuity at an interface of indium arsenide and gallium arsenide in an ohmic contact. The present invention is easy to implement, efficient and exemplary for facilitating good contact resistance to allow electron tunneling.
Referring now to the drawings, FIG. 1 illustrates an energy band diagram, including a conduction band 10 and valence band 11, of a structure 12 with an interface 13 of an indium arsenide (InAs) layer 14 and a gallium arsenide (GaAs) substrate 15. Further shown is a barrier 16 for carriers at interface 13. Barrier 16 prevents good ohmic contact at interface 13 thus inhibiting tunneling along path 17 traversing barrier 16 from InAs 14 to GaAs 15, an anomaly commonly referred to be a result of Fermi level pinning. For the purposes of orientation, path 17 substantially defines the Fermi level.
To overcome the poor ohmic contact exhibited by structure 12, FIG. 2 illustrates an energy band diagram, including a conduction band 20 and a valence band 21, of a structure 22 with an interface 23 of an InAs layer 24 and a GaAs substrate 25 using indium gallium arsenide (InGaAs) 26. By gradually changing GaAs 25 to InAs 24 using InGaAs 26 to form gradual interface 23 as shown, good ohmic contact is achieved. However, gradually changing InAs layer 24 to GaAs layer 25 using graded InGaAs 26 not only results in a poor structure 22 as shown in FIG. 2, it is very difficult to carry out particularly while growing selective material where the selective growth conditions are a function of the crystalline material composition.
To avoid having to grow selectively graded contact or interface regions as shown in FIG. 2, the barrier obtained at the InAs/GaAs interface 13 as shown in FIG. 1 has to be avoided. In this vein, FIG. 3 illustrates an energy band diagram, including a conduction band 30 and a valence band 31, of a structure 32 with a multiple silicon delta doped interface 33 of an InAs layer 34 and a GaAs substrate 35, in accordance with the present invention. In the present example, although InAs layer 34 and GaAs layer 35 may be heavily doped with n-silicon, delta doping very close to interface 33 with n-silicon eliminates or otherwise substantially reduces the formation of a barrier and therefore eliminates Fermi level pinning thus providing for a good quality ohmic contact and wide continuity at interface 33. While a single delta doping close to interface 33 will reduce the barrier, generally a plurality of delta dopings, illustrated as notches 38 in FIG. 3, provide a more satisfactory interface match. The delta doping farthest from interface 33 will generally be within approximately 1000 Å from interface 33, since delta dopings farther than that have little effect, and the delta doping nearest to interface 33 will generally be within approximately 20 Å to 30 Å from interface 33. As a general rule, the delta doping closest to interface 33 should be as close as possible without being exposed by subsequent process steps, e.g. the formation of layer 34.
This allows electron tunneling along path 36 defining the Fermi level traversing interface 33 from InAs layer 34 to GaAs layer 35. Furthermore, with high delta doping of n-silicon close to interface 33, current conduction is possible in both directions enabling the use of InAs for the source and drain region of a field effect transistor device. Structure 32, operative as a non-alloyed ohmic contact, can be used to make single step metalization processes for forming, in addition, a gate contact to the GaAs devices.
In summary, multiple delta-doped n-silicon close to interface 33 of InAs layer 34 and GaAs layer 35 provides for wide continuity at interface 33 and prevents formation of a wide barrier at the pinned GaAs/InAs interface thus allowing tunneling due to an effective decrease in barrier height and a narrowing of the depletion region. With this technique, very good contact resistance 3-4 E-7 ohm-cm2 is possible, Fermi level pinning at the interface is substantially eliminated, the formation of non-alloyed ohmic contacts is possible, and the process can easily be incorporated in epitaxial growth, such as by molecular/chemical beam epitaxy, while eliminating the need to grow compositionally graded InGaAs. Furthermore, although the specific details of delta doping n-silicon have not been herein discussed in great detail, such doping techniques and details are disclosed in exemplary detail in Si Atomic-Planar-Doping in GaAs Made by Molecular Beam Epitaxy, JAPANESE JOURNAL OF APPLIED PHYSICS, Vol. 24, No. 8, August, 1985, pp. L602-L604, of which is incorporated herein by reference.
The present invention has been described above with reference to a preferred embodiment. However, those skilled in the art will recognize that changes and modifications may be made in the described embodiments without departing from the nature and scope of the present invention. Various changes and modifications to the embodiment herein chosen for purposes of illustration will readily occur to those skilled in the art. To the extent that such modifications and variations do not depart from the spirit of the invention, they are intended to be included within the scope thereof which is assessed only by a fair interpretation of the following claims.
Having fully described the invention in such clear and concise terms as to enable those skilled in the art to understand and practice the same, the invention claimed is:

Claims (14)

What is claimed is:
1. A method of improving contact resistance in a multi-layer heterostructure, the method comprising the steps of:
providing a substrate;
growing a crystalline material on the substrate; and doping close to an interface of the substrate and the crystalline material with n-silicon to provide substantial continuity at the interface.
2. The method of claim 1, wherein the step of providing a substrate further includes the step of providing a gallium arsenide substrate.
3. The method of claim 2, wherein the step of growing a crystalline material further includes the step of growing indium arsenide.
4. The method of claim 3, wherein the step of growing the indium arsenide further includes the step of epitaxially growing indium arsenide.
5. The method of claim 1, wherein the step of doping further includes the step of delta-doping.
6. The method of claim 1, wherein the step of doping further includes the step of epitaxially doping.
7. The method of claim 5, wherein the step of delta-doping further includes the step of epitaxially delta-doping.
8. A method of fabricating an ohmic contact, the method comprising the steps of:
providing a substrate;
defining an interface on a surface of the substrate;
selectively growing a crystalline material on the interface; and
doping close to the interface with n-silicon.
9. The method of claim 8, wherein the step of providing a substrate further includes the step of providing a gallium arsenide substrate.
10. The method of claim 9, wherein the step of growing a crystalline material further includes the step of growing indium arsenide.
11. The method of claim 10, wherein the step of growing the indium arsenide further includes the step of epitaxially growing indium arsenide.
12. The method of claim 8, wherein the step of doping further includes the step of delta-doping.
13. The method of claim 8, wherein the step of doping further includes the step of epitaxially doping.
14. The method of claim 12, wherein the step of delta-doping further includes the step of epitaxially delta-doping.
US09/072,197 1998-05-04 1998-05-04 Ohmic contact and method of manufacture Expired - Fee Related US6043143A (en)

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US09/502,702 US6172420B1 (en) 1998-05-04 2000-02-11 Silicon delta-doped gallium arsenide/indium arsenide heterojunction OHMIC contact

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Cited By (1)

* Cited by examiner, † Cited by third party
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US20080017891A1 (en) * 2006-06-30 2008-01-24 Suman Datta Pinning layer for low resistivity n-type source drain ohmic contacts

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US6670653B1 (en) * 1999-07-30 2003-12-30 Hrl Laboratories, Llc InP collector InGaAsSb base DHBT device and method of forming same
US7281942B2 (en) * 2005-11-18 2007-10-16 Ideal Industries, Inc. Releasable wire connector
US9530708B1 (en) 2013-05-31 2016-12-27 Hrl Laboratories, Llc Flexible electronic circuit and method for manufacturing same

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JPH0783028B2 (en) * 1986-06-02 1995-09-06 株式会社日立製作所 Semiconductor device and manufacturing method
US4780748A (en) * 1986-06-06 1988-10-25 American Telephone & Telegraph Company, At&T Bell Laboratories Field-effect transistor having a delta-doped ohmic contact
US4772934A (en) * 1986-06-06 1988-09-20 American Telephone And Telegraph Company, At&T Bell Laboratories Delta-doped ohmic metal to semiconductor contacts
US5098859A (en) * 1986-06-19 1992-03-24 International Business Machines Corporation Method for forming distributed barrier compound semiconductor contacts
US4784967A (en) * 1986-12-19 1988-11-15 American Telephone And Telegraph Company, At&T Bell Laboratories Method for fabricating a field-effect transistor with a self-aligned gate
US5013685A (en) * 1989-11-02 1991-05-07 At&T Bell Laboratories Method of making a non-alloyed ohmic contact to III-V semiconductors-on-silicon
JPH05304290A (en) * 1992-04-28 1993-11-16 Nec Corp Ohmic electrode
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Publication number Priority date Publication date Assignee Title
US20080017891A1 (en) * 2006-06-30 2008-01-24 Suman Datta Pinning layer for low resistivity n-type source drain ohmic contacts
US7355254B2 (en) * 2006-06-30 2008-04-08 Intel Corporation Pinning layer for low resistivity N-type source drain ohmic contacts

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