US5982004A - Polysilicon devices and a method for fabrication thereof - Google Patents
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- US5982004A US5982004A US08/879,886 US87988697A US5982004A US 5982004 A US5982004 A US 5982004A US 87988697 A US87988697 A US 87988697A US 5982004 A US5982004 A US 5982004A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Definitions
- This invention relates to novel designs of semiconductor devices and to a method for their fabrication.
- the present invention relates to a novel thin film transistor, and in particular to such a transistor having advantages of both conventional thin and thick film devices including high drive current and low leakage current in the off state.
- the transistor has application in particular, but by no means exclusively, in the field of display technology, for example in active matrix LCDs (AMLCDs).
- the fabrication method for this transistor may also, however, be adapted to manufacture other novel semiconductor devices including semiconductor capacitance devices, EEPROM devices, and conductivity modulated thin film transistors.
- Thin film transistors (TFTs) fabricated on polycrystalline silicon (polysilicon) have gained much attention in flat panel displays such as active matrix LCDs and in static random access memory units. In the future it can be expected that the degree of circuit integration will continue to increase as device characteristics improve further, so that an entire system will be formed on a single panel.
- polysilicon thin film transistor technology enables the integration of row and column drive circuitry, and also additional functionality such as image reversal, aspect ratio control and level shifting among others.
- display elements and circuitry both analog and digital
- memories, solar cells, touch sensors and other sensors may all be integrated on the panel.
- EEPROMS electrically erasable and programmable read only memories
- TFT devices made with a thin film have the advantages of lower grain boundary trap density, higher mobility, and higher on-state current. It is desirable to make the thin film transistor as thin as possible in order to provide a high supply current in the on-state.
- Policicchio "Investigations on the Kink Effect in Poly-TFTs", Proceediings of the ESSDERC, pp. 1055-1058, 1996 and A. G. Lewis, T. Y. Huang, R. H. Bruce, M. Koyangi, A. Chiang and I. W. Wu, "Polysilicon Thin Film Transistor for Analogue Circuit Applications", IEDM Tech. Digest, pp. 264-267, 1988.
- the kink effect also causes avalanche induced short channel effects.
- a thin film transistor device comprising source and drain regions formed of doped polysilicon and interconnected by a polysilicon channel region, wherein said channel region is of a reduced thickness in comparison with said drain region.
- the source region is also of a greater thickness than the channel region, and a particularly convenient manner of constructing the device would be for the source and drain regions to be of the same thickness. Possibly, however, advantages over the prior art may in some circumstances also be obtained by providing the source and channel of greater thickness, with the drain region being of smaller thickness. Such a situation may, for example, arise in an EEPROM application of the invention.
- the device is a double gated device.
- one of the gates may be located substantially in a space defined by said channel region being of reduced thickness compared to the drain or source region. By tieing the two gates together increased source-drain current may be obtained.
- the channel region may be of a thickness as low as about 200 ⁇ , though a thickness of about 800 ⁇ would be more typical. Typical thicknesses for the drain region (and also the source region when that is of increased thickness) are about 3000 ⁇ .
- a method for forming a semiconductor device on an insulating substrate comprising the steps of:
- a thin film transistor as described above be manufactured, but so may other novel semiconductor devices including large storage capacitors, memory units and high voltage drivers, comprising a sandwich of three polysilicon layers wherein the middle layer has different thicknesses in different parts of the layer, in particular where the middle polysilicon layer is in the form of thin film where it directly overlies the first layer, and is a thick film where it extends to one or both sides of the first layer.
- the insulating substrate may, for example, be silicon dioxide on a silicon wafer or a glass.
- a semiconductor capacitor formed on an insulating substrate and comprising, a first polysilicon layer deposited on said substrate as a bottom gate, a first oxide layer deposited over said substrate and said bottom gate, a second polysilicon layer deposited over said bottom gate and over said substrate to at least one side of said bottom gate, a second oxide layer deposited over said second polysilicon layer, and a third gate deposited on said second oxide layer as a top gate, said top and bottom gates being electrically connected.
- a semiconductor memory unit formed on an insulating substrate and comprising, a first patterned polysilicon layer formed on said substrate and comprising a back plate, a first oxide layer on said first polysilicon layer and on said substrate, a second polysilicon layer comprising a thin drain region over said back plate and relatively thick source and channel regions to one side of said back plate, a second oxide layer on said second polysilicon layer and on said first oxide layer, a third polysilicon layer on said second oxide layer and generally overlying said channel region and serving as a floating gate, a third oxide layer formed on said floating gate and said second oxide layer, and a fourth polysilicon layer comprising a control gate and deposited on said third oxide layer over said floating gate.
- a thin film transistor comprising a source and a drain, each being formed of a doped polysilicon material on an insulating substrate, said source and said drain being spaced apart by undoped polysilicon material which forms the channel region and by an offset region, wherein said source comprises primarily a material of one conductivity and said drain comprises a material of opposite conductivity, whereby in said offset region conduction is by both electron and hole carriers, and wherein said channel region comprises a polysilicon layer sandwiched between front and back gates and wherein said channel region is thin compared to said offset region and said source and said drain.
- FIG. 1 is a cross-section through an embodiment of a thin film transistor device according to a first embodiment of the present invention
- FIGS. 2(a)-(c) are IV plots for thin film transistors according to the prior art
- FIGS. 3(a)-(d) show schematically a method of fabricating the device of FIG. 1,
- FIG. 4 shows source-drain current as a function of gate voltage for a thin film transist or in accordance with the embodiment of FIG. 1 and in accordance with the prior art for comparison
- FIG. 5 shows in schematic cross-section a semiconductor capacitance device in accordance with an embodiment of the present invention
- FIG. 6 shows in schematic cross-section an electronically erasable and programmable read only memory unit in accordance with an embodiment of the present invention
- FIG. 7 shows the carrier concentration near the drain region in the device of FIG. 6,
- FIG. 8 shows the drain current against gate voltage during programming and erasing of device of FIG. 6,
- FIG. 9 a schematic cross-section in perspective of a conductivity modulated thin film transistor in accordance with an embodiment of the present invention.
- FIG. 10 shows the IV characteristics of the transistor of FIG. 8 with zero back gate bias
- FIG. 11 shows the IV characteristics of the transistor of FIG. 8 with single and double gate operation at a front gate bias of 10V.
- FIG. 1 shows in cross-section an elevated channel thin film transistor (ECTFT) according to a first embodiment of the invention.
- the ECTFT is a self-aligned structure with a channel region thickness of approximately 800 ⁇ and source and drain regions of a thickness of approximately 3000 ⁇ .
- the ECTFT of FIG. 1 is a double-gate structure fabricated on polysilicon using a simple low temperature (below 600° C.) process.
- FIG. 3 illustrates a fabrication method for the ECTFT of FIG. 1.
- a silicon wafer with a thermally grown oxide layer 5000 ⁇ thick was used as the starting substrate.
- a 2000 ⁇ layer of polysilicon was deposited and then doped N + and patterned as the back gate.
- a layer of 1000 ⁇ LPCVD (low pressure chemical vapour deposition) oxide was deposited as back gate oxide and annealed at 600° C.
- a 5000 ⁇ silicon layer was then deposited at 550° C. in amorphous form by LPCVD and subsequently crystallized using a standard solid phase recrystallization method (20 hours in nitrogen ambient at 600° C.). After thus forming a polysilicon island (FIG.
- a 3000 ⁇ LTO (low temperature oxide) was deposited and patterned using the negative of the island mask (FIG. 3(b)). This oxide is used as a polish stop oxide.
- the wafer was then chemo-mechanically polished down to the polish stop (FIG. 3(c)) using a Strasbaugh 6-DT single wafer polisher. Due to the excellent selectivity between polysilicon and LTO during polishing, a very good control of the polysilicon film thickness can be achieved. After polishing, the surface topology becomes flat all over the wafer.
- a 1000 ⁇ APCVD (atmospheric pressure chemical vapour deposition) oxide was then deposited as a front gate oxide, and gate polysilicon was then patterned and a self-aligned N + implantation was performed (FIG. 3(d)).
- a 3000 ⁇ LTO was used as an inter-level dielectric. Using a VIA hole, the front and back gates are contacted. The back gate can be a patterned transparent ITO (indium tin oxide).
- the devices were hydrogenated using r.f. H 2 plasma for 2 hours.
- the device comprises a thin channel region 1 and thicker drain 2 and source 3 regions.
- the thickness of the channel region is about 800 ⁇ and of the drain and source regions about 3000 ⁇ .
- the channel region is physically "elevated" relative to the source and the drain regions.
- One immediate advantage of this structure is that it provides a convenient space beneath the channel region for the provision of the back gate 4.
- the use of a double-gate structure is particularly advantageous since it provides a higher drive current than a single gate structure since the back gate can be tied to the front gate so that current flows in the channel regions adjacent to both back gate 4 and front gate 5.
- the channel region is thin allows for high drive current and low trapped charge density as in conventional TFT devices, but by forming the ECTFT with a much thicker drain region the problems discussed above with regard to a high lateral electric field, in particular at the channel/drain junction, causing impact ionisation, are mitigated.
- the ECTFT of the present invention has low leakage current in the off-state and improved IV characteristics in the on-state in comparison with conventional TFTs.
- FIG. 2 For comparison with the ECTFT of FIG. 1 a conventional TFT device with uniform source/channel/drain thickness of 800 ⁇ and a thick film device with a uniform thickness of 3000 ⁇ were also fabricated in the same run. A comparison of the IV characteristics of the conventional thin film and thick film devices with the ECTFT of the present invention is shown in FIG. 2
- FIG. 2(a) shows the IV characteristics of a thin film device with a uniform thickness of 800 ⁇ in the channel and source/drain regions.
- a large kink on the IV curve is observed and the current increases rapidly with increasing drain voltage and this is particularly so with large values of the gate voltage. This is due to the impact ionisation in the device at higher drain voltages induced by the high electric field at the channel/drain region.
- This increase in electric field in the thin polysilicon film is due to the two-dimensional effect caused by the decrease in drain junction depth.
- FIG. 2(b) shows the IV characteristics of a 3000 ⁇ thick film device. It can be seen that as the thickness of the device increases the kink effect is reduced due to the reduction of the lateral electric field. However, the kink is far from being eliminated completely and this is due to the high content of grain boundary trapped charges present in the thick polysilicon film at the channel/drain junction area in which even a reduced electric field can still cause impact ionization.
- FIG. 2(c) shows the IV characteristics of an ECTFT according to an embodiment of the present invention. It is apparent from FIG. 2(c) that in the present invention the kink effect is almost completely eliminated and that above a drain voltage of about 10V the source-drain current is constant for a given gate voltage. This is due to the relaxed lateral electric field at the drain/channel junction and also the reduction in trapped charges in the thin channel region.
- the output resistance is substantially improved.
- a 40% reduction in on-state current is observed for the thick film device of FIG. 2(b) compared to the thinner device of FIG. 2(a), whereas only a 20% reduction in on-state current is observed for the ECTFT without a back-gate bias compared to the thin film device. Therefore an approximately 30% improvement is observed for the ECTFT compared to a thick film device. This 30% improvement is due to the thinner channel region and the enhancement of electron mobility at the channel surface of the ECTFT after the chemo-mechanical polishing.
- the major factors in the reduction in drain current in the thick film device compared to the thin film device are the larger amount of grain boundary trap charges in the thick channel region and the reduction in the lateral electric field.
- the impact ionisation is increased due to the increase in lateral electric field. This is the reason for the 20% reduction in on-state current in the ECTFT compared to the thin film devices.
- the drain current is increased by over 50% in the saturation region.
- the drain current should be increased by about 100% if both the front and back gates oxide were deposited by APCVD.
- the LTO deposited for the back gate has a higher fixed charge compared to the APCVD oxide deposited for the front gate. Thus, only a 50% increase in saturation current is obtained.
- the ECTFT of the present invention also provides significantly improved performance in terms of leakage current in the off-state.
- FIG. 4 shows the measured gate transfer characteristics of the ECTFT of FIG. 1 compared with conventional thick (3000 ⁇ ) and thin (800 ⁇ ) film devices. From considering the source-drain current at 0V gate voltage, ie the leakage current in the off-state, it can be seen that the ECTFT of the present invention has a leakage current comparable with that of a conventional thick film device and over 15 times lower than that of a thin film device at zero gate bias.
- the ECTFT devices according to the present invention have a large number of possible applications.
- they may be employed in systems formed in panels, for example as a pixel transistor, digital and analogue circuit elements, as a large storage capacitor, and as a memory unit.
- the ECTFT as described above may be used for both analogue and digital circuit applications. Since the device exhibits kink-free IV characteristics, the output resistance of the device is improved thereby increasing the gain.
- the device can be switched with small on-resistance and thus the ECTFT can be used as pixel transistors, digital and analogue circuit elements.
- AMLCD active matrix liquid crystal display
- a large storage capacitance is employed to suppress the image flickering and crosstalk.
- a large area storage capacitor will reduce the aperture ratio and image brightness.
- a double-layer large storage capacitor with much reduced area can be fabricated using the front and back-gates linked by a common node to serve as capacitance plates.
- FIG. 5 illustrates such an arrangement.
- FIG. 6 illustrates the use of the invention in the manufacture of a memory unit, for example an EEPROM cell.
- a patterned back polysilicon layer can be selectively placed so that the various locations of the active polysilicon can be elevated. With the drain region raised appropriately, and when the device operates in the strong inversion regime, the avalanche induced current can be enhanced.
- This approach can be utilised to program/erase an EEPROM cell fabricated on a non-uniform film as shown in FIG. 6.
- This memory cell may be described as an elevated drain EEPROM (ED-EEPROM).
- An ED-EEPROM and an EEPROM without back plate are simulated for comparision.
- a single-crystal silicon model is used.
- the channel length used for the device should be reduced since the avalanche effect only occurs at small channel length for Si devices.
- the simulated ED-EEPROM has a back-plate extension of 0.5 ⁇ from the gate edge near the drain into the chanel region. For all devices the effective channel length is 1.5 ⁇ , channel doping is 1 ⁇ 10 17 cm -3 , inter poly oxide thickness is 400 ⁇ , floating gate oxide thickness is 250 ⁇ , the source junction depth is 0.3 ⁇ and drain junction depth is 0.05 ⁇ .
- the substrate is grounded for the EEPROM without back-plate.
- the cell can be programmed via avalanche channel hot-electron injection from the drain pinch-off region.
- the simulated bias voltages to write and erase the cell are tabulated in Table 1.
- the back-plate of the ED-EEPROM is biased at -4V so that the back-interface near the drain is in accumulation.
- hole concentration near the drain is increased so that it acts like a Zener diode.
- the carrier concentration near the drain region during programming is plotted in FIG. 7. This Zener action helps to increase the hot carrier generation at the drain region, and the hot electrons are injected into the floating gate oxide due to the high electric field across the control gate and the drain.
- the Zener action can be further enhanced if the body of the transistor is connected to the source through a body contact.
- Fowler-Nordheim (FN) current flowing through the gate oxide is used.
- a positive bias is applied to the source and a high enough negative bias is applied to the control gate, thereby pushing the electrons from the floating gate into the active polysilicon film.
- the back-plate may be grounded or biased at the accumulation.
- FIG. 8 shows the drain current versus control gate voltage after the programming and erasing.
- ED-EEPROM shows a larger threshold voltage change with a window of 5V, whereas the EEPROM without back-plate shows a threshold voltage window of 2V.
- the write/erase time of the cells are tabulated in Table 2.
- the ED-EEPROM is faster in writing due to the enhanced impact ionisation of the thin drain and the accumulation of the back interface near the drain region.
- the programming time of the ED-EEPROM is 2 ⁇ s; whereas the EEPROM without back-plate shows a programming time of 50 ⁇ s. Both of them show an erase time of 0.1 ⁇ s.
- CMTFT conductivity modulated TFT
- the CMTFT is a mixed carrier device which uses minority carriers (holes) injected from the p + drain to enhance current conduction.
- the injected holes conductivity modulate the high resistivity offset region and thereby the offset resistance is reduced.
- the injection efficiency of holes at the anode has to be optimized and to do so the junction area at the p + drain has to be increased by increasing the film thickness.
- increasing the film thickness uniformly will have adverse effects on the threshold voltage and on-state current of the device.
- FIG. 9 an elevated channel conductivity modulated thin film transistor (EC-CMTFT) is shown in FIG. 9.
- the EC-CMTFT has a channel region thickness of approximately 800 ⁇ and a source/drain/offset region thickness of approximately 3000 ⁇ .
- the thin channel region is used to achieve high electron current, and the thick drain is used to increase injection of holes from the p + drain. In this way an efficient conductivity modulation is achieved by the thick offset region.
- FIG. 10 shows the IV characteristics of the EC-CMTFT with zero back-gate bias. The combined effect of the enhanced channel electron current and higher hole injection from the thick p + drain results in an efficient conductivity modulation at the thick offset region. This results in a higher current drive in the EC-CMTFT.
- FIG. 11 shows IV characteristics for the single- and double-gate operation at a front gate bias of 10V. Approximately four times improvement in current drive is obtained at a drain voltage of 20V. This result indicates that because of the very thin channel, the entire channel is inverted in the double gate operation whereas only the top surface is inverted in the single gate operation.
- the channel current increases using the double gate operation, correspondingly the hole injection from the drain also increases due to a high electron population at the offset region.
- a four times enhancement in drive current is obtained in the double gate operation.
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Abstract
Description
TABLE 1 ______________________________________ Write/Erase Biases ______________________________________ Write Drain=5V, Control Gate=12V, Floating Gate=4V, Back-plate=-4V and Source=0V Erase Source=8V, Control Gate=-12V, Floating Gate=-4V, Back-plate=-4V and Drain=0V ______________________________________
TABLE 2 ______________________________________ Write/Erase Time Devices Write time Erase time ______________________________________ EEPROM without back-plate 50 μs 0.1 ms ED-EEPROM 2 μs 0.1 ms ______________________________________
Claims (2)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/879,886 US5982004A (en) | 1997-06-20 | 1997-06-20 | Polysilicon devices and a method for fabrication thereof |
JP10175160A JPH1174540A (en) | 1997-06-20 | 1998-06-22 | Polysilicon device and its production |
Applications Claiming Priority (1)
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US08/879,886 US5982004A (en) | 1997-06-20 | 1997-06-20 | Polysilicon devices and a method for fabrication thereof |
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