US5928371A - Systems for programmably interleaving and de-interleaving data and method thereof - Google Patents
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- the present invention is related to the following copending applications:
- This invention relates generally to communication systems, and more particularly, to digital communications systems which require data interleaving or de-interleaving.
- ADSL Asymmetric Digital Subscriber Lines
- noisy transmission lines can cause data to be corrupted or lost.
- additional error-checking data is often transmitted along with the transmitted data (payload data).
- payload data The combination of a group of payload data bytes and the error-checking data for the group of payload data bytes is referred to as a codeword.
- the receiving end of the data transmission can determine if errors have occurred in a particular codeword based on the payload data and error-checking data received. If the amount of error or loss in a codeword is relatively small, the error-checking data can be used to recover the correct payload data.
- Bursts of noise on the transmission media may cause the severity of data corruption in a codeword to be such that recovery is not possible.
- data interleaving techniques can be employed. By interleaving data from different codewords before transmission and de-interleaving the received data at the receiver, the impact of a burst of noise is spread over a number of different codewords, thus reducing the loss in each codeword to a level where recovery of the payload data in each codeword is possible.
- the pattern of interleaving is controlled by two parameters. The first is the number of bytes of data in each codeword, which is represented by the number N. The second is the depth of interleaving to be performed, which is represented by the number D.
- Convolutional interleaving in ADSL requires that each of the N bytes B 0 , B 1 , . . . , B N-1 in a codeword be delayed by an amount that varies linearly with the byte index.
- Byte B i (the byte of the codeword with index i) is delayed by (D-1)*i bytes, where D is the interleave depth.
- memory is required to store the data from multiple codewords before transmission. If a particular byte is to be delayed by 20 bytes, the particular byte must be stored in memory for the next 20 transmissions before its turn to be transmitted arises.
- data is stored in memory in interleaved form and transmitted when completed interleaved codewords become available.
- the amount of memory required to perform the interleave function is equal to N*D bytes. It can be seen that as the number of bytes in a codeword and/or the depth of interleaving increases, the amount of memory required to store the interleaved data increases dramatically. Note that an equivalent amount of memory is required in the de-interleaver of the receiver, as data for different codewords will have to be stored until each de-interleaved codeword is complete.
- ADSL American National Standards Institute
- N codeword
- D depth of interleaving
- the size of each codeword (N) may be equal to 255 bytes, and the depth of interleaving (D) equal to 64.
- Certain parameters of an ADSL system may be varied by the user, and it is desirable for ADSL transceivers to support these different parameters without adding system cost.
- One such parameter is the number of frames in a codeword, designated by the variable S.
- the S value is user selectable and is dependent on the number of payload bytes in a frame and the maximum size of a codeword.
- a group of redundancy bytes are added to the S frames of payload data to form a codeword having a length of N bytes, which equals the number of redundancy bytes (R) plus the aggregate number of basic data bytes (K) for the S frames of data.
- the number of redundancy bytes is chosen to provide a desirable amount of error correction at the receiver.
- the movement of data bytes during interleaving and de-interleaving occurs in a different order as S varies, adding substantial complexity to the interleaving/de-interleaving task.
- FIG. 1 illustrates in block diagram form a data interleaving system including an interleaver according to the present invention.
- FIG. 2 illustrates in partial block diagram and partial logic diagram form the low level controller of FIG. 1.
- FIG. 3 illustrates a block diagram of the interleaver memory of FIG. 1.
- FIG. 4 illustrates a conceptual diagram of a multiple frame codeword which illustrates the flexibility of the present invention.
- FIG. 5 illustrates in partial block diagram and partial logic diagram form a data de-interleaving system according to the present invention.
- FIG. 1 illustrates in block diagram form a data interleaving system 20 including an interleaver 30 according to the present invention.
- Data interleaving system 20 includes generally a top level controller 22, an input buffer 24, an output buffer 26, an interleaver memory 28, and interleaver 30.
- Top level controller 22 controls interleaver 30 to perform an interleaving operation on a codeword associated with data interleaving system 20.
- Top level controller 22 outputs values labelled "PARAMETERS" to each of two portions of interleaver 30 which will be described in further detail below.
- Top level controller 22 also has an output for providing a control signal labeled "GO" and an input for receiving a control signal labeled "DONE".
- data interleaving system 20 is part of an ADSL signal processing system in which input buffer 24 is filled during another signal processing function. In other signal processing systems top level controller 22 may write data directly into input buffer 24.
- Input buffer 24 is a set of N contiguous memory locations where N is a parameter corresponding to the number of symbols in a single codeword.
- N is of arbitrary size, but in the example of an ADSL system could assume a value between zero and 255.
- Each of the N symbols in the illustrated embodiment represents a single byte of data and is labeled a i , where i corresponds to the order of the symbol in input buffer 24.
- Input buffer 24 has an input for receiving an address value labelled "ADDRESS" to indicate which symbol is selected, and an output for providing the symbol data labelled "DATA" addressed by the ADDRESS.
- Output buffer 26 includes the same number of symbols N present in input buffer 24.
- Output buffer 26 has a first input for receiving an address also labelled "ADDRESS", and a second input for receiving symbol data also labelled "DATA".
- the symbols in output buffer 26 are interleaved.
- the first symbol is similarly labeled "a 0 " and corresponds to the first symbol in input buffer 24.
- the second symbol does not correspond to "a 1 " but is symbol data from a prior frame and is labeled labelled "x 1 ".
- the last symbol is from a different prior frame and is labelled "z N-1 ".
- input buffer 24 and output buffer 26 are preferably implemented using the same physical buffer.
- input buffer 24 and output buffer 26 are implemented using the same physical buffer, there are important ramifications for the interleaving operation which will be described further below.
- Interleaver memory 28 is a scratchpad memory for use by interleaver 30 so that interleaver 30 may read data from input buffer 24 and output data to output buffer 26 using the desired interleaving algorithm.
- Interleaver memory 28 has a bidirectional connection to interleaver 30 for conducting control, address, and data signals therebetween. Interleaver memory 28 will be further described with reference to FIG. 3 below.
- Interleaver 30 includes a high level controller 32 and a low level controller 34.
- High level controller 32 has a first control input connected to top level controller 22 for receiving the PARAMETERS therefrom, a second control input for receiving signal "GO" from top level controller 22, and a first control output for providing signal "DONE" to top level controller 22.
- High level controller 32 also has outputs for providing an ADDRESS to each of input buffer 24 and output buffer 26. Note that these ADDRESSes will be a common signal if input buffer 24 and output buffer 26 are implemented by the same physical buffer.
- High level controller 32 has a second control output for providing a signal labelled "COMMAND”, a third control output for providing a signal labelled "GO”, and a third control input for receiving a signal labelled "DONE", all connected to low level controller 34.
- low level controller 34 also has a control input for receiving the PARAMETERS from top level controller 22, a bi-directional data connection for conducting DATA between input buffer 24 and output buffer 26, and a bi-directional connection to interleaver memory 28 for conducting the address, data, and control signals.
- Top level controller 22 provides PARAMETERS to high level controller 32 and low level controller 34 for operation upon data within a codeword of data. In order to effectuate the interleaving of a codeword, top level controller 22 provides parameters to high level controller 32 on a frame-by-frame basis.
- High level controller 32 proceeds to issue commands to low level controller 34 on a symbol basis, to process symbols one at a time until the number of operations specified in the PARAMETERS received from top level controller 22 has been completed.
- the COMMAND output by high level controller 32 includes either a write command, a write-read command, or a read command and is interpreted as a primitive symbol command by low level controller 34.
- high level controller 32 provides control on a frame-by-frame basis whereas low level controller 34 provides operations on a symbol-by-symbol basis.
- This division of functions into two distinct controllers provides flexibility by allowing the user to vary the ADSL parameter S without requiring additional circuit complexity.
- FIG. 2 illustrates in partial block diagram and partial logic diagram form low level controller 34 of FIG. 1. Also illustrated in FIG. 2 is interleaver memory 28.
- Low level controller 34 includes generally a controller 40 and a data path 50.
- Controller 40 has inputs for receiving control signals COMMAND and GO from high level controller 32, and an output for providing the DONE signal to high level controller 32.
- controller 40 has control inputs and outputs which will be further described with reference to data path 50, as well as other timing and control inputs and outputs which are omitted from FIG. 2 to facilitate understanding of the present invention.
- Data path 50 includes generally a write address register 52, a read address register/incrementor 54, an interleaver memory address register 56, data buffers 58, a D register 60, an N register 62, a wrap size register 63, a memory address limit register 64, an initial write address register 65, a multiplexor (MUX) 66, an arithmetic logic unit (ALU) 68, a MUX 70, a comparator 72, a comparator 74, an initial read address register 75, a counter labeled "N -- CNT" 76, and a NOR gate 78.
- Write address register 52 has an input, and an output for providing a WRITE ADDRESS which is the address used by data path 50 when performing a write operation.
- Read address register/incrementor 54 has a first input, a first control input for receiving a control signal labeled "INCREMENT", a second control input for receiving a control signal labeled "REINITIALIZE”, and an output for providing a READ ADDRESS which is the address used by data path 50 when performing a read operation.
- Interleaver memory address register 56 has an input, and an output connected to interleaver memory 28.
- Data buffers 58 have a bidirectional connection to interleaver memory 28 and a bidirectional terminal for conducting the DATA signals.
- Data path 50 includes five registers for storing corresponding PARAMETERS received from top level controller 22, including registers 60, 62, 63, 64, and 65.
- Register 60 stores the D PARAMETER
- register 62 stores the N PARAMETER
- register 63 stores a PARAMETER labelled "WRAP SIZE”
- register 64 stores a PARAMETER labelled "MEMORY ADDRESS LIMIT”
- register 65 stores a PARAMETER labelled "INITIAL WRITE ADDRESS”.
- Each of registers 60, 62, 63, and 65 has an output connected to a corresponding input of MUX 66.
- MUX 66 also has a control input connected to an output of controller 40, and an output terminal.
- ALU 68 has a first input terminal connected to the output terminal of write address register 52, a second input terminal connected to the output terminal of MUX 66, a control terminal connected to an output terminal of controller 40 for receiving a signal labeled "ADD/SUBTRACT", and an output terminal connected to the input terminal of write address register 52.
- MUX 70 has a first input terminal connected to the output terminal of write address register 52, a second input terminal connected to the output terminal of read address register/incrementor 54, a control input terminal connected to an output of controller 40, and an output terminal connected to the input terminal of interleaver memory address register 56.
- Comparator 72 has a first input terminal connected to the output terminal of write address register 52, a second input terminal connected to the output terminal of register 64, and an output terminal for providing a signal labeled "FIX".
- Comparator 74 has a first input terminal connected to the output terminal of read address register/incrementor 54, a second input terminal connected to the output terminal of register 64, and an output terminal connected to an input terminal of controller 40 for providing a control signal labeled "DONE -- CYCLE".
- N -- CNT 76 has an input terminal connected to the output terminal of register 62, and an output terminal for providing a multi-bit counter output signal.
- NOR gate 78 has input terminals connected to corresponding outputs of N counter N -- CNT 76, and an output terminal connected to an input of controller 40 for providing a signal labeled "DONEN".
- controller 40 receives commands which are analogous to primitive commands which allow it to do interleaving operations independently from high level controller 32.
- controller 40 responds to three commands: a write command ("W"), a write followed by read command (“W-R”), and a read command (R).
- W write command
- W-R write followed by read command
- R read command
- controller 40 may respond to any arbitrary command which is a primitive type command useful in the interleaving operation being employed.
- the commands are not limited to these enumerated commands, nor is the order or combination of the commands limited to the illustrated embodiment.
- controller 40 In response to a write command or the write portion of a write-read command, controller 40 causes data path 50 to place the contents of write address register 52 in internal interleaver memory address register 56 by enabling the first input of MUX 70, and to decrement the value of N -- CNT 76.
- data path 50 updates the value in write address register 52. The update is performed according to the following algorithm (expressed in equivalent pseudo-code form): ##EQU1## where J represents the next address and J-1 represents the present address.
- Register 65 stores an INITIAL WRITE ADDRESS, which may be any arbitrary value, and controller 40 activates MUX 66 to select the corresponding input thereof which is then output directly by ALU 68 to be input into write address register 52 during initialization.
- controller 40 causes MUX 66 to select the D input so that the WRITE ADDRESS is incremented by the value of D.
- Controller 40 decrements N -- CNT 76 by one.
- Comparator 72 determines whether the updated memory address exceeds the MEMORY ADDRESS LIMIT and if so, controller 40 causes MUX 66 to select the WRAP SIZE input and to enable ALU 68 for subtraction.
- controller 40 causes MUX 66 to select the N input to add to the WRITE ADDRESS. Finally if after this update comparator 72 detects that the WRITE ADDRESS exceeds the MEMORY ADDRESS LIMIT, controller 40 enables MUX 66 to select the WRAP SIZE input and to enable ALU 68 for subtraction to bring the WRITE ADDRESS back within the bounds of interleaver memory 28.
- controller 40 In response to a read command or the read portion of a write-read command, controller 40 causes MUX 70 to select the second input thereof causing the read address to be loaded into interleaver memory address register 56.
- data path 50 updates the value in read address register/incrementor 54. The update is performed according to the following equation:
- J the next address
- J-1 the present address
- MOD the modulus operation
- Register 75 stores an INITIAL READ ADDRESS, which may be any arbitrary value (but equal to the INITIAL WRITE ADDRESS), and controller 40 causes the value stored in register 75 to be loaded into read address register/incrementor 54 by activating signal REINITIALIZE during initialization.
- Comparator 74 determines whether the READ ADDRESS has reached the modulo limit by comparing it to the value stored in memory address limit register 64, and activates the DONE -- CYCLE signal when it exceeds the MEMORY ADDRESS LIMIT. After a cycle, controller 40 activates signal INCREMENT to read address register/incrementor 54 to increment the value stored therein. In response to an activation of DONE -- CYCLE, however, controller 40 subsequently activates signal REINITIALIZE to cause read address register/incrementor 54 to be reset to point to the first location in interleaver memory 28.
- interleaver memory 28 may be located at address $0.
- initial write address register 65 and initial read address register 75 are not needed because the respective initial addresses will be $0.
- other known modulo adders which are capable of performing these operations may be used as well.
- FIG. 3 illustrates a block diagram of interleaver memory 28 of FIG. 1.
- memory location 80 is the first address in interleaver memory 28.
- FIG. 3 illustrates that corresponding to memory location 80 is a first value 82 labeled "a 0 " and a second value 84 also labeled "a 0 ".
- Value 82 in the lower left corner represents the write value and value 84 in the upper right corner represents the read value. Also shown in FIG.
- memory location 90 which is the last address in interleaver memory 28 and includes a write portion 92 for storing symbol labeled "b 5 " and a read portion 94 for storing a read symbol labeled " ⁇ 6 ". Also illustrated in FIG. 3 are three additional memory elements, 100, 102, and 104, which represent memory locations in interleaver memory 28 which have a significance which will be explained further below.
- FIG. 3 is useful in understanding how interleaver 30 writes data into and reads data from interleaver memory 28. Note that in general, sequential write cycles occur column wise and sequential read cycles occur on an incremental basis from low order to high order addresses in interleaver memory 28. Thus, within codeword a, write addresses are incremented by 4 (D) with appropriate checks.
- interleaver 30 begins writing codeword b at location 100. The reason why the first byte of codeword b (b 0 ) is stored at location 100 is that by the time the seven bytes of codeword a have been stored in interleaver memory 28, seven values have also been read and it is time to write and read b 0 at the same location.
- the values ⁇ 1- ⁇ 6 may represent bytes of present or previous codewords which are interleaved according to the ADSL interleaving system or may represent non-useful data at the beginning of the interleaving sequence.
- symbol b 0 has been written into location 100
- additional symbols b 1 -b 6 are stored by adding four to the write address and appropriately adjusting the address.
- codeword b has been stored in interleaver memory 28
- codeword c begins at location 102 and likewise proceeds.
- Codeword d begins at memory location 104 and also likewise proceeds.
- four codewords have been written into interleaver memory 28 in the prescribed interleaving fashion.
- valid data resides in all locations of interleaver memory 28 such that subsequent reading operations will fetch the data for placement into output buffer 26 for correct transmission according to the ADSL interleaving scheme, and the process begins again at location 80.
- FIG. 4 illustrates a conceptual diagram of a multiple frame codeword which illustrates the flexibility of the present invention.
- a codeword 120 which includes four frames including a first frame 122, a second frame 124, and third frame 126, and a fourth frame 128.
- At the end of the four frames in codeword 120 are four redundancy bytes 130 which allow recovery from a noise burst if such a noise burst corrupts data during transmission.
- Codeword 120 has a size of 32 bytes of which 28 bytes are payload and 4 bytes are redundancy bytes. As illustrated in FIG. 4, the number of frames per codeword (S) is equal to 4. In the example shown in FIG.
- interleaver 30 is able to support such codeword parameters flexibly by allowing high level controller 32 to dispatch appropriate sequences of commands to low level controller 34 to accommodate the codeword.
- top level controller 22 passes the parameters W, W-R, and R as 0, 7 and 1 respectively to form a first command 142 to high level controller 32.
- interleaver 30 performs seven write cycles and eight read cycles.
- top level controller 22 passes parameters W, W-R, and R as 0, 7 and 1 to form second command 144 to high level controller 132 and similarly the parameters W, W-R, and R are equal to 0, 7 and 1 for a third command 146.
- interleaver 30 By the completion of the interleaving operation on third frame 126, twenty-one writes have been performed, but twenty-four reads have been performed. Thus, corresponding to fourth frame 128 and redundancy bytes 130 are three additional write cycles and eight write-read cycles such that by the end of the sequence of commands provided to high level controller by top level controller 22 the number of writes is equal to the number of reads.
- the PARAMETERS N and D are required to be relatively coprime.
- the two-level structure of interleaver 30 allows this requirement to be facilitated.
- the ADSL standard defines D as a power of two.
- N could not be an even number.
- top level controller 22 informs high level controller 32 that there are N bytes and one dummy byte.
- High level controller 32 issues COMMANDS to low level controller 34 to read the dummy byte and place it in interleaver memory 28.
- Low level controller 34 subsequently reads the dummy byte back from interleaver memory 28 and delivers it to high level controller 32.
- high level controller 32 then ignores the dummy byte.
- the ability to insert one or more dummy bytes may be used to further enhance the capability of interleaver 30 to handle special or non-standard buffer sizes.
- FIG. 5 illustrates in partial block diagram and partial logic diagram form a data de-interleaving system 220 according to the present invention.
- Data de-interleaving system 220 includes a high level controller 232, a low level controller 234, and a de-interleaver memory 228.
- High level controller 232 has the same set of control input and output signals as high level controller 32 of FIG. 1.
- Low level controller 234 is substantially a mirror image of low level controller 34 of FIG. 2 and corresponding elements have been assigned corresponding reference numbers in FIG. 5.
- Low level controller 234 is adapted for use with a de-interleaver memory 228, which may be contiguous with interleaver memory 28.
- Low level controller 234 includes generally a controller 240 and a data path 250.
- Controller 240 has inputs for receiving control signals COMMAND and GO from high level controller 232, and an output for providing the DONE signal.
- Low level controller 234 has control inputs and outputs which will be further described with reference to data path 250, as well as other timing and control inputs and outputs which are omitted from FIG. 5 to facilitate understanding of the present invention.
- Data path 250 includes generally a read address register 252, a write address register/incrementor 254, a de-interleaver memory address register 256, data buffers 258, a D register 260, an N register 262, a wrap size register 263, a memory address limit register 264, an initial read address register 265, a MUX 266, an ALU 268, a MUX 270, a comparator 272, a comparator 274, an initial write address register 275, a counter labeled "N -- CNT" 276, and a NOR gate 278.
- Read address register 252 has an input, and an output for providing a READ ADDRESS which is the address used by data path 250 when performing a read operation.
- Write address register/incrementor 254 has a first input, a first control input for receiving a control signal labeled "INCREMENT”, a second control input for receiving a control signal labeled "REINITIALIZE”, and an output for providing a WRITE ADDRESS which is the address used by data path 250 when performing a write operation.
- De-interleaver memory address register 256 has an input, and an output connected to de-interleaver memory 228.
- Data buffers 258 have a bidirectional connection to de-interleaver memory 228 and a bidirectional terminal for providing the DATA signals.
- Data path 250 includes five registers for storing corresponding PARAMETERS received from the top level controller, including registers 260, 262, 263, 264, and 265.
- Register 260 stores the D PARAMETER
- register 262 stores the N PARAMETER
- register 263 stores the WRAP SIZE PARAMETER
- register 264 stores the MEMORY ADDRESS LIMIT PARAMETER
- register 265 stores the INITIAL READ ADDRESS PARAMTER.
- Each of registers 260, 262, 263, and 265 has an output connected to a corresponding input of MUX 266.
- MUX 266 also has a control input connected to an output of controller 240, and an output terminal.
- ALU 268 has a first input terminal connected to the output terminal of read address register 252, a second input terminal connected to the output terminal of MUX 266, a control terminal connected to an output terminal of controller 240 for receiving a signal labeled "ADD/SUBTRACT", and an output terminal connected to the input terminal of read address register 252.
- MUX 270 has a first input terminal connected to the output terminal of read address register 252, a second input terminal connected to the output terminal of write address register/incrementor 254, a control input terminal connected to an output terminal of controller 240, and an output terminal connected to the input terminal of de-interleaver memory address register 256.
- Comparator 272 has a first input terminal connected to the output terminal of read address register 252, a second input terminal connected to the output terminal of register 264, and an output terminal for providing a signal labeled "FIX".
- Comparator 274 has a first input terminal connected to the output terminal of write address register/incrementor 254, a second input terminal connected to the output terminal of register 264, and an output terminal connected to an input terminal of controller 240 for providing a control signal labeled "DONE -- CYCLE".
- N -- CNT 276 has an input terminal connected to the output terminal of register 262, and an output terminal for providing a multi-bit counter output signal.
- NOR gate 278 has input terminals connected to corresponding outputs of N -- CNT 276, and an output terminal connected to an input of controller 240 for providing a signal labeled "DONEN".
- controller 240 also receives primitive commands which allow it to do interleaving operations independently from the high level controller. In the illustrated embodiment, controller 240 responds to the command write-read. This command is used in de-interleaving ADSL codewords. Like controller 40 of FIG. 2, controller 240 may respond to any arbitrary primitive command useful in the de-interleaving operation being employed.
- controller 240 In response to the write portion of a write-read command, controller 240 first causes MUX 270 to select the second input thereof causing the WRITE ADDRESS to be loaded into de-interleaver memory address register 256. In addition, data path 250 updates the value in write address register/incrementor 254. The update is performed according to the following equation:
- controller 240 In response to read portion of a write-read command, controller 240 subsequently causes data path 250 to place the contents of read address register 252 in internal de-interleaver memory address register 256 by enabling the first input of MUX 270.
- data path 250 updates the value in read address register 252. The update is performed according to the following algorithm (expressed in equivalent pseudo-code form): ##EQU2## where as before J represents the next address and J-1 represents the present address.
- Register 265 stores an INITIAL READ ADDRESS, which may be any arbitrary value, and controller 240 activates MUX 266 to select the corresponding input thereof which is then output directly by ALU 268 to be input into read address register 252 during initialization.
- controller 240 causes MUX 266 to select the D input so that the READ ADDRESS is incremented by the value of D.
- Controller 240 decrements N -- CNT 276 by one.
- Comparator 272 determines whether the updated memory address exceeds the MEMORY ADDRESS LIMIT and if so, controller 240 causes MUX 266 to select the WRAP SIZE input and to enable ALU 268 for subtraction.
- controller 240 causes MUX 266 to select the N input to add to the READ ADDRESS. Finally if after this update comparator 272 detects that the READ ADDRESS exceeds the MEMORY ADDRESS LIMIT, controller 240 enables MUX 266 to select the WRAP SIZE input and to enable ALU 268 for subtraction to bring the READ ADDRESS back within the bounds of de-interleaver memory 228.
- Register 275 stores an INITIAL WRITE ADDRESS, which may be any arbitrary value, and controller 240 causes the value stored in register 275 to be loaded into write address register/incrementor 254 by activating signal REINITIALIZE during initialization.
- Comparator 274 determines whether the write address register has reached the modulo limit by comparing it to the value stored in memory address limit register 264, and activates the DONE -- CYCLE signal when it reaches the MEMORY ADDRESS LIMIT. After a cycle controller 240 activates signal INCREMENT to write address register/incrementor 254 to increment the value stored therein. In response to an activation of DONE -- CYCLE, however, controller 240 subsequently activates signal REINITIALIZE to cause write address register/incrementor 254 to be reset to point to the first location in de-interleaver memory 228.
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Description
RADD.sub.J =(RADD.sub.J-1 +1).sub.MOD(N*D) 2!
WADD.sub.J =(WADD.sub.J-1 +1).sub.MOD(N*D) 3!
INITIAL READ ADDRESS=INITIAL WRITE ADDRESS+N+(D-1)- (D-1).sub.MODN ! 4!
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US6311304B1 (en) * | 1997-12-30 | 2001-10-30 | Daewoo Electronics Co., Ltd. | Method for encoding/decoding digital data by using shuffling in digital video home system |
US20020083248A1 (en) * | 2000-12-27 | 2002-06-27 | Matsushita Electric Industrial Co., Ltd. | Interleave circuit, de-interleave circuit and xDSL modem |
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US20150172793A1 (en) * | 2012-08-01 | 2015-06-18 | Alcatel Lucent | Bit-interleaver for an optical line terminal |
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US6311304B1 (en) * | 1997-12-30 | 2001-10-30 | Daewoo Electronics Co., Ltd. | Method for encoding/decoding digital data by using shuffling in digital video home system |
US6178530B1 (en) * | 1998-04-24 | 2001-01-23 | Lucent Technologies Inc. | Addressing scheme for convolutional interleaver/de-interleaver |
US6748033B1 (en) * | 1998-07-17 | 2004-06-08 | Kabushiki Kaisha Kenwood | De-interleave circuit |
US6536001B1 (en) * | 1999-03-11 | 2003-03-18 | Globespanvirata, Inc. | Circuit and method for convolutional interleaving using a single modulo operation |
US6701468B1 (en) * | 1999-09-10 | 2004-03-02 | Pioneer Corporation | Code error correcting circuit, code error correcting method, communicating apparatus and communicating method |
US6634009B1 (en) * | 2000-03-08 | 2003-10-14 | Altera Corporation | Interleaver-deinterleaver megacore |
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US20060026484A1 (en) * | 2001-06-08 | 2006-02-02 | Broadcom Corporation | System and method for interleaving data in a communication device |
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US6718503B1 (en) * | 2002-01-04 | 2004-04-06 | Itran Communications Ltd. | Reduced latency interleaver utilizing shortened first codeword |
US20040015665A1 (en) * | 2002-07-19 | 2004-01-22 | Amit Dagan | De-interleaver method and system |
US7433429B2 (en) | 2002-07-19 | 2008-10-07 | Intel Corporation | De-interleaver method and system |
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US7185241B2 (en) * | 2003-03-14 | 2007-02-27 | Samsung Electronics Co., Ltd. | Deinterleaving apparatus and method for a digital communication system |
US20050193308A1 (en) * | 2004-02-10 | 2005-09-01 | Myeong-Cheol Shin | Turbo decoder and turbo interleaver |
US7343530B2 (en) * | 2004-02-10 | 2008-03-11 | Samsung Electronics Co., Ltd. | Turbo decoder and turbo interleaver |
US20080195823A1 (en) * | 2004-05-19 | 2008-08-14 | Wei-Hung Huang | Method and apparatus for convolutional interleaving/de-interleaving technique |
US8095745B1 (en) * | 2006-08-07 | 2012-01-10 | Marvell International Ltd. | Non-sequential transfer of data from a memory |
US9053052B1 (en) | 2006-08-07 | 2015-06-09 | Marvell International Ltd. | Non-sequential transfer of data from a memory |
US20080291984A1 (en) * | 2007-05-24 | 2008-11-27 | Infineon Technologies Ag | Interleaver apparatus and method |
US8374224B2 (en) | 2007-05-24 | 2013-02-12 | Lantiq Deutschland Gmbh | Interleaver apparatus and method |
US7900119B2 (en) * | 2007-11-30 | 2011-03-01 | Lantiq Deutschland Gmbh | Interleaving redundancy apparatus and method |
US8078939B2 (en) | 2007-11-30 | 2011-12-13 | Lantiq Deutschland Gmbh | Interleaving redundancy apparatus and method |
US20110154153A1 (en) * | 2007-11-30 | 2011-06-23 | Lantiq Deutschland Gmbh | Interleaving Redundancy Apparatus and Method |
US20090144590A1 (en) * | 2007-11-30 | 2009-06-04 | Infineon Technologies Ag | Interleaving redundancy apparatus and method |
US20140286153A1 (en) * | 2008-03-31 | 2014-09-25 | Qualcomm Incorporated | Apparatus and methods for update of symbol information |
US8476768B2 (en) | 2011-06-28 | 2013-07-02 | Freescale Semiconductor, Inc. | System on a chip with interleaved sets of pads |
US9706272B2 (en) * | 2012-08-01 | 2017-07-11 | Alcatel Lucent | Bit-interleaver for an optical line terminal |
US20150172793A1 (en) * | 2012-08-01 | 2015-06-18 | Alcatel Lucent | Bit-interleaver for an optical line terminal |
US10693501B2 (en) * | 2014-03-14 | 2020-06-23 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling interleaving depth |
US20150263766A1 (en) * | 2014-03-14 | 2015-09-17 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling interleaving depth |
US10009042B2 (en) * | 2014-03-14 | 2018-06-26 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling interleaving depth |
US20180278271A1 (en) * | 2014-03-14 | 2018-09-27 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling interleaving depth |
US11018699B2 (en) * | 2014-03-14 | 2021-05-25 | Samsung Electronics Co., Ltd. | Method and apparatus for controlling interleaving depth |
US20160182090A1 (en) * | 2014-12-17 | 2016-06-23 | Samsung Electronics Co., Ltd. | Interleaving method and apparatus for adaptively determining interleaving depth |
US10063259B2 (en) * | 2014-12-17 | 2018-08-28 | Samsung Electronics Co., Ltd. | Interleaving method and apparatus for adaptively determining interleaving depth |
US9959066B2 (en) * | 2016-02-12 | 2018-05-01 | Knuedge Incorporated | Memory-attached computing resource in network on a chip architecture to perform calculations on data stored on memory external to the chip |
US10798756B1 (en) | 2016-06-30 | 2020-10-06 | Acacia Communications, Inc. | Forward error correction systems and methods |
US12004240B2 (en) | 2016-06-30 | 2024-06-04 | Acacia Technology, Inc. | Forward error correction systems and methods |
US10784897B2 (en) | 2018-08-10 | 2020-09-22 | Acacia Communications, Inc. | Deinterleaver |
US10425109B1 (en) * | 2018-08-10 | 2019-09-24 | Acacia Communications, Inc. | Method, apparatus, and system for deinterleaving data |
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