KR100464483B1 - interleave /deinterleave embodiment apparatus and method in ADSL - Google Patents

Abstract

The present invention provides an interleaved / deinterleaved device for quickly and easily implementing a variable codeword size and variable depth to conform to the Asymmetric Digital Subscriber Line (ADSL) Discrete Multi Tone (DMT) standard T1.413 Issue2. The method involves first determining the code word size and depth, initializing the write and read addresses for the memory, temporarily storing the first data entered first, and rest of the variables. Initializing them, calculating virtual dummy data when N is even, making N odd, determining a jump address when N is odd, and N When a code word comes in a set of D, the process of determining the first address to use the T-th incoming N-word code, assigning a memory (RAM) address and actually The process of writing / reading data, receiving the next data byte and storing it temporarily, and determining the address to write / read the next data byte, and when N is even, the address to be read from memory corresponds to the position of virtual dummy data. In this case, it is preferable that a jump process is performed by adding the read address once more.

Description

Interleaved / deinterleave embodiment apparatus and method in ADSL}

FIELD OF THE INVENTION The present invention relates to convolutional interleave and deinterleave implementations, and in particular to variable codeword sizes and variable depths to conform to Asymmetric Digital Subscriber Line (ADSL) Discrete Multi Tone (DMT) standard T1.413 Issue2. The present invention relates to an interleaved / deinterleaved device and a method for quickly and simply implementing the device in (Depth).

In communication, it is necessary to transmit accurate information, and accordingly, there is a channel coding theory of detecting and correcting errors in transmission. Among them, block interleaving is not particularly complicated and does not require additional bandwidth. This is how to maximize.

In the past, due to the lack of semiconductor integration technology, hardware that is too complex or large in size is difficult to implement, and therefore, interleaving theories and algorithms have mainly been to reduce the use of memory as much as possible.

In the conventional interleaving method, most of the memory reduction methods require N * D bytes of memory, but the convolutional interleaving is a special structure of Tong's interleaving. The structure was so complex that it took a lot of time and effort to implement.

As described above, a problem arises in that conventionally, by reducing the memory, the utility thereof is lowered.

Accordingly, the present invention was conceived in view of the above problems, and convolutional interleaver and deinterleaver with N * D byte size memory even though code word size (N byte) and depth (Depth: D, number of levels) are variable. Its purpose is to enable simple and fast implementation of.

1 is a block diagram of an interleaved / deinterleaved implementation device applied to the present invention.

Figure 2 is a read / write progress when the interleave applied to the present invention.

3 is a read / write progress when the deinterleave applied to the present invention.

4 is a flowchart of an interleaved implementation method applied to the present invention.

5 is a flowchart of a deinterleave implementation method applied to the present invention.

<Explanation of symbols for the main parts of the drawings>

10: multiplexer 20: splitter

30: address control logic

40: ram

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

An embodiment of the interleaved / deinterleaved implementation apparatus of the present invention,

A multiplexer performing N * D operations,

A divider that uses only the remainder without using the quotient of the value calculated by the multiplexer,

Address control logic that determines the address each data byte will enter into memory and at each time,

It is preferable that the RAM is configured to sequentially store the addresses determined by the address control logic.

The RAM preferably has a size of N * D bytes.

An embodiment of the interleave implementation method of the present invention,

Determining the code word size and depth first, initializing the write address and read address for the memory, temporarily storing the first data entered, and initializing the remaining variables,

A process of determining a jump address when N is odd by calculating virtual dummy data when N is even, and when N is odd,

When the N-word code consists of D sets, determining the first address to use the T-th incoming N-word code,

Allocating a memory (RAM) address, actually writing / reading data, receiving the next data byte and temporarily storing it,

It is preferable to determine the address to write / read the next data byte. When N is an even number, if the address to be read in the memory corresponds to the position of the virtual dummy data, the read address is added once more to jump.

Preferably, the position of the virtual dummy data indicates a jump address.

An embodiment of the deinterleave implementation method of the present invention,

Determining the code word size and depth first, initializing the write address and read address for the memory, temporarily storing the first data entered first, and initializing the remaining variables,

A process of determining a jump address when N is odd by calculating virtual dummy data when N is even, and when N is odd,

When the N-word code consists of D sets, determining the first address to use the T-th incoming N-word code,

Allocating a memory (RAM) address, actually writing / reading data, receiving the next data byte and temporarily storing it,

It is preferable to determine the address to read / write the next data byte, and if N is an even number, if the address to be written in the memory corresponds to the position of the virtual dummy data, the write address is jumped once more.

Preferably, the position of the virtual dummy data indicates a jump address.

FIG. 1 is a block diagram of an interleaved / deinterleaved implementation device applied to the present invention, FIG. 2 is a read / write progression when the interleaved is applied to the present invention, and FIG. 3 is a readout when the deinterleave applied to the present invention. 4 is a flowchart of an interleaved implementation method applied to the present invention, and FIG. 5 is a flowchart of a deinterleaved implementation method applied to the present invention.

As shown in FIG. 1, when the N * D operation is performed in the multiplexer 10, the divider 20 does not use the quotient of the value calculated in the multiplexer 10 and uses only the remainder.

The address control logic 30 determines an address for each data byte to enter into the memory and an address to be taken out at each time, and the RAM 40 stores the addresses determined by the address control logic 30 in order.

Interleaving when odd is as follows.

TABLE 1

When N = 5, D = 4 (where N is odd)

In Table 1, t is the time when each byte of the codeword comes in, the second row of Table 1 is the actual order of the codeword bytes, and the third row is the interleaved and outgoing bytes.

₁₁ of the third row of Table 1 is i * (D-1), i.e. when not be delayed by a 1 * (4-1) = 3.

Interleaving when even is described as follows.

TABLE 2

When N = 4, D = 4 (where N is even)

1 ₁ in 3 of Table 2 is delayed by i * (D-1), that is, 1 * (4-1) = 3.

However, t ₄ when so ₂₀ have to go so to overlap with the time to a ₁₁ get out of the odd-numbered (odd) when and is to be used the other way, in this case _10, the dummy (dummy) bytes front _{20, 30} is Assuming there are one more each, shuffle this dummy byte in the same way as when N is odd and then remove this dummy byte when exporting from memory.

2 and 3 show the progress of read / write in the interleaved and deinterleaved mode. The numbers shown at the bottom left of each cell represent the respective codewords. The displayed number represents the address of the memory.

As shown in FIG. 4, the code word size and depth are determined first (N ← n, D ← d), the write address and read address to be used for the memory are initialized (W_ADDR ← 0, R_ADDR ← 0), and the first input is performed. After temporarily storing the first data (DATA ← 1stDATA), the remaining variables are initialized (s10). Where n and d are the values to be assigned.

When N is even (s11), even dummy data is calculated and N is odd (N ← N + 1) (s12), and N * D is odd when N is odd. Assign to ND (s13) and determine the jump address (JP_ADDR? (ND-D) Modulo N) (s14).

When N codewords come in D sets, the first N codewords are T = 1 (s15) and the second N codewords are T = 2 ..... in the total N * D memory. When the code word is T = D, it determines the first address to use the N-th code word consisting of T (W_ST_ADDR ← N * (T-1), W_ADDR ← W_ST_ADDR) (s16, s17).

In other words, for example, when N = 5 and D = 4, the first starting address is written from 0 (0,4,8,12,16) and the second starting address is from 5 (5,9,13). Write at 17,1, where the last 1 is 21 Modulo 20) ... After writing the last 4th (D), go back to the beginning.

Allocates memory (RAM) addresses, actually writes and reads data (RAM ADDR ← W_ADDR, RAM DATA ← DATA) (RAM ADDR ← R_ADDR, OUT DATA ← RAM DATA) (s18, s19) (DATA ← Input, I ← I + 1) (s20, s21).

If I = N (s22), T + 1 is assigned to T and 0 is assigned to I (s23), and if T <D (s24), the first address to use the T-th incoming N-word code is determined. If the process enters (s16) and T> D (s24), the process proceeds to assigning 1 to T (s15).

If I = N, write the next data byte and determine the address to read (W_ADDR ← (W_ADDR + D) Modulo ND) (R_ADDR ← (R_ADDR + 1) Modulo ND) (s25, s26), when N is even (EVEN_FLAG = 1) (s27) If the address to be read from the memory is the position (jump address) of the virtual duster data (R_ADDR = JP_ADDR) (s28), the address to be read is jumped one more time (R_ADDR ← (R_ADDR + 1) Modulo ND) (s29 ).

As shown in FIG. 5, the code word size and depth are first determined (N ← n, D ← d), and the write address and read address to be used for the memory are initialized (W_ADDR ← 0, R_ADDR ← 0). After temporarily storing the first data (DATA ← 1st DATA), the remaining variables are initialized (s100).

When N is even (s101), it calculates even dummy data and makes N odd (N ← N + 1) (s12), and N * D when N is odd Assign to ND (s103) and determine the jump address (JP_ADDR? (ND-D) Modulo N) (s104).

When N code words are entered into D sets, the first N code words are T = 1 (s105) and the second N code words are T = 2 ..... in the total N * D memory. When the code word is T = D, it determines the first address to use the N-th code word consisting of the T's (R_ST_ADDR ← N * (T-1), R_ADDR ← R_ST_ADDR) (s106, s107).

Allocates memory (RAM) addresses, actually writes and reads data (RAM ADDR ← W_ADDR, RAM DATA ← DATA) (RAM ADDR ← R_ADDR, OUT DATA ← RAM DATA) (s108, s109) (DATA ← Input, I ← I + 1) (s110, s111).

If I = N (s112), T + 1 is assigned to T, 0 is assigned to I (s113), and if T <D (s114), the first address to use the T-th incoming N code word is determined. If the process enters (s106) and T> D (s24), the process proceeds to assigning 1 to T (s105).

If I = N, determine the address to read and write the next byte of data (R_ADDR ← (R_ADDR + D) Modulo ND) (W_ADDR ← (W_ADDR + 1) Modulo ND) (s115, s116), when N is even (EVEN_FLAG = 1) (s117) If the address to be written in the memory corresponds to the position (jump address) of the virtual duster data (W_ADDR = JP_ADDR) (s118), the address to be written is added one more time and jumped (W_ADDR ← (W_ADDR + 1) Modulo ND) (s119).

In this way, the interleaver and the deinterleaver can be implemented with N * D byte size memory.

As described above, according to the present invention, the algorithm of the convolutional interleaver and the deinterleaver can be simply and quickly implemented with a memory size of N * D byte even though the codeword size (N byte) and the depth (Depth: D) are variable. In addition, this algorithm can be simulated using various S / W or H / W description languages, or can be implemented directly in ASIC. Also, this algorithm can use simulation using C language or logic using VHDL (Very High Speed Descripton Language). Can be implemented.

Claims (6)

A multiplexer that performs N (code word) * D (Depth) operation, A divider that uses only the remainder of the value calculated by the multiplexer and does not use its share; Address control logic that determines the address each data byte will enter into memory and at each time, And storing the addresses determined by the address control logic in order and including a RAM having a size of N * D bytes. delete Determine the codeword size and depth first, initialize the write address and read address to use in memory, temporarily store the first data entered first, and initialize the remaining variables , After the initialization process, if the input data N is even, virtual dummy data is calculated to make N odd, and if N is odd, a determination process of determining a jump address. and, An address determination process of determining a first address to use a T-th incoming N code word when the N code words consisting of D numbers are input into D sets; A temporary storage process of allocating an address of the memory (RAM), actually writing and reading data, and receiving and temporarily storing a next data byte; Determining an address to write / read the next data byte, and if N is an even number, if the address to be read in the memory corresponds to the position of the virtual dummy data, a jump process of adding the read address once more to jump is included. Interleave implementation method. 4. The method of claim 3, wherein the position of the dummy data indicates a jump address. delete delete