US5925916A - Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors - Google Patents

Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors Download PDF

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US5925916A
US5925916A US09/100,522 US10052298A US5925916A US 5925916 A US5925916 A US 5925916A US 10052298 A US10052298 A US 10052298A US 5925916 A US5925916 A US 5925916A
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field effect
diffusion regions
active area
regions
pair
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US09/100,522
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Trung Tri Doan
Charles H. Dennison
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Micron Technology Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/765—Making of isolation regions between components by field effect

Definitions

  • This invention relates to semiconductor processing methods of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors.
  • the drain current (I D ) should only be due to current flow from source to drain through a channel under the gate. This further implies that no significant current between adjacent MOS devices should exist if no channels exist between them.
  • the method by which the components of an integrated circuit are interconnected involves the fabrication of conductive lines that run across oxide in the regions between the transistors, typically referred to as field oxide or field regions. Unfortunately, these conductive lines have a tendency to form gates of parasitic MOS transistors, with the oxide beneath them forming a gate oxide and the diffused regions of separate transistors adjacent the field regions acting as parasitic sources and drains.
  • the threshold voltage of such parasitic transistors is kept higher than any possible operating voltage so that spurious channels will not be inadvertently formed between transistor devices.
  • Two techniques for increasing the threshold voltage are increasing the field-oxide thickness and raising the doping concentration of the bulk substrate area beneath the field oxide.
  • a semiconductor wafer fragment 10 is comprised of a bulk monocrystalline silicon substrate 12 and an isolating field oxide region 14 positioned between a pair of field effect transistor devices 16 and 18.
  • Such transistors each comprise respective gate constructions 20, composed of a conductive portion 21, an underlying gate dielectric layer 22, and opposing insulating sidewall spacers 23.
  • Each transistor is provided with a pair of electrically conductive n+ source/drain diffusion regions 24 and 25.
  • Example dopant concentration for regions 24 and 25 is 1 ⁇ 10 20 ions/cm 3 or greater.
  • Bulk substrate or well area 12 is provided to a p-concentration, such as 1 ⁇ 10 15 ions/cm 3 .
  • Transistors 16 and 18 are also provided with n- lightly doped drain (LDD) regions 26.
  • Example concentration for regions 26 is 1 ⁇ 10 17 ions/cm 3 .
  • an implant has been conducted to provide a higher concentration of p-type material, indicated by the plurality of "+" symbols therebeneath. Such effectively raises the threshold voltage for a preventing a parasitic transistor from forming beneath oxide 14 utilizing the adjacent regions 24 and 25 as parasitic sources and drains.
  • FIG. 2 illustrates an alternate prior art isolation process, referred to as buried-oxide (BOX) isolation technology.
  • BOX buried-oxide
  • Like numerals are utilized from the first described embodiment where appropriate, with differences being indicated with different numerals or with the suffix "a”.
  • Buried-oxide isolation technology typically uses shallow trenches 28 formed within bulk substrate 12 which are refilled with a chemical vapor deposited SiO 2 layer 30. This layer is then etched back to yield the illustrated planar upper surface 31.
  • This invention comprises improved techniques for providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors.
  • FIG. 1 is a diagrammatic sectional view of one prior art semiconductor wafer fragment at a prior art processing step, and is discussed in the "Background" section above.
  • FIG. 2 is a diagrammatic sectional view of another prior art a semiconductor wafer fragment at a prior art processing step, and is discussed in the "Background" section above.
  • FIG. 3 is a diagrammatic sectional view of a semiconductor wafer fragment at one processing step in accordance with the invention.
  • FIG. 4 is a view of the FIG. 3 wafer fragment at a processing step subsequent to that shown by FIG. 3.
  • FIG. 5 is a diagrammatic sectional view of an alternate is embodiment semiconductor wafer fragment at one alternate processing step in accordance with the invention.
  • FIG. 6 is a diagrammatic sectional view of another alternate embodiment semiconductor wafer fragment at another alternate processing step in accordance with the invention.
  • FIG. 7 is a view of the FIG. 6 wafer fragment at a processing step subsequent to that shown by FIG. 6.
  • FIG. 8 is a view of the FIG. 6 wafer fragment at a processing step subsequent to that shown by FIG. 7.
  • a semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors comprises the following steps:
  • the electrically conductive source/drain diffusion regions each having an outermost edge adjacent the insulative isolation mass, such source/drain diffusion regions edges being received within the respective active area regions spaced from the respective mass laterally outermost edges to space the transistor source/drain diffusion regions edges away from the isolation mass.
  • integrated circuitry having adjacent electrically isolated field effect transistors comprises:
  • an electrically insulative device isolation mass received between opposing active area regions, the insulative isolation mass having opposing laterally outermost edges;
  • the electrically conductive source/drain diffusion regions each having an outermost edge adjacent the insulative isolation mass, such source/drain diffusion regions edges being received within the respective active area regions spaced from the respective mass laterally outermost edges to space the transistor source/drain diffusion regions edges away from the isolation mass.
  • FIGS. 3 and 4 A first described embodiment is shown in FIGS. 3 and 4.
  • a semiconductor wafer fragment 32 in process is comprised of a bulk semiconductor substrate 33.
  • An electrically insulative field oxide region 34 has been grown within bulk substrate 33 to effectively define an electrical isolation region 35 positioned between opposing substrate active area regions 37 extending laterally outward of isolation region 35.
  • field oxide region 34 and the respective active area regions 37 join at respective interface edges 36.
  • a pair of transistor gates 41 and 43 are shown comprising respective conductive regions 38 and gate oxide regions 40. Ion implanting is conducted to produce a pair of n- LDD diffusion regions 42 and 44 received within the respective active area regions 37.
  • LDD diffusion regions 42 and 44 each have an outermost edge 45 adjacent and abutting against field oxide region 34.
  • electrically insulating sidewall spacers 46 have been provided relative to conductive gate layer 38 and gate oxide. layer 40.
  • a photoresist masking layer 48 has been deposited and patterned over field oxide region 34. Photoresist mask 48 has lateral outermost edges 50 spaced laterally outward within active area regions 37 beyond the respective interface edges 36.
  • Conductive source/drain diffusion region 52 is received within the left illustrated active area region 37 and is associated with field effect transistor gate 41.
  • Conductive source/drain diffusion region 54 is received within the right illustrated active area region 37 and is associated with field effect transistor 43.
  • Each region 52 and 54 has an outermost edge 55 adjacent field oxide region 34. Such edges 55 are received within the respective active area regions 37, but spaced from respective interface edges 36 to space transistor source/drain diffusion regions edges 55 away from field oxide region 34.
  • FIG. 5 illustrates an alternate embodiment 32a wherein even more isolation is provided by not providing the LDD diffusion regions 42, 44 against field oxide region 34. Such would however come at the added cost of an additional masking step.
  • FIG. 6 there illustrated is a wafer fragment 60 comprised of a bulk semiconductor substrate 62 having an outer surface 64.
  • a buried oxide electrically insulative device isolation mass 65 is provided within bulk substrate 62 to define an electrical isolation region 66 positioned between opposing substrate active area regions 67 extending laterally outward thereof. Insulated isolation mass 65 and the respective active area region 67 join at respective interface edges 68. Buried oxide mass 65 projects outwardly of substrate outer surface 64, and includes sidewalls 70 which project substantially perpendicularly from surface 64.
  • Gates 71 and 72 are provided, and respectively comprise a conductive region 73 and a gate oxide region 74. Ion implanting is preferably conducted to provide the illustrated pair of LDD diffusion regions 75 and 76. Such have outermost lateral edges 77 which abut insulation mass 65.
  • a layer of material 78 is provided over substrate 62, buried oxide 65 projecting therefrom and its associated sidewalls 70, and gates 71 and 72.
  • Layer 78 preferably predominantly comprises SiO 2 .
  • layer 78 might comprise a nitride or material other than the same predominant composition of buried oxide electrically insulative device isolation mass 65.
  • layer 78 is anisotropically etched to provide sidewall spacers 80 over sidewalls 70 of buried oxide mass 65 projecting from substrate outer surface 64, and sidewall spacers 82 about transistor gates 71 and 72. Subsequent heavy ion implanting is conducted to produce the illustrated pair of electrically conductive transistor source/drain diffusion regions 84 and 86 in a manner similar to the first described embodiment. Separate masking could also of course be conducted to provide no LDD diffusion region against electrically insulative device isolation mass 65.
  • the above described embodiments can facilitate provision of thinner electrically insulative device isolation masses between field effect transistors.
  • the respective electrically insulative device isolation masses have their lowest or innermost respective bases provided below the bases of the LDD regions, but not necessarily below the bases of the heavy doped source/drain diffusion regions.
  • spacing of the highly conductive source/drain diffusion regions laterally from the device isolation mass can be utilized in certain design application to eliminate deeper implanted or formed oxide.
  • the invention also contemplates spacing one electrically conductive (heavy implant) diffusion region of one of adjacent field effect transistors away from the device isolation mass. Regardless, preferred spacing of the implant from the device isolation is at least 0.01 micron.

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Abstract

Integrated circuitry having adjacent electrically isolated field effect transistors is disclosed and which includes a bulk semiconductor substrate; an electrically insulative device isolation mass located on the substrate and positioned between opposing active area regions; a first pair of LDD diffusion regions associated with the active area and abutting against the electrically insulative device isolation mass; a pair of field effect transistors each being received within one active area; a second paid of LDD diffusion regions associated with the active area and abutting against each field effect transistor; and a pair of electrically conductive transistor source and drain diffusion regions which are respectively spaced from the insulative isolation mass and field effect transistor.

Description

RELATION PATENT DATA
This application is a divisional application of Ser. No. 08/633,030, which was filed on Apr. 16, 1996, now U.S. Pat. No. 5,895,243.
TECHNICAL FIELD
This invention relates to semiconductor processing methods of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors.
BACKGROUND OF THE INVENTION
Implementing electric circuits involves connecting isolated devices or electronic components through specific electrical paths. When fabricating integrated circuits from semiconductor materials, such as silicon, it must therefore be possible to isolate devices built into the substrate from one another. Such devices are subsequently electrically interconnected to create the specific circuit configurations desired.
A variety of techniques have been developed to isolate devices in integrated circuits. Different integrated circuit types can require somewhat different isolation requirements. For example, PMOS and NMOS integrated circuits require an isolation structure that prevents the establishment of parasitic channels between adjacent transistor devices. MOS transistors are inherently self-isolated.
As long as the source-substrate and drain-substrate pn junctions are held at reverse bias in MOS transistors, the drain current (ID) should only be due to current flow from source to drain through a channel under the gate. This further implies that no significant current between adjacent MOS devices should exist if no channels exist between them. However, the method by which the components of an integrated circuit are interconnected involves the fabrication of conductive lines that run across oxide in the regions between the transistors, typically referred to as field oxide or field regions. Unfortunately, these conductive lines have a tendency to form gates of parasitic MOS transistors, with the oxide beneath them forming a gate oxide and the diffused regions of separate transistors adjacent the field regions acting as parasitic sources and drains. The threshold voltage of such parasitic transistors is kept higher than any possible operating voltage so that spurious channels will not be inadvertently formed between transistor devices. Two techniques for increasing the threshold voltage are increasing the field-oxide thickness and raising the doping concentration of the bulk substrate area beneath the field oxide.
Typical prior art isolation technology is described with reference to FIGS. 1 and 2. Referring first to FIG. 1, a semiconductor wafer fragment 10 is comprised of a bulk monocrystalline silicon substrate 12 and an isolating field oxide region 14 positioned between a pair of field effect transistor devices 16 and 18. Such transistors each comprise respective gate constructions 20, composed of a conductive portion 21, an underlying gate dielectric layer 22, and opposing insulating sidewall spacers 23. Each transistor is provided with a pair of electrically conductive n+ source/drain diffusion regions 24 and 25. Example dopant concentration for regions 24 and 25 is 1×1020 ions/cm3 or greater. Bulk substrate or well area 12 is provided to a p-concentration, such as 1×1015 ions/cm3. Transistors 16 and 18 are also provided with n- lightly doped drain (LDD) regions 26. Example concentration for regions 26 is 1×1017 ions/cm3. Immediately beneath field oxide region 14, an implant has been conducted to provide a higher concentration of p-type material, indicated by the plurality of "+" symbols therebeneath. Such effectively raises the threshold voltage for a preventing a parasitic transistor from forming beneath oxide 14 utilizing the adjacent regions 24 and 25 as parasitic sources and drains.
FIG. 2 illustrates an alternate prior art isolation process, referred to as buried-oxide (BOX) isolation technology. Like numerals are utilized from the first described embodiment where appropriate, with differences being indicated with different numerals or with the suffix "a". Buried-oxide isolation technology typically uses shallow trenches 28 formed within bulk substrate 12 which are refilled with a chemical vapor deposited SiO2 layer 30. This layer is then etched back to yield the illustrated planar upper surface 31.
This invention comprises improved techniques for providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors.
BRIEF DESCRIPTION OF THE DRAWINGS
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
FIG. 1 is a diagrammatic sectional view of one prior art semiconductor wafer fragment at a prior art processing step, and is discussed in the "Background" section above.
FIG. 2 is a diagrammatic sectional view of another prior art a semiconductor wafer fragment at a prior art processing step, and is discussed in the "Background" section above.
FIG. 3 is a diagrammatic sectional view of a semiconductor wafer fragment at one processing step in accordance with the invention.
FIG. 4 is a view of the FIG. 3 wafer fragment at a processing step subsequent to that shown by FIG. 3.
FIG. 5 is a diagrammatic sectional view of an alternate is embodiment semiconductor wafer fragment at one alternate processing step in accordance with the invention.
FIG. 6 is a diagrammatic sectional view of another alternate embodiment semiconductor wafer fragment at another alternate processing step in accordance with the invention.
FIG. 7 is a view of the FIG. 6 wafer fragment at a processing step subsequent to that shown by FIG. 6.
FIG. 8 is a view of the FIG. 6 wafer fragment at a processing step subsequent to that shown by FIG. 7.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws "to promote the progress of science and useful arts" (Article 1, Section 8).
In accordance with one aspect of the invention, a semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors comprises the following steps:
providing an electrically insulative device isolation mass between opposing active area regions, the insulative isolation mass having opposing laterally outermost edges; and
providing a pair of electrically conductive transistor source/drain diffusion regions within the active area regions, one of the conductive source/drain diffusion regions being received within one of the active area regions and being associated with one field effect transistor, the other of the conductive source/drain diffusion regions being received within the other of the active area regions and being associated with another field effect transistor, the electrically conductive source/drain diffusion regions each having an outermost edge adjacent the insulative isolation mass, such source/drain diffusion regions edges being received within the respective active area regions spaced from the respective mass laterally outermost edges to space the transistor source/drain diffusion regions edges away from the isolation mass.
In accordance with another aspect of the invention, integrated circuitry having adjacent electrically isolated field effect transistors comprises:
an electrically insulative device isolation mass received between opposing active area regions, the insulative isolation mass having opposing laterally outermost edges; and
a pair of field effect transistors, one field effect transistor being received within one active area, the other field effect transistor being received within the other active area;
a pair of electrically conductive transistor source/drain diffusion regions within the active area regions, one of the conductive source/drain diffusion regions being received within the one active area region and being associated with the one field effect transistor, the other of the conductive source/drain diffusion regions being received within the other active area region and being associated with the other field effect transistor, the electrically conductive source/drain diffusion regions each having an outermost edge adjacent the insulative isolation mass, such source/drain diffusion regions edges being received within the respective active area regions spaced from the respective mass laterally outermost edges to space the transistor source/drain diffusion regions edges away from the isolation mass.
A first described embodiment is shown in FIGS. 3 and 4. Referring first to FIG. 3, a semiconductor wafer fragment 32 in process is comprised of a bulk semiconductor substrate 33. An electrically insulative field oxide region 34 has been grown within bulk substrate 33 to effectively define an electrical isolation region 35 positioned between opposing substrate active area regions 37 extending laterally outward of isolation region 35. For purposes of the continuing discussion, field oxide region 34 and the respective active area regions 37 join at respective interface edges 36. A pair of transistor gates 41 and 43 are shown comprising respective conductive regions 38 and gate oxide regions 40. Ion implanting is conducted to produce a pair of n- LDD diffusion regions 42 and 44 received within the respective active area regions 37. LDD diffusion regions 42 and 44 each have an outermost edge 45 adjacent and abutting against field oxide region 34.
Referring to FIG. 4, electrically insulating sidewall spacers 46 have been provided relative to conductive gate layer 38 and gate oxide. layer 40. A photoresist masking layer 48 has been deposited and patterned over field oxide region 34. Photoresist mask 48 has lateral outermost edges 50 spaced laterally outward within active area regions 37 beyond the respective interface edges 36.
With photoresist mask 48 in place, ion implanting of a conductivity enhancing dopant impurity is conducted into unmasked areas of substrate active area regions 37 to a concentration effect to form a pair of electrically conductive transistors source/drain diffusion regions 52 and 54. An example and preferred resultant implant concentration is again greater than or equal 1×1020 ions/cm3. Conductive source/drain diffusion region 52 is received within the left illustrated active area region 37 and is associated with field effect transistor gate 41. Conductive source/drain diffusion region 54 is received within the right illustrated active area region 37 and is associated with field effect transistor 43. Each region 52 and 54 has an outermost edge 55 adjacent field oxide region 34. Such edges 55 are received within the respective active area regions 37, but spaced from respective interface edges 36 to space transistor source/drain diffusion regions edges 55 away from field oxide region 34.
The prior art heretofore has been understood to position such electrically conductive diffusion regions entirely against the intervening isolation field or trench oxide. Spacing such regions laterally away from the isolation oxide in accordance with the invention provides the advantage of producing higher junction breakdown voltage, effectively higher field threshold voltage and improved punch-through characteristics.
FIG. 5 illustrates an alternate embodiment 32a wherein even more isolation is provided by not providing the LDD diffusion regions 42, 44 against field oxide region 34. Such would however come at the added cost of an additional masking step.
An alternate embodiment is described with reference to FIGS. 6-8. First with reference to FIG. 6, there illustrated is a wafer fragment 60 comprised of a bulk semiconductor substrate 62 having an outer surface 64. A buried oxide electrically insulative device isolation mass 65 is provided within bulk substrate 62 to define an electrical isolation region 66 positioned between opposing substrate active area regions 67 extending laterally outward thereof. Insulated isolation mass 65 and the respective active area region 67 join at respective interface edges 68. Buried oxide mass 65 projects outwardly of substrate outer surface 64, and includes sidewalls 70 which project substantially perpendicularly from surface 64.
Gates 71 and 72 are provided, and respectively comprise a conductive region 73 and a gate oxide region 74. Ion implanting is preferably conducted to provide the illustrated pair of LDD diffusion regions 75 and 76. Such have outermost lateral edges 77 which abut insulation mass 65.
Referring to FIG. 7, a layer of material 78 is provided over substrate 62, buried oxide 65 projecting therefrom and its associated sidewalls 70, and gates 71 and 72. Layer 78 preferably predominantly comprises SiO2. Alternately, layer 78 might comprise a nitride or material other than the same predominant composition of buried oxide electrically insulative device isolation mass 65.
Referring to FIG. 8, layer 78 is anisotropically etched to provide sidewall spacers 80 over sidewalls 70 of buried oxide mass 65 projecting from substrate outer surface 64, and sidewall spacers 82 about transistor gates 71 and 72. Subsequent heavy ion implanting is conducted to produce the illustrated pair of electrically conductive transistor source/ drain diffusion regions 84 and 86 in a manner similar to the first described embodiment. Separate masking could also of course be conducted to provide no LDD diffusion region against electrically insulative device isolation mass 65.
The above described embodiments can facilitate provision of thinner electrically insulative device isolation masses between field effect transistors. For example with respect to each of the above described embodiments, the respective electrically insulative device isolation masses have their lowest or innermost respective bases provided below the bases of the LDD regions, but not necessarily below the bases of the heavy doped source/drain diffusion regions. In otherwords, spacing of the highly conductive source/drain diffusion regions laterally from the device isolation mass can be utilized in certain design application to eliminate deeper implanted or formed oxide.
Further, the above described preferred embodiments have been described with respect to oxide or device iso lation masses formed relative to bulk semiconductor substrates, and provision of diffusion regions therein. Alternate processing might be conducted apart from bulk semiconductor processing with formation of diffusion regions therein, is with the invention only being limited by the accompanying claims appropriately interpreted in accordance with the doctrine of equivalence.
The invention also contemplates spacing one electrically conductive (heavy implant) diffusion region of one of adjacent field effect transistors away from the device isolation mass. Regardless, preferred spacing of the implant from the device isolation is at least 0.01 micron.
In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims (1)

We claim:
1. Integrated circuitry having adjacent electrically isolated field effect transistor comprising:
a bulk semiconductor substrate;
an electrically insulative device isolation mass received within the bulk substrate positioned between opposing substrate active area regions extending laterally outward thereof, the insulative isolation mass and the respective active area regions joining at respective interface edges, and wherein the electrically insulative isolation mass has an innermost base terminus;
a first pair of LDD diffusion regions associated with the active area and abutting against the electrically insulative device isolation mass, and wherein the first pair of LDD diffusion region have an innermost base terminus;
a pair of field effect transistors, one field effect transistor being received within one active area, the other field effect transistor being received within the other active area;
a second pair of LDD diffusion regions associated with the active area and abutting against each field effect transistor, and wherein the second pair of LDD diffusion regions have an innermost base terminus; and
a pair of electrically conductive transistor source/drain diffusion regions, one of the conductive source/drain diffusion regions being received within the one active area region and being associated with the one field effect transistor, the other of the conductive source/drain diffusion regions being received within the other active area region and being associated with the other field effect transistor, the electrically conductive source/drain diffusion regions each having outermost edges which are respectively spaced from the insulative isolation mass and field effect transistor, such source/drain diffusion regions edges being received within the respective active area regions spaced from the respective interface edges to space the transistor source/drain diffusion regions edges away from the isolation mass, and wherein the source/drain regions have an innermost base terminus, and wherein the isolation mass innermost base terminus is positioned below the innermost base terminus of the first and second pair of LDD diffusion regions, but not below the innermost base terminus of the source and drain regions.
US09/100,522 1996-04-16 1998-06-18 Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors Expired - Lifetime US5925916A (en)

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