FR3022688B1 - METHOD FOR MANUFACTURING AN NMOS TRANSISTOR WITH REDUCED DISLOCATION RISK AND CORRESPONDING INTEGRATED CIRCUIT - Google Patents

METHOD FOR MANUFACTURING AN NMOS TRANSISTOR WITH REDUCED DISLOCATION RISK AND CORRESPONDING INTEGRATED CIRCUIT

Info

Publication number
FR3022688B1
FR3022688B1 FR1455785A FR1455785A FR3022688B1 FR 3022688 B1 FR3022688 B1 FR 3022688B1 FR 1455785 A FR1455785 A FR 1455785A FR 1455785 A FR1455785 A FR 1455785A FR 3022688 B1 FR3022688 B1 FR 3022688B1
Authority
FR
France
Prior art keywords
manufacturing
integrated circuit
nmos transistor
corresponding integrated
reduced dislocation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1455785A
Other languages
French (fr)
Other versions
FR3022688A1 (en
Inventor
Christian Rivero
Julien Delalleau
Guilhem Bouton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1455785A priority Critical patent/FR3022688B1/en
Publication of FR3022688A1 publication Critical patent/FR3022688A1/en
Application granted granted Critical
Publication of FR3022688B1 publication Critical patent/FR3022688B1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
FR1455785A 2014-06-23 2014-06-23 METHOD FOR MANUFACTURING AN NMOS TRANSISTOR WITH REDUCED DISLOCATION RISK AND CORRESPONDING INTEGRATED CIRCUIT Expired - Fee Related FR3022688B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR1455785A FR3022688B1 (en) 2014-06-23 2014-06-23 METHOD FOR MANUFACTURING AN NMOS TRANSISTOR WITH REDUCED DISLOCATION RISK AND CORRESPONDING INTEGRATED CIRCUIT

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1455785A FR3022688B1 (en) 2014-06-23 2014-06-23 METHOD FOR MANUFACTURING AN NMOS TRANSISTOR WITH REDUCED DISLOCATION RISK AND CORRESPONDING INTEGRATED CIRCUIT

Publications (2)

Publication Number Publication Date
FR3022688A1 FR3022688A1 (en) 2015-12-25
FR3022688B1 true FR3022688B1 (en) 2017-01-27

Family

ID=52016659

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1455785A Expired - Fee Related FR3022688B1 (en) 2014-06-23 2014-06-23 METHOD FOR MANUFACTURING AN NMOS TRANSISTOR WITH REDUCED DISLOCATION RISK AND CORRESPONDING INTEGRATED CIRCUIT

Country Status (1)

Country Link
FR (1) FR3022688B1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5069747A (en) * 1990-12-21 1991-12-03 Micron Technology, Inc. Creation and removal of temporary silicon dioxide structures on an in-process integrated circuit with minimal effect on exposed, permanent silicon dioxide structures
US5895243A (en) * 1996-04-16 1999-04-20 Micron Technology, Inc. Semiconductor processing method of providing electrical isolation between adjacent semiconductor diffusion regions of different field effect transistors and integrated circuitry having adjacent electrically isolated field effect transistors
US6077748A (en) * 1998-10-19 2000-06-20 Advanced Micro Devices, Inc. Advanced trench isolation fabrication scheme for precision polysilicon gate control
US6929995B2 (en) * 2003-11-27 2005-08-16 United Microelectronics Corp. Method of forming high voltage metal oxide semiconductor transistor

Also Published As

Publication number Publication date
FR3022688A1 (en) 2015-12-25

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