US5805842A - Apparatus, system and method for supporting DMA transfers on a multiplexed bus - Google Patents

Apparatus, system and method for supporting DMA transfers on a multiplexed bus Download PDF

Info

Publication number
US5805842A
US5805842A US08/534,187 US53418795A US5805842A US 5805842 A US5805842 A US 5805842A US 53418795 A US53418795 A US 53418795A US 5805842 A US5805842 A US 5805842A
Authority
US
United States
Prior art keywords
memory access
direct memory
electronic device
bus
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08/534,187
Other languages
English (en)
Inventor
Ravi Nagaraj
Aniruddha Kunda
James Akiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to US08/534,187 priority Critical patent/US5805842A/en
Assigned to INTEL CORPORATION reassignment INTEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AKIYAMA, JAMES, KUNDA, ANIRUDDHA, NAGARAJ, RAVI
Priority to GB9803706A priority patent/GB2319642B/en
Priority to AU71125/96A priority patent/AU7112596A/en
Priority to PCT/US1996/014939 priority patent/WO1997014100A1/en
Priority to BR9610950A priority patent/BR9610950A/pt
Priority to KR1019980702208A priority patent/KR100271336B1/ko
Priority to DE19681574T priority patent/DE19681574T1/de
Publication of US5805842A publication Critical patent/US5805842A/en
Application granted granted Critical
Priority to HK98112384A priority patent/HK1011228A1/xx
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Definitions

  • the present invention relates to the field of computers. More particularly, the present invention relates to an apparatus and method for allowing legacy devices using direct memory access (“DMA”) transfers to be moved from an Industry Standard Architecture (“ISA”) bus to a Peripheral Component Interconnect (“PCI”) bus.
  • DMA direct memory access
  • ISA Industry Standard Architecture
  • PCI Peripheral Component Interconnect
  • PCs personal computers
  • ISA Industry Standard Architecture
  • I/O input/output
  • the ISA bus is a non-multiplexed bus typically supporting 16-bit data and 24-bit addresses with an operating rate of approximately 8 megahertz (“MHz").
  • a DMA controller e.g., an Intel® 8237 controller
  • PCI Peripheral Component Interconnect
  • the PCI bus is a multiplexed 32-bit bus configured to operate at a rate of approximately 33 MHz.
  • the PCI bus is a multi-master bus which allows one bus master to control one or more bus slaves.
  • a "bus master” is a device (e.g., microprocessor, memory, an I/O device, etc.) which controls a bus by initiating bus cycles.
  • a "bus slave” only receives bus cycles without having a capability of initiating them.
  • a PC 100 comprises a central processing unit (“CPU") 105, main memory 110 (e.g., random access memory “RAM”, read only memory “ROM”, cache, etc.) and two distinct buses, namely a PCI bus 120 and an ISA bus 130. More specifically, the CPU 105 and main memory 110 are coupled to a system controller 115, preferably a memory controller, which is coupled to a PCI bus 120 having the characteristics discussed above.
  • the PCI bus 120 is coupled to an ISA bus 130 through a PCI-ISA bridge 125 to establish a communication path between a number of I/O devices 135, coupled to the ISA bus 130, and the CPU 105 or main memory 110.
  • the PCI-ISA bridge 125 includes, among other things, two DMA controllers (e.g., Intel® 8237 controllers), two interrupt controllers and timing mechanisms (not shown).
  • This PCI-ISA bridge 125 allows the I/O devices 135, for example volatile memory (e.g., EEPROM) 140 and a Super I/O 145, access to the main memory 110.
  • the Super I/O 145 is an interface for a real-time clock, devices coupled through parallel and serial ports and a floppy disk drive controller which is able to request DMA transfers as shown by data paths 146-149, respectively.
  • the I/O devices 135 further include other I/O devices 100 like audio devices which can request DMA transfers and "J" card slots 155 (where "I" is an arbitrary whole number) for connecting a modem, an audio device, network card or other devices which may or may not use DMA to the ISA bus.
  • I is an arbitrary whole number
  • I/O devices 135 connected to the ISA bus 130 can be coupled to the PCI bus 120 in the alternative without incurring any configuration problems.
  • those I/O devices using DMA e.g., floppy disk drive controller, a device 150 coupled to a motherboard and legacy cards using DMA which are inserted into card slots 155, especially those legacy cards used in connection with disk operating system "DOS" based applications
  • DMA disk operating system
  • DMA device For clarity sake, a device, card, etc., which is coupled to the motherboard and can perform DMA transfers, is generically referred to as a "DMA device.”
  • DMA device two distinct types of bus architectures currently are required to be implemented within the PC which poses a number of disadvantages.
  • One primary disadvantage is that the speed limitations associated the ISA bus preclude certain DMA devices, which can operate at a rate greater than 8 MHz, from operating at their optimal level. Collectively, this precludes the PC from achieving its optimum operating speed.
  • Another disadvantage is that it is more costly for computer manufacturers to support two different types of bus architectures instead of a single bus architecture. Yet another disadvantage is that it is confusing to many computer users as to which I/O devices are coupled to which bus types.
  • the present invention relates to an apparatus and corresponding method for enabling a Peripheral Component Interconnect (“PCI”) bus to support greater functionality such as direct memory access (“DMA”) transfers.
  • PCI Peripheral Component Interconnect
  • the apparatus coupled to the PCI bus, comprises a plurality of DMA controllers, a state machine and an internal storage element.
  • the plurality of DMA controllers are responsive to a DMA request from one of its DMA devices ("targeted DMA device") by issuing a DMA acknowledge signal once the apparatus is ready to support DMA transfers to be made on the PCI bus.
  • the state machine controls the operations of the apparatus by performing two transactions in response to a DMA request. These transactions include the performance of a memory cycle and an input/output cycle.
  • the internal storage element provides internal buffering to allow a multiple cycle DMA transfer to be performed in lieu of a typical single cycle DMA transfer.
  • the apparatus includes a location register to better predict whether the targeted DMA device resides on the PCI bus or on an Industry Standard Architecture bus.
  • FIG. 1 is an illustrative block diagram of a conventional computer system implementing both an Industry Standard Architecture (“ISA”) bus and a Peripheral Component Interconnect (“PCI”) bus.
  • ISA Industry Standard Architecture
  • PCI Peripheral Component Interconnect
  • FIG. 2 is an illustrative block diagram of a personal computer having a number of I/O devices using DMA which are coupled to the PCI bus instead of the ISA bus.
  • FIG. 3 is an illustrative block diagram of a PCI I/O device including DMA controllers, a state machine, an internal storage element and a location register to collectively control via control lines the operations of the PCI-ISA bridge of FIG. 2.
  • FIG. 4 is an illustrative block diagram of the bit representations of the location register of FIG. 3.
  • FIG. 5 is an illustrative flowchart setting forth the operational steps necessary to support DMA devices coupled to either the PCI bus and the ISA bus to exchange information with main memory.
  • FIGS. 6a and 6b collectively are an illustrative flowchart incorporating the operational steps set forth in FIG. 5 as well as additional operational steps to avoid latency resulting from successive checks in locating the DMA device.
  • the present invention describes a system and method for increasing the functionality on a PCI bus by enabling I/O devices using DMA to be supported by the PCI bus.
  • the following detailed description is presented largely in terms of block diagrams and flowcharts which clearly illustrate the present invention in detail but does not discuss well-known circuits or process steps to avoid unnecessarily obscuring the present invention.
  • the flowcharts illustrate a series of steps leading to a desired result. These steps require physical manipulations of physical quantities in the form of electrical or magnetic signals capable of being stored, transferred, combined, compared or otherwise manipulated.
  • the computer system 200 comprises a CPU 205 and a main memory element 210 (e.g., RAM, ROM, cache, etc.) coupled to a system controller 215.
  • the system controller 215 is coupled to a PCI bus 220 which interconnects a number of devices including, but not limited to a PCI I/O device 225 and "n" DMA devices 230a-230n coupled to the motherboard (where "n" is an arbitrary whole number).
  • the PCI I/O device 225 which acts solely as a bridge, is coupled to an Industry Standard Architecture ("ISA") bus (not shown) through a bus including control lines 235 as shown.
  • ISA Industry Standard Architecture
  • the PCI I/O device 225 now supports control lines 240a-240n which are used by the DMA devices 230a-230n to exchange information with the PCI I/O device 225 transparent to the operating software.
  • the PCI I/O device 225 preferably comprises a pair of DMA controllers 300 and 310, a state machine 320, an internal storage element 340, a PCI state machine 360 and an ISA state machine 370.
  • the DMA controllers 300 and 310 e.g., Intel® 8237 controllers
  • DRQ DMA Request
  • DACK DMA Acknowledge
  • the DRQ control lines 330 are used to signal the DMA controllers 300 and 310 that a DMA device connected to either the ISA bus 245 or to the PCI bus 220 requests a DMA transfer to occur and the DACK control lines 335 are used to indicate that the DMA transfer can begin.
  • the DMA controller 300 asserting a first Hold Request (“HRQ1”) signal via control line 311 into the state machine 320 upon detecting a DMA request from one of its supported DMA devices via DRQ lines 330, namely "DRQ 3:0!.
  • the DMA controller 310 asserts a second Hold Request (“HRQ2”) signal via control line 312 into the DMA controller 300 upon detecting a DMA request from one of its supported DMA devices through the remaining DMA channels "DRQ 7:4!.
  • the DMA controllers 300 and 310 are cascaded together to operate as a collective unit by the HRQ1 signal being asserted by the DMA controller 300 if the HRQ2 signal is asserted to indicate that a DMA request has been received and is awaiting attention.
  • the state machine 320 is able to determine whether the DMA transfer is a memory read or a memory write from DMA command registers in the DMA controller 300 and/or 310. It is contemplated that more than eight (8) DMA channels, as shown, can be supported by the PCI I/O device 225 by increasing the number of DMA controllers.
  • the PCI I/O device 225 In response to asserting one of the DRQ lines, the PCI I/O device 225 performs the DMA operation by splitting the operation into two PCI cycles; namely one memory cycle and one I/O cycle.
  • the PCI I/O device 225 For a DMA memory read operation initiated by a DMA device coupled to the PCI bus, the PCI I/O device 225 (i) issues a PCI memory read cycle and thereafter, (ii) issues an I/O write cycle with a dummy address onto the PCI bus 220.
  • the dummy address is not associated with any hardware device coupled to the PCI bus 220 but is sent for the sake of completeness to check whether the targeted DMA device responds to the I/O write cycle.
  • the state machine 320 upon receiving an asserted HRQ1 signal from the DMA controller 300, the state machine 320 signals the PCI state machine 360 via control line 321 to request ownership of the PCI bus 220.
  • the PCI state machine 360 Upon the PCI state machine 360 receiving ownership of the PCI bus 220 for the PCI I/O device 225, the PCI state machine 360 places a requested memory address onto the PCI bus 220 to be received by the main memory element (not shown) which, in response, places data onto the PCI bus 220.
  • the state machine 320 asserts a control signal via control line 322 to the internal storage element 340 to receive the data in parallel via data lines 341.
  • the internal storage element 340 operates as a temporary buffer to store a predetermined number of bits (e.g., 32-bits) from memory during a DMA memory read operation and the targeted DMA device during a DMA memory write operation. This is necessary since two PCI cycles are needed to perform a DMA operation.
  • a predetermined number of bits e.g., 32-bits
  • the state machine 320 asserts a first Hold Acknowledge (“HLDA1”) control line 313 which indicates to the DMA controller 300 that the PCI memory read cycle has completed.
  • a second HLDA control line (“HLDA2”) 314 is asserted if the targeted DMA device is supported by the DMA controller 310.
  • the DMA controller supporting the targeted DMA device issues a DACK signal.
  • the state machine 320 signals the PCI state machine 360 to issue an I/O write cycle on the PCI bus by placing the data stored in the internal storage element 340 and a dummy address onto the PCI bus 220. If the targeted DMA device is coupled to the PCI bus 220, it receives the data and the DMA transfer is completed. However, if there is no response to the I/O write cycle indicating that targeted DMA device is coupled to the ISA bus 245, the state machine 320 requests the ISA state machine 370 to perform multiple ISA I/O write cycles which are well known in the art.
  • the PCI I/O device 225 issues an I/O read cycle with the dummy address and then issues a PCI memory write cycle onto the PCI bus with a memory address. These PCI cycles prevent software from detecting that DMA operations are not being performed by a device coupled to the ISA bus 245.
  • the targeted DMA device would assert its corresponding DRQ line 330.
  • the DMA controller 300 would issue the HRQ1 signal.
  • the state machine 320 Upon receiving the asserted HRQ1 signal from the DMA controller 300, the state machine 320 signals the PCI state machine 360 via control line 321 to request ownership of the PCI bus 220. Once the PCI bus 220 is acquired, the state machine 320 asserts the HLDA1 control line 313, possibly causing assertion of the HLDA2 control line 314 if responding to a DRQ signal supported by DMA controller 310, to indicate to the DMA controllers 300 and 310 that they can issue a DACK signal to the targeted DMA device.
  • the state machine 320 prompts the PCI state machine 360 to issue an I/O read cycle with a dummy address. If the targeted DMA device responds, it places 32-bits of data at a time into the internal storage element 340 which are written to the main memory element in the next PCI memory write cycle. However, if the targeted DMA device does not respond, suggesting that the targeted DMA device is coupled to the ISA bus 245, the state machine 320 signals the ISA state machine 370 to control data propagation into the internal storage element 340 via data lines 342. Once the internal storage element 340 is full, the state machine 320 signals the PCI state machine 360 to write the data to the main memory element.
  • a location register 350 may be employed within the PCI I/O device 225.
  • the location register 350 is coupled to the state machine 320 through a 16-bit data bus 351 and control lines 352.
  • a 16-bit data bus is necessary since the location register 350, as shown in FIG. 4, is 16-bits in length since two bits are associated with each potential DMA channel. Since there are two DMA controllers each providing up to 4 DMA channels, a total of 8 DMA channels (labeled "CH”) 360-367 can be supported. However, it is contemplated that the location register 350 can be adjusted depending on the number of DMA channels supported by the PCI I/O device 225.
  • One bit corresponding to each DMA channel is an identification bit ("IB") which, when set (logic level “1") indicates that the bus, on which the targeted DMA device resides, has been previously determined.
  • the "identification” bit gets flushed whenever the I/O address range of the DMA controller is written.
  • the other bit associated with each DMA channel is a bus bit ("BB") which, when cleared (logic level "0"), indicates that a targeted DMA device resides on the PCI bus. Otherwise, if the bus bit is set (logic "1"), the targeted DMA device resides on the ISA bus.
  • the location register 350 is defaulted to "0".
  • Step 405 a DMA device (hereinafter referred to as the "targeted DMA device") issues a DRQ signal to the PCI I/O device requesting DMA.
  • the PCI I/O device determines whether the targeted DMA device is requesting DMA read operation or a DMA write operation trough the DMA command reaisters (Step 410).
  • the PCI I/O device requests ownership of the PCI bus by asserting a request ("REQ") signal transmitted to a PCI bus arbiter typically implemented within the system controller (Step 415).
  • REQ request
  • a PCI bus arbiter typically implemented within the system controller
  • the PCI I/O device Upon the PCI bus arbiter granting ownership of the PCI bus to the PCI I/O device by returning a grant ("GNT") signal, the PCI I/O device transmits a DMA acknowledge (“DACK”) signal to the targeted DMA device (Steps 420 and 425). Thereafter, the PCI I/O device issues an I/O read cycle on the PCI bus with a dummy address (Step 430).
  • DACK DMA acknowledge
  • the dummy address is a predetermined address unavailable to any device coupled to the PCI bus in order to prevent a device from accidentally claiming the I/O read cycle. As a result, only the targeted DMA device can claim the I/O read cycle, provided the targeted DMA device is coupled to the PCI bus.
  • Step 435 a check is made as to whether the targeted DMA device responds to the I/O read cycle within three clock cycles. If the targeted DMA device responds thereby indicating that the targeted DMA device is coupled to the PCI bus, the targeted DMA device transmits data (32-bits every cycle) into the internal storage element of the PCI I/O device (Step 440). After the internal storage element becomes full or the data is the last bytes associated with the DMA write operation, the targeted DMA device issues a PCI memory write cycle to write the data stored in the internal storage element into memory (Step 445). This process continues until all the data associated with the DMA write operation has been transmitted to main memory.
  • the PCI I/O device issues (i) an ISA I/O read cycle to the ISA bus in which the targeted DMA device transmits data (8-bits every cycle) into the internal storage element and thereafter (ii) issues the PCI memory write cycle as shown through Steps 440-450.
  • the PCI I/O device requests ownership of the PCI bus and awaits such ownership (Steps 455 and 460).
  • the PCI I/O device issues a PCI memory read cycle onto the PCI bus to obtain data from main memory (Step 465).
  • the PCI I/O device receives this data and temporarily stores the data within the internal storage element (Step 470).
  • the PCI I/O device transmits an acknowledge signal ("DACK") to the targeted DMA device (Step 475).
  • DACK acknowledge signal
  • the PCI I/O device issues an I/O write cycle on the PCI bus with a dummy address (Step 480).
  • Step 485 a check is made as to whether the targeted DMA device responds to the I/O write cycle within at most three clock cycles. If the targeted DMA device responds thereby indicating that the targeted DMA device is coupled to the PCI bus, the targeted DMA device has received the data from the internal storage element and the process continues until the all data associated with the DMA has been transmitted to the targeted DMA device. However, as shown in Step 490, if the targeted DMA device fails to respond, the PCI I/O device issues an ISA I/O write cycle to the ISA bus in which the targeted DMA device receives 8-bits of data at a time until the internal storage element is empty.
  • flag bits i.e., "identification” and "bus” bits
  • Step 426 after the PCI I/O device sends the DACK signal to the targeted DMA device, a determination is made as to whether the location of the targeted DMA device has been previously determined. This is accomplished by checking whether the identification bit associated with the channel used by the targeted DMA device is set. If it is not set, the processor continues to Step 430, and thereafter, at Step 436 or alternately at Step 437, the appropriate identification and bus bits are set to indicate that the targeted DMA device is coupled to PCI or ISA bus, respectively.
  • Step 427 another determination is made as to whether the targeted DMA device is coupled to the PCI bus by determining the logic state of the bus bit corresponding to the above-checked identification bit (Step 427). If so, the process continues to Step 430 but if targeted DMA device is coupled to the ISA bus, the process ignores Steps 430 and 435 and successively performs Steps 450, 440 and 445. It is contemplated that the same type of additional operations occur in the event that the DMA operation is a memory read as shown in Steps 476-477 and 486-487.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
US08/534,187 1995-09-26 1995-09-26 Apparatus, system and method for supporting DMA transfers on a multiplexed bus Expired - Lifetime US5805842A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US08/534,187 US5805842A (en) 1995-09-26 1995-09-26 Apparatus, system and method for supporting DMA transfers on a multiplexed bus
BR9610950A BR9610950A (pt) 1995-09-26 1996-09-18 Sistema de um método para aumento da fucionalidade no barramento de interconexão de componente periférico
AU71125/96A AU7112596A (en) 1995-09-26 1996-09-18 A system and method for increasing functionality on the peripheral component interconnect bus
PCT/US1996/014939 WO1997014100A1 (en) 1995-09-26 1996-09-18 A system and method for increasing functionality on the peripheral component interconnect bus
GB9803706A GB2319642B (en) 1995-09-26 1996-09-18 A system and method for increasing functionality on the peripheral component interconnect bus
KR1019980702208A KR100271336B1 (ko) 1995-09-26 1996-09-18 주변구성요소 내부접속 버스상의 기능을 향상시키는 장치 및방법
DE19681574T DE19681574T1 (de) 1995-09-26 1996-09-18 System und Verfahren zum Erhöhen der Funktionalität am PCI-Bus
HK98112384A HK1011228A1 (en) 1995-09-26 1998-11-27 A system and method for increasing functionality on the peripheral component interconnect bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/534,187 US5805842A (en) 1995-09-26 1995-09-26 Apparatus, system and method for supporting DMA transfers on a multiplexed bus

Publications (1)

Publication Number Publication Date
US5805842A true US5805842A (en) 1998-09-08

Family

ID=24129034

Family Applications (1)

Application Number Title Priority Date Filing Date
US08/534,187 Expired - Lifetime US5805842A (en) 1995-09-26 1995-09-26 Apparatus, system and method for supporting DMA transfers on a multiplexed bus

Country Status (8)

Country Link
US (1) US5805842A (ko)
KR (1) KR100271336B1 (ko)
AU (1) AU7112596A (ko)
BR (1) BR9610950A (ko)
DE (1) DE19681574T1 (ko)
GB (1) GB2319642B (ko)
HK (1) HK1011228A1 (ko)
WO (1) WO1997014100A1 (ko)

Cited By (82)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6131133A (en) * 1997-08-02 2000-10-10 U.S. Philips Corporation Data exchange interface that directly transmits control signals either to a microprocessor or a D.M.A. controller via a first and second control line respectively
US6138183A (en) * 1998-05-06 2000-10-24 Ess Technolgoy Inc. Transparent direct memory access
WO2001042913A1 (en) * 1999-12-07 2001-06-14 Advanced Micro Devices, Inc. Register arrangement for optimum access
US20020038393A1 (en) * 2000-09-08 2002-03-28 Kumar Ganapathy Method and apparatus for distributed direct memory access for systems on chip
US20020058502A1 (en) * 2000-11-13 2002-05-16 Peter Stanforth Ad hoc peer-to-peer mobile radio access system interfaced to the PSTN and cellular networks
US6412027B1 (en) * 1998-02-11 2002-06-25 Globespanvirata, Inc. Direct memory access controller having on-board arbitration circuitry
US20020116555A1 (en) * 2000-12-20 2002-08-22 Jeffrey Somers Method and apparatus for efficiently moving portions of a memory block
US20020191573A1 (en) * 2001-06-14 2002-12-19 Whitehill Eric A. Embedded routing algorithms under the internet protocol routing layer of a software architecture protocol stack in a mobile Ad-Hoc network
US20030018844A1 (en) * 1998-05-07 2003-01-23 Kazuhito Akiyama Data processing device having a plurality of state-machine parts
US20030035437A1 (en) * 2001-08-15 2003-02-20 Masood Garahi Movable access points and repeaters for minimizing coverage and capacity constraints in a wireless communications network and a method for using the same
US20030040316A1 (en) * 2001-03-22 2003-02-27 Peter Stanforth Prioritized-routing for an ad-hoc, peer-to-peer, mobile radio access system based on battery-power levels and type of service
US20030043790A1 (en) * 2001-09-06 2003-03-06 Philip Gutierrez Multi-master bus architecture for system -on-chip designs
US20030058886A1 (en) * 2001-09-25 2003-03-27 Stanforth Peter J. System and method employing algorithms and protocols for optimizing carrier sense multiple access (CSMA) protocols in wireless networks
US20030060202A1 (en) * 2001-08-28 2003-03-27 Roberts Robin U. System and method for enabling a radio node to selectably function as a router in a wireless communications network
US20030061428A1 (en) * 2001-09-25 2003-03-27 Intel Corporation Dynamic master/slave configuration for multiple expansion modules
US20030091012A1 (en) * 2001-08-15 2003-05-15 Barker Charles R. System and method for providing an addressing and proxy scheme for facilitating mobility of wireless nodes between wired access points on a core network of a communications network
US20030091011A1 (en) * 2001-08-15 2003-05-15 Roberts Robin U. System and method for performing soft handoff in a wireless data network
US6580981B1 (en) 2002-04-16 2003-06-17 Meshnetworks, Inc. System and method for providing wireless telematics store and forward messaging for peer-to-peer and peer-to-peer-to-infrastructure a communication network
US20030142638A1 (en) * 2000-11-08 2003-07-31 Belcea John M. Time division protocol for an ad-hoc, peer-to-peer radio network having coordinating channel access to shared parallel data channels with separate reservation channel
US6617990B1 (en) 2002-03-06 2003-09-09 Meshnetworks Digital-to-analog converter using pseudo-random sequences and a method for using the same
US20030214921A1 (en) * 2002-05-16 2003-11-20 Alapuranen Pertti O. System and method for performing multiple network routing and provisioning in overlapping wireless deployments
US20030227895A1 (en) * 2002-06-05 2003-12-11 Strutt Guenael T. System and method for improving the accuracy of time of arrival measurements in a wireless ad-hoc communications network
US20030228875A1 (en) * 2002-06-05 2003-12-11 Alapuranen Pertti O. MAC protocol with duty-cycle limitation for portable devices in a wireless Ad-Hoc communication network and a method for using the same
US20030227934A1 (en) * 2002-06-11 2003-12-11 White Eric D. System and method for multicast media access using broadcast transmissions with multiple acknowledgements in an Ad-Hoc communications network
US6674790B1 (en) 2002-01-24 2004-01-06 Meshnetworks, Inc. System and method employing concatenated spreading sequences to provide data modulated spread signals having increased data rates with extended multi-path delay spread
US20040005902A1 (en) * 2002-07-05 2004-01-08 Belcea John M. System and method for correcting the clock drift and maintaining the synchronization of low quality clocks in wireless networks
US6687259B2 (en) 2002-06-05 2004-02-03 Meshnetworks, Inc. ARQ MAC for ad-hoc communication networks and a method for using the same
US20040028017A1 (en) * 2002-07-29 2004-02-12 Whitehill Eric A. System and method for determining physical location of a node in a wireless network during an authentication check of the node
US6728232B2 (en) 2002-03-15 2004-04-27 Meshnetworks, Inc. System and method for auto-configuration and discovery of IP to MAC address mapping and gateway presence in wireless peer-to-peer ad-hoc routing networks
US6728545B1 (en) 2001-11-16 2004-04-27 Meshnetworks, Inc. System and method for computing the location of a mobile terminal in a wireless communications network
US20040082341A1 (en) * 2002-05-17 2004-04-29 Stanforth Peter J. System and method for determining relative positioning in ad-hoc networks
US20040081166A1 (en) * 2002-05-01 2004-04-29 Stanforth Peter J. System and method for using an ad-hoc routing algorithm based on activity detection in an ad-hoc network
US6744766B2 (en) 2002-06-05 2004-06-01 Meshnetworks, Inc. Hybrid ARQ for a wireless Ad-Hoc network and a method for using the same
US6754188B1 (en) 2001-09-28 2004-06-22 Meshnetworks, Inc. System and method for enabling a node in an ad-hoc packet-switched wireless communications network to route packets based on packet content
US6757762B1 (en) 1999-10-29 2004-06-29 Unisys Corporation Multi-mode processor bus bridge
US20040143842A1 (en) * 2003-01-13 2004-07-22 Avinash Joshi System and method for achieving continuous connectivity to an access point or gateway in a wireless network following an on-demand routing protocol, and to perform smooth handoff of mobile terminals between fixed terminals in the network
US6768730B1 (en) 2001-10-11 2004-07-27 Meshnetworks, Inc. System and method for efficiently performing two-way ranging to determine the location of a wireless node in a communications network
US6771666B2 (en) 2002-03-15 2004-08-03 Meshnetworks, Inc. System and method for trans-medium address resolution on an ad-hoc network with at least one highly disconnected medium having multiple access points to other media
US20040179667A1 (en) * 2003-03-14 2004-09-16 Meshnetworks, Inc. System and method for analyzing the precision of geo-location services in a wireless network terminal
US20040246926A1 (en) * 2003-06-06 2004-12-09 Meshnetworks, Inc. System and method for identifying the floor number where a firefighter in need of help is located using received signal strength indicator and signal propagation time
US20040246975A1 (en) * 2003-06-06 2004-12-09 Meshnetworks, Inc. System and method to improve the overall performance of a wireless communication network
US20040246935A1 (en) * 2003-06-06 2004-12-09 Meshnetworks, Inc. System and method for characterizing the quality of a link in a wireless network
US20040252643A1 (en) * 2003-06-05 2004-12-16 Meshnetworks, Inc. System and method to improve the network performance of a wireless communications network by finding an optimal route between a source and a destination
US20040252630A1 (en) * 2003-06-05 2004-12-16 Meshnetworks, Inc. System and method for determining synchronization point in OFDM modems for accurate time of flight measurement
US20040259571A1 (en) * 2003-06-05 2004-12-23 Meshnetworks, Inc. System and method for determining location of a device in a wireless communication network
US20040258040A1 (en) * 2003-06-05 2004-12-23 Meshnetworks, Inc. System and method to maximize channel utilization in a multi-channel wireless communiction network
US6873839B2 (en) 2000-11-13 2005-03-29 Meshnetworks, Inc. Prioritized-routing for an ad-hoc, peer-to-peer, mobile radio access system
US20050114564A1 (en) * 2003-11-25 2005-05-26 Zohar Bogin Stream under-run/over-run recovery
US6904021B2 (en) 2002-03-15 2005-06-07 Meshnetworks, Inc. System and method for providing adaptive control of transmit power and data rate in an ad-hoc communication network
US20050143843A1 (en) * 2003-11-25 2005-06-30 Zohar Bogin Command pacing
US20050174474A1 (en) * 2004-02-05 2005-08-11 Konica Minolta Photo Imaging, Inc. Image-taking apparatus
US20050186966A1 (en) * 2003-03-13 2005-08-25 Meshnetworks, Inc. Real-time system and method for improving the accuracy of the computed location of mobile subscribers in a wireless ad-hoc network using a low speed central processing unit
US6937602B2 (en) 2001-10-23 2005-08-30 Meshnetworks, Inc. System and method for providing a congestion optimized address resolution protocol for wireless ad-hoc networks
US6970444B2 (en) 2002-05-13 2005-11-29 Meshnetworks, Inc. System and method for self propagating information in ad-hoc peer-to-peer networks
US6982982B1 (en) 2001-10-23 2006-01-03 Meshnetworks, Inc. System and method for providing a congestion optimized address resolution protocol for wireless ad-hoc networks
US6987795B1 (en) 2002-04-08 2006-01-17 Meshnetworks, Inc. System and method for selecting spreading codes based on multipath delay profile estimation for wireless transceivers in a communication network
US20060077938A1 (en) * 2004-10-07 2006-04-13 Meshnetworks, Inc. System and method for creating a spectrum agile wireless multi-hopping network
US7046962B1 (en) 2002-07-18 2006-05-16 Meshnetworks, Inc. System and method for improving the quality of range measurement based upon historical data
US7047328B1 (en) * 2001-07-13 2006-05-16 Legerity, Inc. Method and apparatus for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers
US7058018B1 (en) 2002-03-06 2006-06-06 Meshnetworks, Inc. System and method for using per-packet receive signal strength indication and transmit power levels to compute path loss for a link for use in layer II routing in a wireless communication network
US7072618B1 (en) 2001-12-21 2006-07-04 Meshnetworks, Inc. Adaptive threshold selection system and method for detection of a signal in the presence of interference
US7075890B2 (en) 2003-06-06 2006-07-11 Meshnetworks, Inc. System and method to provide fairness and service differentation in ad-hoc networks
US7106707B1 (en) 2001-12-20 2006-09-12 Meshnetworks, Inc. System and method for performing code and frequency channel selection for combined CDMA/FDMA spread spectrum communication systems
US7107498B1 (en) 2002-04-16 2006-09-12 Methnetworks, Inc. System and method for identifying and maintaining reliable infrastructure links using bit error rate data in an ad-hoc communication network
US7106703B1 (en) 2002-05-28 2006-09-12 Meshnetworks, Inc. System and method for controlling pipeline delays by adjusting the power levels at which nodes in an ad-hoc network transmit data packets
US7136587B1 (en) 2001-11-15 2006-11-14 Meshnetworks, Inc. System and method for providing simulated hardware-in-the-loop testing of wireless communications networks
US7181214B1 (en) 2001-11-13 2007-02-20 Meshnetworks, Inc. System and method for determining the measure of mobility of a subscriber device in an ad-hoc wireless network with fixed wireless routers and wide area network (WAN) access points
US7180875B1 (en) 2001-12-20 2007-02-20 Meshnetworks, Inc. System and method for performing macro-diversity selection and distribution of routes for routing data packets in Ad-Hoc networks
US7190672B1 (en) 2001-12-19 2007-03-13 Meshnetworks, Inc. System and method for using destination-directed spreading codes in a multi-channel metropolitan area wireless communications network
US7200149B1 (en) 2002-04-12 2007-04-03 Meshnetworks, Inc. System and method for identifying potential hidden node problems in multi-hop wireless ad-hoc networks for the purpose of avoiding such potentially problem nodes in route selection
US7215638B1 (en) 2002-06-19 2007-05-08 Meshnetworks, Inc. System and method to provide 911 access in voice over internet protocol systems without compromising network security
US7221686B1 (en) 2001-11-30 2007-05-22 Meshnetworks, Inc. System and method for computing the signal propagation time and the clock correction for mobile stations in a wireless network
US7280545B1 (en) 2001-12-20 2007-10-09 Nagle Darragh J Complex adaptive routing system and method for a nodal communication network
US7284268B2 (en) 2002-05-16 2007-10-16 Meshnetworks, Inc. System and method for a routing device to securely share network data with a host utilizing a hardware firewall
US7346716B2 (en) 2003-11-25 2008-03-18 Intel Corporation Tracking progress of data streamer
US20090307473A1 (en) * 2008-06-09 2009-12-10 Emulex Design & Manufacturing Corporation Method for adopting sequential processing from a parallel processing architecture
US7697420B1 (en) 2002-04-15 2010-04-13 Meshnetworks, Inc. System and method for leveraging network topology for enhanced security
US7796570B1 (en) 2002-07-12 2010-09-14 Meshnetworks, Inc. Method for sparse table accounting and dissemination from a mobile subscriber device in a wireless mobile ad-hoc network
US20110004719A1 (en) * 2008-06-19 2011-01-06 Nokia Corporation Memory Element
KR101018080B1 (ko) 2009-11-26 2011-03-02 주식회사 케피코 디엠에이를 사용한 임베디드 시스템의 메모리 데이터 수집 방법
US20170040051A1 (en) * 2015-08-03 2017-02-09 Intel Corporation Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode
US10268602B2 (en) * 2016-09-29 2019-04-23 Micron Technology, Inc. System and method for individual addressing

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571675A (en) * 1984-01-03 1986-02-18 Texas Instruments Incorporated Microprocessor device with integrated auto-loaded timer
US4577313A (en) * 1984-06-04 1986-03-18 Sy Kian Bon K Routing mechanism with encapsulated FCS for a multi-ring local area network
US4777591A (en) * 1984-01-03 1988-10-11 Texas Instruments Incorporated Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data communications systems
US5191657A (en) * 1989-11-09 1993-03-02 Ast Research, Inc. Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus
US5396602A (en) * 1993-05-28 1995-03-07 International Business Machines Corp. Arbitration logic for multiple bus computer system
US5446869A (en) * 1993-12-30 1995-08-29 International Business Machines Corporation Configuration and RAM/ROM control of PCI extension card residing on MCA adapter card
US5448558A (en) * 1994-04-05 1995-09-05 International Business Machines Corporation Method and apparatus for managing packet FIFOS
US5450551A (en) * 1993-05-28 1995-09-12 International Business Machines Corporation System direct memory access (DMA) support logic for PCI based computer system
US5471590A (en) * 1994-01-28 1995-11-28 Compaq Computer Corp. Bus master arbitration circuitry having improved prioritization
US5495569A (en) * 1994-12-30 1996-02-27 Compaq Computer Corp. Circuit for ensuring that a local interrupt controller in a microprocessor is powered up active
US5515513A (en) * 1991-04-08 1996-05-07 Digital Equipment Corporation Disposition filtering of messages using a single address and protocol table bridge
US5524235A (en) * 1994-10-14 1996-06-04 Compaq Computer Corporation System for arbitrating access to memory with dynamic priority assignment
US5542053A (en) * 1994-11-30 1996-07-30 International Business Machines Corporation Bridge interface between two buses of a computer system with a direct memory access controller programmed by a scatter/gather programmer
US5557758A (en) * 1994-11-30 1996-09-17 International Business Machines Corporation Bridge between two buses of a computer system that determines the location of memory or accesses from bus masters on one of the buses
US5559968A (en) * 1995-03-03 1996-09-24 Compaq Computer Corporation Non-conforming PCI bus master timing compensation circuit
US5642489A (en) * 1994-12-19 1997-06-24 International Business Machines Corporation Bridge between two buses of a computer system with a direct memory access controller with accessible registers to support power management

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571675A (en) * 1984-01-03 1986-02-18 Texas Instruments Incorporated Microprocessor device with integrated auto-loaded timer
US4777591A (en) * 1984-01-03 1988-10-11 Texas Instruments Incorporated Microprocessor with integrated CPU, RAM, timer, and bus arbiter for data communications systems
US4577313A (en) * 1984-06-04 1986-03-18 Sy Kian Bon K Routing mechanism with encapsulated FCS for a multi-ring local area network
US5191657A (en) * 1989-11-09 1993-03-02 Ast Research, Inc. Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus
US5515513A (en) * 1991-04-08 1996-05-07 Digital Equipment Corporation Disposition filtering of messages using a single address and protocol table bridge
US5396602A (en) * 1993-05-28 1995-03-07 International Business Machines Corp. Arbitration logic for multiple bus computer system
US5450551A (en) * 1993-05-28 1995-09-12 International Business Machines Corporation System direct memory access (DMA) support logic for PCI based computer system
US5446869A (en) * 1993-12-30 1995-08-29 International Business Machines Corporation Configuration and RAM/ROM control of PCI extension card residing on MCA adapter card
US5471590A (en) * 1994-01-28 1995-11-28 Compaq Computer Corp. Bus master arbitration circuitry having improved prioritization
US5448558A (en) * 1994-04-05 1995-09-05 International Business Machines Corporation Method and apparatus for managing packet FIFOS
US5524235A (en) * 1994-10-14 1996-06-04 Compaq Computer Corporation System for arbitrating access to memory with dynamic priority assignment
US5542053A (en) * 1994-11-30 1996-07-30 International Business Machines Corporation Bridge interface between two buses of a computer system with a direct memory access controller programmed by a scatter/gather programmer
US5557758A (en) * 1994-11-30 1996-09-17 International Business Machines Corporation Bridge between two buses of a computer system that determines the location of memory or accesses from bus masters on one of the buses
US5642489A (en) * 1994-12-19 1997-06-24 International Business Machines Corporation Bridge between two buses of a computer system with a direct memory access controller with accessible registers to support power management
US5495569A (en) * 1994-12-30 1996-02-27 Compaq Computer Corp. Circuit for ensuring that a local interrupt controller in a microprocessor is powered up active
US5559968A (en) * 1995-03-03 1996-09-24 Compaq Computer Corporation Non-conforming PCI bus master timing compensation circuit

Cited By (155)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6131133A (en) * 1997-08-02 2000-10-10 U.S. Philips Corporation Data exchange interface that directly transmits control signals either to a microprocessor or a D.M.A. controller via a first and second control line respectively
US6412027B1 (en) * 1998-02-11 2002-06-25 Globespanvirata, Inc. Direct memory access controller having on-board arbitration circuitry
US6138183A (en) * 1998-05-06 2000-10-24 Ess Technolgoy Inc. Transparent direct memory access
US20030018844A1 (en) * 1998-05-07 2003-01-23 Kazuhito Akiyama Data processing device having a plurality of state-machine parts
US6807601B2 (en) * 1998-05-07 2004-10-19 Ricoh Company, Ltd Data processing device having a plurality of state-machine parts
US6757762B1 (en) 1999-10-29 2004-06-29 Unisys Corporation Multi-mode processor bus bridge
US6915356B1 (en) 1999-12-07 2005-07-05 Advanced Micro Devices, Inc. Register addresses optimum access
WO2001042913A1 (en) * 1999-12-07 2001-06-14 Advanced Micro Devices, Inc. Register arrangement for optimum access
US20020038393A1 (en) * 2000-09-08 2002-03-28 Kumar Ganapathy Method and apparatus for distributed direct memory access for systems on chip
US8719465B2 (en) 2000-09-08 2014-05-06 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
US20050125572A1 (en) * 2000-09-08 2005-06-09 Kumar Ganapathy Distributed direct memory access for systems on chip
US6874039B2 (en) 2000-09-08 2005-03-29 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
US7155541B2 (en) 2000-09-08 2006-12-26 Intel Corporation Tables with direct memory access descriptor lists for distributed direct memory access
US20050216613A1 (en) * 2000-09-08 2005-09-29 Kumar Ganapathy Tables with direct memory access descriptor lists for distributed direct memory access
US7464197B2 (en) 2000-09-08 2008-12-09 Intel Corporation Distributed direct memory access for systems on chip
US7970961B2 (en) 2000-09-08 2011-06-28 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
US8386665B2 (en) 2000-09-08 2013-02-26 Intel Corporation Method and apparatus for distributed direct memory access for systems on chip
US7266104B2 (en) 2000-11-08 2007-09-04 Meshnetworks, Inc. Time division protocol for an AD-HOC, peer-to-peer radio network having coordinating channel access to shared parallel data channels with separate reservation channel
US7133391B2 (en) 2000-11-08 2006-11-07 Meshnetworks, Inc. Time division protocol for an ad-hoc, peer-to-peer radio network having coordinating channel access to shared parallel data channels with separate reservation channel
US20030142638A1 (en) * 2000-11-08 2003-07-31 Belcea John M. Time division protocol for an ad-hoc, peer-to-peer radio network having coordinating channel access to shared parallel data channels with separate reservation channel
US7197016B2 (en) 2000-11-08 2007-03-27 Meshnetworks, Inc. Time division protocol for an ad-hoc, peer-to-peer radio network having coordinating channel access to shared parallel data channels with separate reservation channel
US7212504B2 (en) 2000-11-08 2007-05-01 Meshnetworks, Inc. Time division protocol for an ad-hoc, peer-to-peer radio network having coordinating channel access to shared parallel data channels with separate reservation channel
US6807165B2 (en) 2000-11-08 2004-10-19 Meshnetworks, Inc. Time division protocol for an ad-hoc, peer-to-peer radio network having coordinating channel access to shared parallel data channels with separate reservation channel
US7796573B2 (en) 2000-11-08 2010-09-14 Meshnetworks, Inc. Terminal operating within an ad-hoc, peer-to-peer radio network
US20080013497A1 (en) * 2000-11-08 2008-01-17 Motorola, Inc. Terminal operating within an ad-hoc, peer-to-peer radio network
US7079509B2 (en) 2000-11-08 2006-07-18 Meshnetworks, Inc. Time division protocol for an ad-hoc, peer-to-peer radio network having coordinating channel access to shared parallel data channels with separate reservation channel
US7099296B2 (en) 2000-11-08 2006-08-29 Meshnetworks, Inc. Time division protocol for an ad-hoc, peer-to-peer radio network having coordinating channel access to shared parallel data channels with separate reservation channel
US7072650B2 (en) 2000-11-13 2006-07-04 Meshnetworks, Inc. Ad hoc peer-to-peer mobile radio access system interfaced to the PSTN and cellular networks
US6873839B2 (en) 2000-11-13 2005-03-29 Meshnetworks, Inc. Prioritized-routing for an ad-hoc, peer-to-peer, mobile radio access system
US20020058502A1 (en) * 2000-11-13 2002-05-16 Peter Stanforth Ad hoc peer-to-peer mobile radio access system interfaced to the PSTN and cellular networks
US20060233184A1 (en) * 2000-11-13 2006-10-19 Meshnetworks, Inc. Ad-hoc peer-to-peer mobile radio access system interfaced to the PSTN and cellular networks
US8180351B2 (en) 2000-11-13 2012-05-15 Meshnetworks, Inc. Ad-hoc peer-to-peer mobile radio access system interfaced to the PSTN and cellular networks
US6904275B2 (en) 2000-11-13 2005-06-07 Meshnetworks, Inc. Prioritized-routing for an ad-hoc, peer-to-peer, mobile radio access system
US6961575B2 (en) 2000-11-13 2005-11-01 Meshnetworks, Inc. Ad Hoc peer-to-peer mobile radio access system interfaced to the PSTN and cellular networks
US20020116555A1 (en) * 2000-12-20 2002-08-22 Jeffrey Somers Method and apparatus for efficiently moving portions of a memory block
US6948010B2 (en) * 2000-12-20 2005-09-20 Stratus Technologies Bermuda Ltd. Method and apparatus for efficiently moving portions of a memory block
US20030040316A1 (en) * 2001-03-22 2003-02-27 Peter Stanforth Prioritized-routing for an ad-hoc, peer-to-peer, mobile radio access system based on battery-power levels and type of service
US7151769B2 (en) 2001-03-22 2006-12-19 Meshnetworks, Inc. Prioritized-routing for an ad-hoc, peer-to-peer, mobile radio access system based on battery-power levels and type of service
US20020191573A1 (en) * 2001-06-14 2002-12-19 Whitehill Eric A. Embedded routing algorithms under the internet protocol routing layer of a software architecture protocol stack in a mobile Ad-Hoc network
US7756041B2 (en) 2001-06-14 2010-07-13 Meshnetworks, Inc. Embedded routing algorithms under the internet protocol routing layer of a software architecture protocol stack in a mobile Ad-Hoc network
US7047328B1 (en) * 2001-07-13 2006-05-16 Legerity, Inc. Method and apparatus for accessing memories having a time-variant response over a PCI bus by using two-stage DMA transfers
US20030035437A1 (en) * 2001-08-15 2003-02-20 Masood Garahi Movable access points and repeaters for minimizing coverage and capacity constraints in a wireless communications network and a method for using the same
US7206294B2 (en) 2001-08-15 2007-04-17 Meshnetworks, Inc. Movable access points and repeaters for minimizing coverage and capacity constraints in a wireless communications network and a method for using the same
US20030091010A1 (en) * 2001-08-15 2003-05-15 Masood Garahi Movable access points and repeaters for minimizing coverage and capacity constraints in a wireless communications network and a method for using the same
US7072323B2 (en) 2001-08-15 2006-07-04 Meshnetworks, Inc. System and method for performing soft handoff in a wireless data network
US20030091012A1 (en) * 2001-08-15 2003-05-15 Barker Charles R. System and method for providing an addressing and proxy scheme for facilitating mobility of wireless nodes between wired access points on a core network of a communications network
US7349380B2 (en) 2001-08-15 2008-03-25 Meshnetworks, Inc. System and method for providing an addressing and proxy scheme for facilitating mobility of wireless nodes between wired access points on a core network of a communications network
US20030091011A1 (en) * 2001-08-15 2003-05-15 Roberts Robin U. System and method for performing soft handoff in a wireless data network
US7149197B2 (en) 2001-08-15 2006-12-12 Meshnetworks, Inc. Movable access points and repeaters for minimizing coverage and capacity constraints in a wireless communications network and a method for using the same
US20030060202A1 (en) * 2001-08-28 2003-03-27 Roberts Robin U. System and method for enabling a radio node to selectably function as a router in a wireless communications network
US7613458B2 (en) 2001-08-28 2009-11-03 Meshnetworks, Inc. System and method for enabling a radio node to selectably function as a router in a wireless communications network
US20030043790A1 (en) * 2001-09-06 2003-03-06 Philip Gutierrez Multi-master bus architecture for system -on-chip designs
US7145903B2 (en) 2001-09-06 2006-12-05 Meshnetworks, Inc. Multi-master bus architecture for system-on-chip designs
US7152125B2 (en) * 2001-09-25 2006-12-19 Intel Corporation Dynamic master/slave configuration for multiple expansion modules
US20030058886A1 (en) * 2001-09-25 2003-03-27 Stanforth Peter J. System and method employing algorithms and protocols for optimizing carrier sense multiple access (CSMA) protocols in wireless networks
US7587717B2 (en) 2001-09-25 2009-09-08 Intel Corporation Dynamic master/slave configuration for multiple expansion modules
US7280555B2 (en) 2001-09-25 2007-10-09 Meshnetworks, Inc. System and method employing algorithms and protocols for optimizing carrier sense multiple access (CSMA) protocols in wireless networks
US20030061428A1 (en) * 2001-09-25 2003-03-27 Intel Corporation Dynamic master/slave configuration for multiple expansion modules
US20070088884A1 (en) * 2001-09-25 2007-04-19 Intel Corporation Dynamic master/slave configuration for multiple expansion cards
US6754188B1 (en) 2001-09-28 2004-06-22 Meshnetworks, Inc. System and method for enabling a node in an ad-hoc packet-switched wireless communications network to route packets based on packet content
US6768730B1 (en) 2001-10-11 2004-07-27 Meshnetworks, Inc. System and method for efficiently performing two-way ranging to determine the location of a wireless node in a communications network
US6937602B2 (en) 2001-10-23 2005-08-30 Meshnetworks, Inc. System and method for providing a congestion optimized address resolution protocol for wireless ad-hoc networks
US6982982B1 (en) 2001-10-23 2006-01-03 Meshnetworks, Inc. System and method for providing a congestion optimized address resolution protocol for wireless ad-hoc networks
US7181214B1 (en) 2001-11-13 2007-02-20 Meshnetworks, Inc. System and method for determining the measure of mobility of a subscriber device in an ad-hoc wireless network with fixed wireless routers and wide area network (WAN) access points
US7136587B1 (en) 2001-11-15 2006-11-14 Meshnetworks, Inc. System and method for providing simulated hardware-in-the-loop testing of wireless communications networks
US6728545B1 (en) 2001-11-16 2004-04-27 Meshnetworks, Inc. System and method for computing the location of a mobile terminal in a wireless communications network
US7221686B1 (en) 2001-11-30 2007-05-22 Meshnetworks, Inc. System and method for computing the signal propagation time and the clock correction for mobile stations in a wireless network
US7190672B1 (en) 2001-12-19 2007-03-13 Meshnetworks, Inc. System and method for using destination-directed spreading codes in a multi-channel metropolitan area wireless communications network
US7106707B1 (en) 2001-12-20 2006-09-12 Meshnetworks, Inc. System and method for performing code and frequency channel selection for combined CDMA/FDMA spread spectrum communication systems
US7280545B1 (en) 2001-12-20 2007-10-09 Nagle Darragh J Complex adaptive routing system and method for a nodal communication network
US7180875B1 (en) 2001-12-20 2007-02-20 Meshnetworks, Inc. System and method for performing macro-diversity selection and distribution of routes for routing data packets in Ad-Hoc networks
US7072618B1 (en) 2001-12-21 2006-07-04 Meshnetworks, Inc. Adaptive threshold selection system and method for detection of a signal in the presence of interference
US6674790B1 (en) 2002-01-24 2004-01-06 Meshnetworks, Inc. System and method employing concatenated spreading sequences to provide data modulated spread signals having increased data rates with extended multi-path delay spread
US7058018B1 (en) 2002-03-06 2006-06-06 Meshnetworks, Inc. System and method for using per-packet receive signal strength indication and transmit power levels to compute path loss for a link for use in layer II routing in a wireless communication network
US6617990B1 (en) 2002-03-06 2003-09-09 Meshnetworks Digital-to-analog converter using pseudo-random sequences and a method for using the same
US6728232B2 (en) 2002-03-15 2004-04-27 Meshnetworks, Inc. System and method for auto-configuration and discovery of IP to MAC address mapping and gateway presence in wireless peer-to-peer ad-hoc routing networks
US6771666B2 (en) 2002-03-15 2004-08-03 Meshnetworks, Inc. System and method for trans-medium address resolution on an ad-hoc network with at least one highly disconnected medium having multiple access points to other media
US6904021B2 (en) 2002-03-15 2005-06-07 Meshnetworks, Inc. System and method for providing adaptive control of transmit power and data rate in an ad-hoc communication network
US6987795B1 (en) 2002-04-08 2006-01-17 Meshnetworks, Inc. System and method for selecting spreading codes based on multipath delay profile estimation for wireless transceivers in a communication network
US7200149B1 (en) 2002-04-12 2007-04-03 Meshnetworks, Inc. System and method for identifying potential hidden node problems in multi-hop wireless ad-hoc networks for the purpose of avoiding such potentially problem nodes in route selection
US7697420B1 (en) 2002-04-15 2010-04-13 Meshnetworks, Inc. System and method for leveraging network topology for enhanced security
US6580981B1 (en) 2002-04-16 2003-06-17 Meshnetworks, Inc. System and method for providing wireless telematics store and forward messaging for peer-to-peer and peer-to-peer-to-infrastructure a communication network
US7107498B1 (en) 2002-04-16 2006-09-12 Methnetworks, Inc. System and method for identifying and maintaining reliable infrastructure links using bit error rate data in an ad-hoc communication network
US7142524B2 (en) 2002-05-01 2006-11-28 Meshnetworks, Inc. System and method for using an ad-hoc routing algorithm based on activity detection in an ad-hoc network
US20040081166A1 (en) * 2002-05-01 2004-04-29 Stanforth Peter J. System and method for using an ad-hoc routing algorithm based on activity detection in an ad-hoc network
US6970444B2 (en) 2002-05-13 2005-11-29 Meshnetworks, Inc. System and method for self propagating information in ad-hoc peer-to-peer networks
US20030214921A1 (en) * 2002-05-16 2003-11-20 Alapuranen Pertti O. System and method for performing multiple network routing and provisioning in overlapping wireless deployments
US7284268B2 (en) 2002-05-16 2007-10-16 Meshnetworks, Inc. System and method for a routing device to securely share network data with a host utilizing a hardware firewall
US7016306B2 (en) 2002-05-16 2006-03-21 Meshnetworks, Inc. System and method for performing multiple network routing and provisioning in overlapping wireless deployments
US20040082341A1 (en) * 2002-05-17 2004-04-29 Stanforth Peter J. System and method for determining relative positioning in ad-hoc networks
US7167715B2 (en) 2002-05-17 2007-01-23 Meshnetworks, Inc. System and method for determining relative positioning in AD-HOC networks
US7106703B1 (en) 2002-05-28 2006-09-12 Meshnetworks, Inc. System and method for controlling pipeline delays by adjusting the power levels at which nodes in an ad-hoc network transmit data packets
US7054126B2 (en) 2002-06-05 2006-05-30 Meshnetworks, Inc. System and method for improving the accuracy of time of arrival measurements in a wireless ad-hoc communications network
US7610027B2 (en) 2002-06-05 2009-10-27 Meshnetworks, Inc. Method and apparatus to maintain specification absorption rate at a wireless node
US6687259B2 (en) 2002-06-05 2004-02-03 Meshnetworks, Inc. ARQ MAC for ad-hoc communication networks and a method for using the same
US20030228875A1 (en) * 2002-06-05 2003-12-11 Alapuranen Pertti O. MAC protocol with duty-cycle limitation for portable devices in a wireless Ad-Hoc communication network and a method for using the same
US20030227895A1 (en) * 2002-06-05 2003-12-11 Strutt Guenael T. System and method for improving the accuracy of time of arrival measurements in a wireless ad-hoc communications network
US6744766B2 (en) 2002-06-05 2004-06-01 Meshnetworks, Inc. Hybrid ARQ for a wireless Ad-Hoc network and a method for using the same
US20030227934A1 (en) * 2002-06-11 2003-12-11 White Eric D. System and method for multicast media access using broadcast transmissions with multiple acknowledgements in an Ad-Hoc communications network
US7215638B1 (en) 2002-06-19 2007-05-08 Meshnetworks, Inc. System and method to provide 911 access in voice over internet protocol systems without compromising network security
US20040005902A1 (en) * 2002-07-05 2004-01-08 Belcea John M. System and method for correcting the clock drift and maintaining the synchronization of low quality clocks in wireless networks
US7072432B2 (en) 2002-07-05 2006-07-04 Meshnetworks, Inc. System and method for correcting the clock drift and maintaining the synchronization of low quality clocks in wireless networks
US7796570B1 (en) 2002-07-12 2010-09-14 Meshnetworks, Inc. Method for sparse table accounting and dissemination from a mobile subscriber device in a wireless mobile ad-hoc network
US7046962B1 (en) 2002-07-18 2006-05-16 Meshnetworks, Inc. System and method for improving the quality of range measurement based upon historical data
US20040028017A1 (en) * 2002-07-29 2004-02-12 Whitehill Eric A. System and method for determining physical location of a node in a wireless network during an authentication check of the node
US20060153075A1 (en) * 2002-07-29 2006-07-13 Whitehill Eric A System and method for determining physical location of a node in a wireless network during an authentication check of the node
US8325653B2 (en) 2002-07-29 2012-12-04 Meshnetworks, Inc. System and method for restricting network access to one or more nodes in a wireless communications network
US7042867B2 (en) 2002-07-29 2006-05-09 Meshnetworks, Inc. System and method for determining physical location of a node in a wireless network during an authentication check of the node
US20040143842A1 (en) * 2003-01-13 2004-07-22 Avinash Joshi System and method for achieving continuous connectivity to an access point or gateway in a wireless network following an on-demand routing protocol, and to perform smooth handoff of mobile terminals between fixed terminals in the network
US7522537B2 (en) 2003-01-13 2009-04-21 Meshnetworks, Inc. System and method for providing connectivity between an intelligent access point and nodes in a wireless network
US7076259B2 (en) 2003-03-13 2006-07-11 Meshnetworks, Inc. Real-time system and method for improving the accuracy of the computed location of mobile subscribers in a wireless ad-hoc network using a low speed central processing unit
US20050186966A1 (en) * 2003-03-13 2005-08-25 Meshnetworks, Inc. Real-time system and method for improving the accuracy of the computed location of mobile subscribers in a wireless ad-hoc network using a low speed central processing unit
US7171220B2 (en) 2003-03-14 2007-01-30 Meshnetworks, Inc. System and method for analyzing the precision of geo-location services in a wireless network terminal
US20040179667A1 (en) * 2003-03-14 2004-09-16 Meshnetworks, Inc. System and method for analyzing the precision of geo-location services in a wireless network terminal
US20040258040A1 (en) * 2003-06-05 2004-12-23 Meshnetworks, Inc. System and method to maximize channel utilization in a multi-channel wireless communiction network
US7215966B2 (en) 2003-06-05 2007-05-08 Meshnetworks, Inc. System and method for determining location of a device in a wireless communication network
US20040252643A1 (en) * 2003-06-05 2004-12-16 Meshnetworks, Inc. System and method to improve the network performance of a wireless communications network by finding an optimal route between a source and a destination
US20040252630A1 (en) * 2003-06-05 2004-12-16 Meshnetworks, Inc. System and method for determining synchronization point in OFDM modems for accurate time of flight measurement
US7280483B2 (en) 2003-06-05 2007-10-09 Meshnetworks, Inc. System and method to improve the network performance of a wireless communications network by finding an optimal route between a source and a destination
US7116632B2 (en) 2003-06-05 2006-10-03 Meshnetworks, Inc. System and method for determining synchronization point in OFDM modems for accurate time of flight measurement
US7734809B2 (en) 2003-06-05 2010-06-08 Meshnetworks, Inc. System and method to maximize channel utilization in a multi-channel wireless communication network
US20040259571A1 (en) * 2003-06-05 2004-12-23 Meshnetworks, Inc. System and method for determining location of a device in a wireless communication network
US7075890B2 (en) 2003-06-06 2006-07-11 Meshnetworks, Inc. System and method to provide fairness and service differentation in ad-hoc networks
US20040246935A1 (en) * 2003-06-06 2004-12-09 Meshnetworks, Inc. System and method for characterizing the quality of a link in a wireless network
US7061925B2 (en) 2003-06-06 2006-06-13 Meshnetworks, Inc. System and method for decreasing latency in locating routes between nodes in a wireless communication network
US7412241B2 (en) 2003-06-06 2008-08-12 Meshnetworks, Inc. Method to provide a measure of link reliability to a routing protocol in an ad hoc wireless network
US20040246986A1 (en) * 2003-06-06 2004-12-09 Meshnetworks, Inc. MAC protocol for accurately computing the position of wireless devices inside buildings
US20040260808A1 (en) * 2003-06-06 2004-12-23 Meshnetworks, Inc. Method to provide a measure of link reliability to a routing protocol in an ad hoc wireless network
US20040258013A1 (en) * 2003-06-06 2004-12-23 Meshnetworks, Inc. System and method for accurately computing the position of wireless devices inside high-rise buildings
US7558818B2 (en) 2003-06-06 2009-07-07 Meshnetworks, Inc. System and method for characterizing the quality of a link in a wireless network
US20040246926A1 (en) * 2003-06-06 2004-12-09 Meshnetworks, Inc. System and method for identifying the floor number where a firefighter in need of help is located using received signal strength indicator and signal propagation time
US20040246975A1 (en) * 2003-06-06 2004-12-09 Meshnetworks, Inc. System and method to improve the overall performance of a wireless communication network
US7203497B2 (en) 2003-06-06 2007-04-10 Meshnetworks, Inc. System and method for accurately computing the position of wireless devices inside high-rise buildings
US7349441B2 (en) 2003-06-06 2008-03-25 Meshnetworks, Inc. Method for optimizing communication within a wireless network
US7126951B2 (en) 2003-06-06 2006-10-24 Meshnetworks, Inc. System and method for identifying the floor number where a firefighter in need of help is located using received signal strength indicator and signal propagation time
US7694044B2 (en) 2003-11-25 2010-04-06 Intel Corporation Stream under-run/over-run recovery
US20050143843A1 (en) * 2003-11-25 2005-06-30 Zohar Bogin Command pacing
US7370125B2 (en) 2003-11-25 2008-05-06 Intel Corporation Stream under-run/over-run recovery
US20050114564A1 (en) * 2003-11-25 2005-05-26 Zohar Bogin Stream under-run/over-run recovery
US7346716B2 (en) 2003-11-25 2008-03-18 Intel Corporation Tracking progress of data streamer
US20080250183A1 (en) * 2003-11-25 2008-10-09 Zohar Bogin Stream under-run/over-run recovery
US20050174474A1 (en) * 2004-02-05 2005-08-11 Konica Minolta Photo Imaging, Inc. Image-taking apparatus
US20060077938A1 (en) * 2004-10-07 2006-04-13 Meshnetworks, Inc. System and method for creating a spectrum agile wireless multi-hopping network
US7167463B2 (en) 2004-10-07 2007-01-23 Meshnetworks, Inc. System and method for creating a spectrum agile wireless multi-hopping network
US20090307473A1 (en) * 2008-06-09 2009-12-10 Emulex Design & Manufacturing Corporation Method for adopting sequential processing from a parallel processing architecture
US8145805B2 (en) * 2008-06-09 2012-03-27 Emulex Design & Manufacturing Corporation Method for re-sequencing commands and data between a master and target devices utilizing parallel processing
US20110004719A1 (en) * 2008-06-19 2011-01-06 Nokia Corporation Memory Element
KR101018080B1 (ko) 2009-11-26 2011-03-02 주식회사 케피코 디엠에이를 사용한 임베디드 시스템의 메모리 데이터 수집 방법
US20170040051A1 (en) * 2015-08-03 2017-02-09 Intel Corporation Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode
US10127968B2 (en) * 2015-08-03 2018-11-13 Intel Corporation Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode
US10679690B2 (en) 2015-08-03 2020-06-09 Intel Corporation Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode
US10268602B2 (en) * 2016-09-29 2019-04-23 Micron Technology, Inc. System and method for individual addressing
US10339071B2 (en) 2016-09-29 2019-07-02 Micron Technology, Inc. System and method for individual addressing
US10521366B2 (en) * 2016-09-29 2019-12-31 Micron Technology, Inc. System and method for individual addressing
US10789182B2 (en) 2016-09-29 2020-09-29 Micron Technology, Inc. System and method for individual addressing

Also Published As

Publication number Publication date
KR100271336B1 (ko) 2000-11-01
KR19990063741A (ko) 1999-07-26
HK1011228A1 (en) 1999-07-09
GB2319642B (en) 2000-09-13
GB2319642A (en) 1998-05-27
BR9610950A (pt) 1999-01-12
AU7112596A (en) 1997-04-30
WO1997014100A1 (en) 1997-04-17
DE19681574T1 (de) 1998-10-01
GB9803706D0 (en) 1998-04-15

Similar Documents

Publication Publication Date Title
US5805842A (en) Apparatus, system and method for supporting DMA transfers on a multiplexed bus
US6226700B1 (en) Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devices
US5450551A (en) System direct memory access (DMA) support logic for PCI based computer system
USRE37980E1 (en) Bus-to-bus bridge in computer system, with fast burst memory range
JP4008987B2 (ja) バス通信システム及びバス調停方法並びにデータ転送方法
US5664197A (en) Method and apparatus for handling bus master channel and direct memory access (DMA) channel access requests at an I/O controller
US7752374B2 (en) Method and apparatus for host messaging unit for peripheral component interconnect busmaster devices
US5774681A (en) Method and apparatus for controlling a response timing of a target ready signal on a PCI bridge
US6070215A (en) Computer system with improved transition to low power operation
US7047348B2 (en) Method and architecture for accessing hardware devices in computer system and chipset thereof
WO1996000940A1 (en) Pci to isa interrupt protocol converter and selection mechanism
US6101566A (en) Computer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devices
US6397279B1 (en) Smart retry system that reduces wasted bus transactions associated with master retries
EP0820021B1 (en) Apparatus and method for positively and subtractively decoding addresses on a bus
EP0820018A2 (en) Circuit for handling distributed arbitration in a computer system having multiple arbiters
JPH10293744A (ja) Ｐｃｉバス・システム
US6122679A (en) Master DMA controller with re-map engine for only spawning programming cycles to slave DMA controllers which do not match current programming cycle
US5951667A (en) Method and apparatus for connecting expansion buses to a peripheral component interconnect bus
US6078742A (en) Hardware emulation
US5968144A (en) System for supporting DMA I/O device using PCI bus and PCI-PCI bridge comprising programmable DMA controller for request arbitration and storing data transfer information
US5890002A (en) System and method for bus master emulation
US5878239A (en) Method and apparatus for processing a target retry from a PCI target device to an ISA master devise using a PCI/ISA bridge
US5850529A (en) Method and apparatus for detecting a resource lock on a PCI bus
US6757798B2 (en) Method and apparatus for arbitrating deferred read requests
US5857081A (en) Method and apparatus for controlling a master abort in a computer system

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

CC Certificate of correction
FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

SULP Surcharge for late payment

Year of fee payment: 11