US5519708A - System for converting synchronous time-division signals into asynchronous time-division data packets - Google Patents

System for converting synchronous time-division signals into asynchronous time-division data packets Download PDF

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Publication number
US5519708A
US5519708A US08/427,782 US42778295A US5519708A US 5519708 A US5519708 A US 5519708A US 42778295 A US42778295 A US 42778295A US 5519708 A US5519708 A US 5519708A
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United States
Prior art keywords
division
time
storage means
ram
data packets
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Expired - Fee Related
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US08/427,782
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English (en)
Inventor
Hendrik Van Der Veen
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US Philips Corp
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US Philips Corp
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Priority to US08/427,782 priority Critical patent/US5519708A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/16—Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
    • H04J3/1605—Fixed allocated frame structures
    • H04J3/1611—Synchronous digital hierarchy [SDH] or SONET
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5614—User Network Interface
    • H04L2012/5618—Bridges, gateways [GW] or interworking units [IWU]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L2012/5672—Multiplexing, e.g. coding, scrambling

Definitions

  • the invention relates to a system for processing synchronous time-division (STD) signals as well as asynchronous time-division (ATD) data packets, in which input signals spread over various input channels are converted into output signals spread over various output channels, in response to control means the input signals being temporarily stored in a first-in first-out (FIFO) memory and read out therefrom, and are also temporarily stored in a RAM and read out therefrom as well.
  • STD synchronous time-division
  • ATD synchronous time-division
  • a drawback of the prior-art system is that it is only suitable for converting asynchronous data packets into synchronous multiplex signals, whereas there is also a need for a system converting synchronous time-division signals into asynchronous time-division data packets.
  • the system according to the invention is thereto characterized, in that the input signals are the STD signals, the output signals are the ATD packets and the STD signals are first stored in the RAM before being placed in the FIFO.
  • FIG. 1 shows a system for converting time-division synchronous signals into asynchronous time-division data packets
  • FIG. 2 shows a memory layout of the RAM in the system shown in FIG. 1.
  • FIG. 1 shows a system 100 for converting a synchronous time-division signal referenced STD signal (Synchronous Time-Division), into an asynchronous data packet referenced ATD packet (Asynchronous Time-Division).
  • STD signal Synchronous Time-Division
  • ATD packet Asynchronous Time-Division
  • the incoming STD signal is transported to a RAM 102 in response to a RAM input control 107 through a series-to-parallel converter 101. If the latter is not explicitly included, synchronizing means 108 derive time synchronizing information from the incoming channels.
  • the series-to-parallel converter 101 has for its function to carry out the data processing at a lower rate.
  • Various input channels for example, in the form of multiplex time-division channels, can be connected to the system shown in FIG. 1.
  • the RAM 102 has such a memory structure that a column is reserved for each incoming channel, with each column comprising a number of rows for individual information packets.
  • a RAM-to-FIFO control 106 In response to a RAM-to-FIFO control 106 the information is taken from the columns of the RAM 102 to a FIFO memory 103 (First In First Out), where a header identifying the destination of the data packet is affixed to the data packet.
  • the FIFO 103 has an independent access for read and write operations and is used for the desired rate adjustments.
  • the RAM input control 107 knows about the organization of the input channels, for example, 32 channels of 64 kbit/s and, on the basis thereof, fills the RAM memory locations. This should be effected in such a way that the complete data packets for the different output channels are finished is effected in a time-division mode. In that case the data transfer control is loaded as uniformly as possible and the formation of data packets for the different output channels is delayed the least possible.
  • the RAM-m-FIFO control 106 comprises, for example, a table of headings for each column in the RAM.
  • the table of headings itself is controlled by a PD control 109 which includes an error detection section.
  • the header comprises, for example, a transfer bit denoting whether a specific output channel is to be supplied with a data packet.
  • the RAM-to-FIFO control 106 continuously scans the rows in the RAM 102. If a sufficient number of rows in a column are filled for assembling a data packet, the RAM-to-FIFO control 106 places a header in the FIFO 103 and adds in the fastest way possible the relevant contents of the column to the header, unless the transfer bit of the header has a zero value.
  • a signal is sent to a FIFO output control 105, which in its turn transfers the data packets located in the FIFO 103 to a parallel-to-series converter 104 and then to the ATD output channels while maintaining the desired synchronization.
  • each column comprises as many rows as is strictly necessary for storing a data packet.
  • each column in the RAM comprises exactly N-byte memory locations. If the write pointer, whose position is generated by the RAM input control 107, is at the end of these N memory locations, a data packet is full.
  • the RAM-FIFO control 106 then receives from the RAM input control 107 the associated column address for addressing the desired output channel, and transfers the data packet concerned to the FIFO 103. This transfer is to be effected as soon as possible, but is to be completed before the next information byte for the associated column arrives.
  • FIG. 2 shows, for example, that packet (x+1) of column 4 is full (the write pointer has a value N). This packet is to be transported to the FIFO before the arrival of the next information byte for column 4.
  • the synchronous signals are shifted per column row (e.g. 1 row) in the memory matrix of rows and columns as is shown in FIG. 2. If in the first column C1, for example, the filling of a data packet is commenced in the zero th row RO, this is commenced in the i th column C1 on the (i-1)st row R(i-1).
  • the row-shifted data packet storage in the RAM ensures that the data packets become available efficiency divided over time.
  • An extremely efficient data packet transfer to the FIFO may therefore be effected.
  • a minimum-size FIFO may also suffice, because the transfer is effected uniformly divided over time.
  • Each filled data packet will be presented to the FIFO with the same (minimum) time delay.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
US08/427,782 1991-06-21 1995-04-17 System for converting synchronous time-division signals into asynchronous time-division data packets Expired - Fee Related US5519708A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US08/427,782 US5519708A (en) 1991-06-21 1995-04-17 System for converting synchronous time-division signals into asynchronous time-division data packets

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP91201596 1991-06-21
EP91201596 1991-06-21
US90145792A 1992-06-19 1992-06-19
US08/427,782 US5519708A (en) 1991-06-21 1995-04-17 System for converting synchronous time-division signals into asynchronous time-division data packets

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US90145792A Continuation 1991-06-21 1992-06-19

Publications (1)

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US5519708A true US5519708A (en) 1996-05-21

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US08/427,782 Expired - Fee Related US5519708A (en) 1991-06-21 1995-04-17 System for converting synchronous time-division signals into asynchronous time-division data packets

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US (1) US5519708A (fr)
EP (1) EP0519563A3 (fr)
JP (1) JPH05191441A (fr)
CA (1) CA2071583C (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715249A (en) * 1994-11-07 1998-02-03 Nec Corporation ATM cell format converter using cell start indicator for generating output cell pulse
US5825768A (en) * 1996-09-30 1998-10-20 Motorola, Inc. Interface for an asymmetric digital subscriber line transceiver
US6393021B1 (en) 1997-02-14 2002-05-21 Advanced Micro Devices, Inc. Integrated multiport switch having shared data receive FIFO structure
US20030227906A1 (en) * 2002-06-05 2003-12-11 Litchfield Communications, Inc. Fair multiplexing of transport signals across a packet-oriented network
US20040047367A1 (en) * 2002-09-05 2004-03-11 Litchfield Communications, Inc. Method and system for optimizing the size of a variable buffer
US20050149764A1 (en) * 2001-09-21 2005-07-07 Microsoft Corporation Systems and methods for managing network connectivity for mobile users

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU667004B2 (en) * 1993-03-31 1996-02-29 Nec Corporation Cell processing system having first and second processing units capable of outputting first and second processed signals at the same time
FR2721463A1 (fr) * 1994-06-17 1995-12-22 Trt Telecom Radio Electr Système de transmission comportant au moins deux liaisons pour relier un émetteur et un récepteur et récepteur convenant à un tel système.
US5479398A (en) * 1994-12-22 1995-12-26 At&T Corp Digital data concentrator

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4603416A (en) * 1982-12-29 1986-07-29 Michel Servel (Time division multiplex) switching system for routing trains of constant length data packets
US4612636A (en) * 1984-12-31 1986-09-16 Northern Telecom Limited Multiple channel depacketizer
US4862451A (en) * 1987-01-28 1989-08-29 International Business Machines Corporation Method and apparatus for switching information between channels for synchronous information traffic and asynchronous data packets
US4884264A (en) * 1987-07-24 1989-11-28 Etat Francais Represente Par Le Ministre Des Ptt (Centre National D'etudes Des Telecommunications Hybrid time multiplex switching system with optimized buffer memory
US5083269A (en) * 1989-01-10 1992-01-21 Kabushiki Kaisha Toshiba Buffer device suitable for asynchronous transfer mode communication
US5144619A (en) * 1991-01-11 1992-09-01 Northern Telecom Limited Common memory switch for routing data signals comprising ATM and STM cells
US5212686A (en) * 1988-10-06 1993-05-18 Plessey Overseas Limited Asynchronous time division switching arrangement and a method of operating same
US5224099A (en) * 1991-05-17 1993-06-29 Stratacom, Inc. Circuitry and method for fair queuing and servicing cell traffic using hopcounts and traffic classes

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2553609B1 (fr) * 1983-10-14 1985-12-27 Chomel Denis Systeme de multiplexage numerique temporel asynchrone a bus distribue
FR2589656B1 (fr) * 1985-07-03 1987-12-11 Servel Michel Procede et dispositif de conversion de multitrame de canaux numeriques en multitrame de paquets
US4734907A (en) * 1985-09-06 1988-03-29 Washington University Broadcast packet switching network
FR2655794A1 (fr) * 1989-12-13 1991-06-14 Cit Alcatel Convertisseur synchrone-asynchrone.

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4603416A (en) * 1982-12-29 1986-07-29 Michel Servel (Time division multiplex) switching system for routing trains of constant length data packets
US4612636A (en) * 1984-12-31 1986-09-16 Northern Telecom Limited Multiple channel depacketizer
US4862451A (en) * 1987-01-28 1989-08-29 International Business Machines Corporation Method and apparatus for switching information between channels for synchronous information traffic and asynchronous data packets
US4884264A (en) * 1987-07-24 1989-11-28 Etat Francais Represente Par Le Ministre Des Ptt (Centre National D'etudes Des Telecommunications Hybrid time multiplex switching system with optimized buffer memory
US5212686A (en) * 1988-10-06 1993-05-18 Plessey Overseas Limited Asynchronous time division switching arrangement and a method of operating same
US5083269A (en) * 1989-01-10 1992-01-21 Kabushiki Kaisha Toshiba Buffer device suitable for asynchronous transfer mode communication
US5144619A (en) * 1991-01-11 1992-09-01 Northern Telecom Limited Common memory switch for routing data signals comprising ATM and STM cells
US5224099A (en) * 1991-05-17 1993-06-29 Stratacom, Inc. Circuitry and method for fair queuing and servicing cell traffic using hopcounts and traffic classes

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5715249A (en) * 1994-11-07 1998-02-03 Nec Corporation ATM cell format converter using cell start indicator for generating output cell pulse
US5825768A (en) * 1996-09-30 1998-10-20 Motorola, Inc. Interface for an asymmetric digital subscriber line transceiver
US6393021B1 (en) 1997-02-14 2002-05-21 Advanced Micro Devices, Inc. Integrated multiport switch having shared data receive FIFO structure
US20050149764A1 (en) * 2001-09-21 2005-07-07 Microsoft Corporation Systems and methods for managing network connectivity for mobile users
US20030227906A1 (en) * 2002-06-05 2003-12-11 Litchfield Communications, Inc. Fair multiplexing of transport signals across a packet-oriented network
US20030227943A1 (en) * 2002-06-05 2003-12-11 Litchfield Communications, Inc. Communicating synchronous TDM signals across a packet-oriented network
US20030227913A1 (en) * 2002-06-05 2003-12-11 Litchfield Communications, Inc. Adaptive timing recovery of synchronous transport signals
US20040047367A1 (en) * 2002-09-05 2004-03-11 Litchfield Communications, Inc. Method and system for optimizing the size of a variable buffer

Also Published As

Publication number Publication date
EP0519563A3 (en) 1997-08-27
EP0519563A2 (fr) 1992-12-23
CA2071583A1 (fr) 1992-12-22
JPH05191441A (ja) 1993-07-30
CA2071583C (fr) 2003-06-03

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FP Expired due to failure to pay maintenance fee

Effective date: 19961030

FPAY Fee payment

Year of fee payment: 4

LAPS Lapse for failure to pay maintenance fees
FP Expired due to failure to pay maintenance fee

Effective date: 20040521

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362