US5472886A - Structure of and method for manufacturing an LED - Google Patents
Structure of and method for manufacturing an LED Download PDFInfo
- Publication number
- US5472886A US5472886A US08/364,368 US36436894A US5472886A US 5472886 A US5472886 A US 5472886A US 36436894 A US36436894 A US 36436894A US 5472886 A US5472886 A US 5472886A
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- contact
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- 238000000034 method Methods 0.000 title claims description 27
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 239000010931 gold Substances 0.000 claims description 13
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 9
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 4
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- BMYNFMYTOJXKLE-UHFFFAOYSA-N 3-azaniumyl-2-hydroxypropanoate Chemical compound NCC(O)C(O)=O BMYNFMYTOJXKLE-UHFFFAOYSA-N 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 claims description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 abstract description 18
- 239000000463 material Substances 0.000 abstract description 14
- 230000003287 optical effect Effects 0.000 description 21
- 239000000835 fiber Substances 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 238000009736 wetting Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000013307 optical fiber Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 3
- 229910001258 titanium gold Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 1
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
Definitions
- This invention relates generally to the structure and manufacture of a double heterostructure light emitting diode or laser diode (collectively abbreviated "LED") for use in devices where the LED must be aligned with great accuracy to the device carrier, as, for example, in the optical communications field. More particularly, the invention relates to an LED with both the p-contact and the n-contact on the same side, permitting the solder bonding pads to be configured so that precise solder bump self alignment is achieved without shorting between the pads and without the need for bonding wires.
- LED double heterostructure light emitting diode or laser diode
- LEDs used as light sources in fiber optic communications must be precisely aligned to the device carrier, so that the optical emission from the device may be accurately directed into an optical communications fiber.
- LEDs with output suitable for use in optical communications have bonding pads on opposite surfaces. This structure has presented difficulties in mass producing optical devices that require alignment between LED and fiber, as explained in the Detailed Description below.
- the present invention provides a structure of and a method for manufacturing an LED with an optical output suitable for the communications field, and with both bonding pads on the same surface.
- the LED is preferably both aligned and electrically connected to the device carrier during a single solder bonding operation. Because both contacts of the LED are on the same side of the device, the need for a wire bond to the LED is eliminated.
- a groove on the p-surface of the device extends through the p-material into the n-material below.
- the groove allows an n-contact, which is deposited in part on the p-surface, to make electrical contact with the n-material below.
- a p-contact is deposited on another part of the p-surface.
- Metal bonding pads over metallic film areas in contact with the p- and n-contacts allow a mechanically stable, reliable and low stress solder joint to the base member.
- Non-wetting surfaces surround the metal bonding pads, preventing shorts from forming between the bonding pads or across the p-n junction during solder reflow, thereby making solder attachment of the LED to the base member a reliable batch process.
- the LED device is manufactured from a standard double-heterostructure wafer, such as indium gallium arsenide phosphide/indium phosphide (InGaAsP/InP).
- a metal n-contact is applied which extends from the p-surface down one side of the groove to the n-material exposed at the bottom of the groove.
- a p-contact then is formed on the p-surface on the other side of the groove.
- a non-wetting dielectric is deposited on all surfaces surrounding the contacts, and openings are formed in the dielectric exposing the contacts.
- All surfaces are then covered with a metal film, and thick metal bonding pads are formed over the areas of the p-and n-contacts. Finally, the metal film left exposed after adding the bonding pads is removed, leaving non-wetting dielectric material surrounding the bonding pads.
- FIG. 1 is a cross sectional view of a known double heterostructure InGaAsP/InP LED
- FIG. 2 is a schematic side elevational view in cross section of an LED according to the present invention.
- FIG. 3 is a bottom plan view of the LED according to the present invention.
- FIG. 4 is a perspective view of a silicon wafer prepared as a device carrier for an optical package that will contain an LED according to the present invention
- FIGS. 5A to 5G are schematic side elevational views in cross section of an LED in successive steps of a manufacturing process according to the present invention.
- a currently available LED 20 having a double heterostructure wafer configuration typically has a p-contact 1 and an n-contact 2 located on opposite surfaces of the device, most often the top and bottom.
- a bonding pad 3 on the bottom surface is soldered to a contact 4 on the device carrier.
- the LED is aligned by surface tension forces present in the molten solder, a technique referred to as solder bump self alignment.
- a bonding wire 5 must be used to connect the top, or n-contact 2 to a second contact 6 on the device carrier 10. Attaching the bonding wire adds the expense of a second operation, and may compromise the reliability and positioning accuracy of the device mounting operation. Further, the surrounding components in an optical package containing the LED of FIG. 1 must be designed to provide additional clearance for the bonding wire.
- FIGS. 2-4 One embodiment of an LED according to the present invention, and an exemplary implementation of the device, will be explained with reference to FIGS. 2-4.
- LED 50 comprises a wafer 51 having standard double heterostructure InGaAsP/InP construction.
- This construction was used in the embodiment fabricated by the inventors and is known in the art as being appropriate for use in LEDs used in optical communications devices.
- Other wafer constructions having appropriate optical output characteristics such as another construction having an indium phosphide substrate, or a construction having a gallium arsenide (GaAs) substrate, could also be used.
- Wafer 51 has at least one n-layer 52 comprising an n-type substrate and at least one p-layer 53 comprising a p-type film. In an installed LED of the invention, the n-layer 52 is above the p-layer 53; that is, the n-layer is closest to the optical fiber in an installed device, and the p-layer is closest to the chip carrier.
- a groove 60 extends upwardly from a p-surface 61 on the underside of the p-layer 53, completely through the p-layer, and to a depth sufficient to penetrate a portion of the n-layer 52.
- a metallic n-contact 62 extends from the n-layer 52 at the bottom 60c of the groove 60, along a first side 60a of the groove 60, to the p-surface 61.
- a p-contact 63 depends from the p-surface 61 adjacent a second side 60b of the groove 60.
- Each of the p- and n-contacts are in electrical contact with separate thin metallic film areas 80a and 80b. Attached to these film areas are thick metal bonding pads 120 and 121. The bonding pads are shaped so as to optimize the locating forces created by solder bump surface tension, while providing a sufficient heat sink during LED operation.
- Dielectric film 65 covers all surfaces surrounding the metal bonding pads 120 and 121 on the underside of LED 50, including areas of the p-surface 61 surrounding the bonding pads, and the sides and base of the groove 60.
- the dielectric film is non-wetting as to solder, and therefore prevents shorting of the device during the solder melt operation.
- the LED further may have an integral lens 66 on n-surface 67, which increases the amount of light coupled into an optical fiber during device operation.
- the active light-emitting region of the diode lies at the p-n junction area 69 between the p-contact 63 and the lens 66.
- the portion of the p-layer 53 adjacent the first side 60a of groove 60 is electrically isolated from the active region of the diode, but serves as a spacer so that the bonding pad 121 is maintained at the same level as bonding pad 120.
- FIG. 3 is a bottom plan view of an exemplary LED 50 according to the invention.
- the overall width 501 of the LED in this example is 0.250 mm, and the overall length 502 is 0.375 mm.
- An n- bonding pad 120 and a p- bonding pad 121 are disposed on opposite sides of groove 60.
- the two bonding pads 120 and 121 are of similar dimensions, having a width 510 of 0.125 mm and a length 511 of 0.200 mm.
- the use of two bonding pads as shown in FIG. 3 improves the efficiency of solder bump self alignment. Furthermore, while the bonding pads shown in FIG. 3 have sharp corners, rounded corners could be used to improve solder wetting characteristics.
- a typical chip carrier configuration for building an optical package using the LED of the invention is shown schematically in FIG. 4.
- a silicon wafer 600 forms the base material of the chip carrier.
- Two bond pad sites 601 are formed on the silicon wafer 600.
- the bond pad sites have a length and width close to those of bonding pads 120 and 121 of the LED.
- Leads 602 electrically connect the bond pad sites 601 to the optical package circuitry.
- Mechanical alignment fiducials 610 in the silicon wafer 600 are precisely located with respect to the bond pad sites 601, and mate with similar fiducials provided in the associated optical components (not shown), such as a lens holder and an optical fiber ferrule. The optical components are thereby passively aligned to the LED during the optical package assembly operations.
- Steps in the process of manufacturing the above-described LED are related below with reference to FIGS. 5A-5G.
- fabrication of the LED begins with a standard double heterostructure InGaAsP/InP wafer 701, with layer thickness and composition suitable for the fabrication of LEDs.
- Other compositions suitable for communications applications, such as GaAs, will be apparent to those skilled in the art.
- the wafer 701 has at least one p-layer 53 and a p-surface 61, and at least one n-layer 52 and an n-surface 67.
- the wafer further comprises primary crystallographic planes, such as plane 707.
- a suitable chemical mask 706 is formed on the p-surface 61 of the wafer.
- the mask can be a dielectric mask, such as silicon dioxide or silicon nitride, or can be a photoresist mask that is chemically resistant to the chemical processes used in subsequent process steps.
- a stripe opening 708 is defined on the mask, parallel to primary crystallographic plane 707 of the wafer.
- a groove 60 is etched in the semiconductor wafer at the opening 708 in the chemical mask 706, as shown in FIG. 5B.
- the groove 60 is etched using either a wet chemical or a dry etching technique.
- the groove is etched to a depth sufficient to completely penetrate the p-layer 53 of the wafer, and to expose the n-layer 52.
- the groove is not, however, etched so deep as to mechanically weaken the final LED device or to result in poor step coverage or discontinuous films on the walls of the groove.
- a suitable etchant is composed of hydrobromic acid, hydrogen peroxide and water in a 5:1:20 volume ratio; however, one skilled in the art will recognize that other etchants suitable for this purpose can be formulated. Such etchants must not be reactive with the chemical mask 706.
- the chemical mask shown in FIG. 5B is removed and the underlying surfaces are cleaned, readying the wafer for the next step.
- n-contact 62 is then formed as shown in FIG. 5C, using photolithographic and deposition techniques known in the art.
- a suitable contact material is layered Au/Sn/Au which is subsequently alloyed by heat treatment, although other contact materials known in the art may be used.
- the n-contact 62 of this example is approximately 1-1.5 microns in total thickness.
- the n-contact 62 contacts the n-layer 52 at the base 60c of the groove, and forms a continuous film on the first side 60a of the groove 60 to the p-surface 61.
- the n-contact of this example extends across the p-surface adjacent the first side 60a of groove 60 to cover the area where bonding pad 122 will subsequently be applied. It is important that only the first side 60a, and not the second side 60b, of the groove 60 be covered with the n-contact metal in order to avoid short circuiting the device.
- a p-contact 63 is formed on the p-surface of the device opposite groove 60 from the n-contact.
- a suitable contact metal known in the art such as a AuBe film, is used.
- the contact is circular in plan view (not shown), being approximately 25 microns in diameter and 0.1 micron in thickness.
- the wafer 701 is then thinned by removing material from the n-surface 67 until the wafer is the desired thickness.
- a lens 66 shown in FIG. 5D, can be integrally formed on the n-surface 67 aligned with the p-contact 63, to increase the amount of light coupled into an optical fiber.
- the lens is formed using the known technique of reactive-ion etching.
- An anti-reflective film 70 can be added to the lens.
- a dielectric film 65 is deposited over all features on the p side of the wafer, including the p-surface 61, the p-contact 63, the bottom 60c and walls 60a, 60b of the groove 60, and the n-contact 62.
- the dielectric film 65 isolates these features and seals the groove surfaces.
- the dielectric film used in the embodiment fabricated by the inventors was silicon nitride deposited to a thickness of approximately 0.2 microns. Other appropriate materials known in the art, such as silicon dioxide, can alternatively be used.
- Openings 710, 711 are then defined in the dielectric film as shown in FIG. 5F, using standard photolithographic and etching processes.
- the diameter of opening 710 is slightly smaller than the diameter of the p-contact 63 and is centered over it, exposing the center portion of the p-contact.
- Opening 711 is defined in the position to be occupied by the bonding pad 121, as shown in FIG. 5G, and exposes a portion of the n-contact 62 located on the p-surface 61.
- a metal film 80 shown in FIG. 5G, is then deposited over the dielectric film 65 and the openings 710, 711.
- a layered TiAu metal film comprising approximately 0.2 microns titanium and 0.5 microns gold is used. This composition provides good adhesion and conductivity for bonding pads 120, 121 to be subsequently applied, and the TiAu film can be partially etched later in the processing sequence to isolate the n- and p-contacts 62, 63.
- footprints for bonding pads 120, 121 centered on the n- and p-contacts 62, 62 are defined on the metal film 80, and thick gold bonding pads 120, 121 are formed on these footprints.
- the pads are formed by electroplating to a thickness of 5 microns. Other methods, such as evaporation techniques, and other thicknesses in the range of about 4 to 10 microns, could also be used.
- the gold bonding pads 120, 121 must be thick enough to serve both as a heat sink under the p-contact 63 as a cushion between the solder bond and the semiconductor after die attachment, but not so thick as to cause wafer breakage and waste gold.
- metal film 80 remaining exposed around the gold bonding pads 120, 121 is then removed to again expose the dielectric film 65. As shown in FIG. 2, metal film portion 80a below bonding pad 120 and metal film portion 80b below bonding pad 121 are left intact. Since the remaining dielectric film 65 will not be wetted by the solder during die attachment, this step will ensure that shorting will not take place across the bonding pads 120, 121 during solder bond.
- the finished wafer is then diced using standard processes, such as scribe-and-break, forming the finished LED device 50 as shown in FIG. 2.
- the LED chip is now ready to be bonded to a carrier board.
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Abstract
Description
Claims (14)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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US08/364,368 US5472886A (en) | 1994-12-27 | 1994-12-27 | Structure of and method for manufacturing an LED |
EP95308969A EP0720241A3 (en) | 1994-12-27 | 1995-12-11 | Structure of and method for manufacturing an LED |
JP33626795A JPH08236808A (en) | 1994-12-27 | 1995-12-25 | Led and its manufacture |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/364,368 US5472886A (en) | 1994-12-27 | 1994-12-27 | Structure of and method for manufacturing an LED |
Publications (1)
Publication Number | Publication Date |
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US5472886A true US5472886A (en) | 1995-12-05 |
Family
ID=23434207
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US08/364,368 Expired - Lifetime US5472886A (en) | 1994-12-27 | 1994-12-27 | Structure of and method for manufacturing an LED |
Country Status (3)
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US (1) | US5472886A (en) |
EP (1) | EP0720241A3 (en) |
JP (1) | JPH08236808A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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WO1998027590A1 (en) * | 1996-12-19 | 1998-06-25 | Telefonaktiebolaget Lm Ericsson (Publ) | Bumps in grooves for elastic positioning |
US5892248A (en) * | 1996-05-13 | 1999-04-06 | Trw Inc. | Double photoresist layer self-aligned heterojuction bipolar transistor |
US20050047718A1 (en) * | 2003-08-01 | 2005-03-03 | Seiko Epson Corporation | Optical device and method for manufacturing the same, optical module, and optical transmission device |
US20110220925A1 (en) * | 2010-03-10 | 2011-09-15 | Micron Technology, Inc. | Light emitting diode wafer-level package with self-aligning features |
CN103456856A (en) * | 2013-09-05 | 2013-12-18 | 深圳市智讯达光电科技有限公司 | Inversion LED chip and ohmic contact electrode structure of inversion LED chip |
US20140227833A1 (en) * | 2012-04-30 | 2014-08-14 | Apple Inc. | Sensor array package |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10294493A (en) * | 1997-02-21 | 1998-11-04 | Toshiba Corp | Semiconductor light-emitting device |
EP0905797B1 (en) * | 1997-09-29 | 2010-02-10 | OSRAM Opto Semiconductors GmbH | Semiconductor light source and method of fabrication |
DE19945131A1 (en) * | 1999-09-21 | 2001-04-12 | Osram Opto Semiconductors Gmbh | Electronic component and coating agent |
DE19963550B4 (en) * | 1999-12-22 | 2004-05-06 | Epigap Optoelektronik Gmbh | Bipolar illumination source from a self-bundling semiconductor body contacted on one side |
BRPI0714507A8 (en) | 2006-07-14 | 2015-10-06 | Koninklijke Philips Electronics Nv | ASSEMBLY STRUCTURE, AND METHOD FOR ASSEMBLY OF AN ELECTRO-OPTIC COMPONENT IN ALIGNMENT WITH AN OPTICAL ELEMENT |
DE102007022947B4 (en) * | 2007-04-26 | 2022-05-05 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelectronic semiconductor body and method for producing such |
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1994
- 1994-12-27 US US08/364,368 patent/US5472886A/en not_active Expired - Lifetime
-
1995
- 1995-12-11 EP EP95308969A patent/EP0720241A3/en not_active Withdrawn
- 1995-12-25 JP JP33626795A patent/JPH08236808A/en active Pending
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US5892248A (en) * | 1996-05-13 | 1999-04-06 | Trw Inc. | Double photoresist layer self-aligned heterojuction bipolar transistor |
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US6188138B1 (en) | 1996-12-19 | 2001-02-13 | Telefonaktiebolaget Lm Ericsson (Pub) | Bumps in grooves for elastic positioning |
US7483603B2 (en) | 2003-08-01 | 2009-01-27 | Seiko Epson Corporation | Optical device and method for manufacturing the same, optical module, and optical transmission device |
US7155090B2 (en) * | 2003-08-01 | 2006-12-26 | Seiko Epson Corporation | Optical device and method for manufacturing the same, optical module, and optical transmission device |
US20060291778A1 (en) * | 2003-08-01 | 2006-12-28 | Seiko Epson Corporation | Optical device and method for manufacturing the same, optical module, and optical transmission device |
US20050047718A1 (en) * | 2003-08-01 | 2005-03-03 | Seiko Epson Corporation | Optical device and method for manufacturing the same, optical module, and optical transmission device |
US20110220925A1 (en) * | 2010-03-10 | 2011-09-15 | Micron Technology, Inc. | Light emitting diode wafer-level package with self-aligning features |
US8441020B2 (en) | 2010-03-10 | 2013-05-14 | Micron Technology, Inc. | Light emitting diode wafer-level package with self-aligning features |
US8878205B2 (en) | 2010-03-10 | 2014-11-04 | Micron Technology, Inc. | Light emitting diode wafer-level package with self-aligning features |
US20140227833A1 (en) * | 2012-04-30 | 2014-08-14 | Apple Inc. | Sensor array package |
US9018091B2 (en) * | 2012-04-30 | 2015-04-28 | Apple Inc. | Methods for forming a sensor array package |
US9402316B2 (en) | 2012-04-30 | 2016-07-26 | Apple Inc. | Methods for forming a sensor array package |
CN103456856A (en) * | 2013-09-05 | 2013-12-18 | 深圳市智讯达光电科技有限公司 | Inversion LED chip and ohmic contact electrode structure of inversion LED chip |
Also Published As
Publication number | Publication date |
---|---|
EP0720241A2 (en) | 1996-07-03 |
JPH08236808A (en) | 1996-09-13 |
EP0720241A3 (en) | 1998-10-21 |
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