US5400277A - Semiconductor on insulator static random access meory cell utilizing polysilicon resistors formed in trenches - Google Patents
Semiconductor on insulator static random access meory cell utilizing polysilicon resistors formed in trenches Download PDFInfo
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- US5400277A US5400277A US08/145,450 US14545093A US5400277A US 5400277 A US5400277 A US 5400277A US 14545093 A US14545093 A US 14545093A US 5400277 A US5400277 A US 5400277A
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- 229920005591 polysilicon Polymers 0.000 title claims abstract description 25
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- 230000003068 static effect Effects 0.000 title description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
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- 239000011810 insulating material Substances 0.000 claims 2
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- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
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- 229910052697 platinum Inorganic materials 0.000 description 1
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- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/15—Static random access memory [SRAM] devices comprising a resistor load element
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
Definitions
- This is invention relates generally to static random access memory (SRAM) cells and particularly to semiconductor on insulator (SOI SRAM cells which utilize polysilicon resistors formed in trenches.
- SRAM static random access memory
- SOI SRAM semiconductor on insulator
- CMOS complementary metal oxide silicon
- SRAM cells are constructed using either a four transistor or a six transistor implementation.
- the four transistor configuration uses a polysilicon load element which functions as a passive resistor.
- the load resistors are generally situated horizontally over the active cell elements to reduce the cell area. See, for example, T. Ohzone, T. Hirao, K. Tsuji, S. Horiuchi, and S. Takayanagi, A 2Kx8-Bit Static MOS RAM with a New Memory Cell Structure, IEEE J. Solid-State Circuits, vol. SC-15, pp. 201-205, April. 1980.
- the four transistor configuration has the advantage of a small size.
- the four transistor configuration has the disadvantage of requiring a more complex process than a six transistor implementation.
- the four transistor configuration also has the disadvantage of a higher standby current.
- the six transistor configuration has the advantage that it can easily be implemented in the standard ASIC CMOS process.
- SRAM cells which utilize the six transistor configuration are larger than SRAM cells which utilize the four transistor configuration and are more susceptible to latch up. Latch up occurs when the four-layer NPNP CMOS structure acts like a silicon controlled rectifier (SCR) and switches from a high impedance state to a low impedance state in response to a triggering signal. This latch up is detrimental and sometimes destructive to the integrated circuit.
- SCR silicon controlled rectifier
- a resistor is connected to the source/drain of a transistor and used as a load element of a memory cell.
- a trench is formed which extends from a top of a wafer through an isolation region to a silicon base or substrate.
- the wafer is a bonded semiconductor on insulator (SOI) wafer.
- SOI semiconductor on insulator
- the silicon base of the wafer is located below the isolation region.
- a resistive layer of material is formed in the trench. The resistive layer extends from the top of the wafer through the isolation region of the wafer and is electrically connected to the silicon base of the wafer.
- the resistor is connected to other circuitry on the wafer, for example, by implanting into the wafer atoms of a first conductivity type into a region immediately adjacent to the resistive layer of material in the trench.
- the resistive layer of material is deposited polysilicon.
- the formation of the resistor may be done by adding steps to the normal process flow of forming a transistor.
- a gate insulator region is formed on a wafer.
- a gate is formed on the gate insulator region.
- low doping concentration source/drain regions are implanted on both sides of the gate.
- a trench is formed on a first side of the gate. The trench extends from a top of the wafer through an isolation region of the wafer to a base of the wafer. The base of the wafer is located below the isolation region of the wafer.
- a resistive layer of material is formed in the trench.
- the resistive layer is, for example, deposited polysilicon.
- the resistive layer extends from the top of the wafer through the isolation region of the wafer and is electrically coupled to the base of the wafer. Construction of the transistor is completed by forming highly doped source/drain regions on the sides of the transistor. The source/drain region on the first side of the gate is in electrical contact with the resistive layer formed in the trench. In the preferred embodiment of the present invention, spacers are formed on both sides of the gate before implanting atoms to form the highly doped source/drain regions.
- the resistors described above can be used as load elements for a four transistor SRAM cell.
- the memory cell includes two load elements, a word line, a bit line, an inverted bit line, a ground line, a power line, a first transistor, a second transistor, a third transistor and a fourth transistor.
- the power line is connected to the silicon base of the wafer.
- the first transistor has a first end connected to the inverted bit line, a second end, and a gate connected to the word line.
- the second transistor has a first end, a second end connected to the bit line, and a gate connected to the word line.
- the third transistor has a first end connected to the second end of the first transistor, a second end connected to the ground line, and a gate connected to the first end of the second transistor.
- the fourth transistor has a first end connected to the first end of the second transistor, a second end connected to the ground line, and a gate connected to the second end of the first transistor.
- the first load element is connected between the second end of the first transistor and the silicon base of the wafer.
- the second load element is connected between the first end of the second transistor and the silicon base of the wafer.
- resistors in accordance with the preferred embodiment of the present invention as load elements in SRAM cells has several significant advantages over the prior art. For example, by using a silicon base as a voltage source allows for the elimination of a separate power bias line in the memory cell. The elimination of the power line in addition to the vertical orientation of the resistor allows reduction in the size of the SRAM cell. Also the preferred embodiment of the present invention eliminates the possibility of contamination of the polysilicon resistor from underlying oxides, as is possible in prior art SRAM cells where a polysilicon resistor is placed on top of an oxide region.
- FIG. 1 shows a schematic diagram of an SRAM cell in accordance with the preferred embodiment of the present invention.
- FIG. 2, FIG. 3, FIG. 4, FIG. 5 and FIG. 6 show processing steps to produce a semiconductor on insulator (SOI) SRAM cell which utilizes polysilicon resistors formed in trenches in accordance with the preferred embodiment of the present invention.
- SOI semiconductor on insulator
- FIG. 1 shows a schematic diagram of an SRAM cell according to the preferred embodiment of the present invention.
- the SRAM cell includes a transistor 64, a transistor 65, a transistor 66 and a transistor 67 connected as shown.
- Transistor 64, transistor 65, transistor 66 and transistor 67 are each NMOS transistors.
- a load resistor 68 and a load resistor 69 are used as load devices for the SRAM memory cell.
- a V cc bias voltage is placed on a V cc bias voltage line 70.
- the V cc bias voltage is, for example 5 volts.
- a V ss bias voltage is placed on a V ss bias voltage line 63.
- the V ss bias voltage is, for example 0 volts.
- the SRAM cell is accessed using a word line 62, a bit line 60 and an inverted bit line 61.
- the preferred embodiment of the present invention utilizes bonded semiconductor on silicon (SOI) wafer technology.
- SOI semiconductor on silicon
- the use of bonded wafers for SOI technology has overcome many of the difficulties encountered with silicon on sapphire technology and the use of SIMOX wafers. See, for example, Laura Peters, SOI Takes Over Where Silicon Leaves Off, Semiconductor International, March 1993, pp. 48-51; or, H. H. Hosack, Recent Progess in SOI Materials For the Next Generation of IC Technology, The Electrochemical Society Interface, Spring 1993, pp. 51-57. Bonded wafers for SOI processes are available, for example, from Hughes Danbury Optical Systems, Inc. Precision Materials Operations, having a business address of 100 Wooster Heights Road, Danbury, Conn. 06810-7589.
- FIG. 2, FIG. 3, FIG. 4, FIG. 5 and FIG. 6 show the additional processing steps integrated into a semiconductor on insulator (SOI) process for producing polysilicon SRAM cell load resistors in trenches, in accordance with the preferred embodiment of the present invention.
- SOI semiconductor on insulator
- FIG. 2, FIG. 3, FIG. 4, FIG. 5 and FIG. 6 illustrate the formation of transistor 64 and load resistance 68 shown in FIG. 1.
- a bonded wafer is shown to include a silicon base 10 of a first conductivity type, a silicon dioxide isolation layer 11 and a silicon layer 12 of a second conductivity type.
- the first conductivity type is n-type and the second conductivity type is p-type.
- a standard process flow may be used up to the point in the process shown in FIG. 2.
- a local oxidation of silicon (LOCOS) process or other process is used to form an insulating layer 9 of, for example, field oxide on silicon layer 12.
- LOCOS local oxidation of silicon
- a layer of pad oxide is thermally grown.
- a layer of Silicon Nitride is deposited.
- the Silicon Nitride is patterned and etched.
- Field oxide is grown on silicon layer 12 at places where the Silicon Nitride has been etched to expose silicon layer 12. The Silicon Nitride and pad oxide are then removed.
- gate 15 is the gate of transistor 64.
- gate 15 has a width which is approximately equal to 0.6 microns.
- Gate 15 may be made of polysilicon, for example, doped with n-type atoms at 10 20 atoms per cubic centimeter. The n-type atoms may be, for example, Phosphorus or Arsenic. Alternate to forming gate 15 entirely of polysilicon, a polycide may be used. The polycide gate may be formed as follows.
- a layer of polysilicon is deposited over the layer of gate oxide.
- the deposition may be a chemical vapor deposition (CVD).
- the polysilicon is doped using POCl 3 .
- an implant of Phosphorus or Arsenic atoms may be used.
- a metal layer is deposited on top of the polysilicon layer.
- a rapid thermal anneal (or other annealing process) is used to react the metal layer with the polysilicon layer.
- the metal-silicide layer may be formed, for example, using Titanium (Ti), Molybdenum (Mo), Chromium (Cr), Nickel (Ni), Platinum (Pt), Cobalt (Co), Tungsten (W) or Tantalum (Ta).
- Region 14 and region 34 act as lightly doped source/drain (LDD) regions for transistor 64.
- LDD lightly doped source/drain
- regions 14 and 34 are n - regions doped with Phosphorus at 10 18 atoms per cubic centimeter. Regions 14 and 34 each extend approximately 0.1 microns below the surface of silicon layer 12. A spacer oxide region 13 is then deposited to a thickness of, for example 3000 Angstroms.
- trenches are formed in which polysilicon resistors will be formed.
- a photoresist layer 16 is deposited over spacer oxide region 13.
- the photoresist is patterned leaving an opening where a trench will be etched.
- a trench 19 is formed by reactive ion etching (RIE) through spacer oxide region 13, silicon layer 12 and silicon dioxide isolation layer 11 to expose silicon base 10. The photoresist is then removed.
- RIE reactive ion etching
- a layer 22 of, for example, polysilicon is deposited.
- Layer 22 will be used to form load resistor 68.
- Layer 22 is for example, 0.1 micrometer thick.
- Layer 22 can be doped in-situ during deposition. Alternately, layer 22 can be doped after deposition, for example, by large tilt angle implants. Alternately, the polysilicon may be left undoped. The doping level will be determined by the memory cell and circuit standby current requirements.
- trench 19 is back-filled with an isolation material 21. Isolation material 21 is deposited in a layer which is thick enough to completely fill trench 19. For example, isolation material 21 is silicon dioxide.
- FIG. 5 An insulation region 24 of, for example silicon dioxide fills what was once trench 19.
- a spacer 31 and a spacer 32 are formed on either side of gate 15. Spacer 31 and spacer 32 each extend approximately 0.2 micrometers out from the bottom of gate 15.
- resistor 68 The processing steps for forming resistor 68 is complete. The remainder of the processing follows a standard CMOS flow. This includes implantation of the source/drain regions, such as n + region 44, n + region 45 and n + region 54 formed on either side of trench 19 and gate 15, as shown in FIG. 6. A layer 41 of, for example, silicon dioxide is placed over the circuit and filled trench 19, as shown in FIG. 6. Completion of the circuit includes patterning and etching of contact holes and metalization.
- CMOS flow This includes implantation of the source/drain regions, such as n + region 44, n + region 45 and n + region 54 formed on either side of trench 19 and gate 15, as shown in FIG. 6.
- a layer 41 of, for example, silicon dioxide is placed over the circuit and filled trench 19, as shown in FIG. 6.
- Completion of the circuit includes patterning and etching of contact holes and metalization.
- load resistors such as load resistor 68
- V cc bias voltage allows for the elimination of a separate V cc bias line within the memory cell.
- vertical orientation of the polysilicon resistor allows additional reduction in the size of the SRAM cell.
- the preferred embodiment of the present invention eliminates the possibility of contamination of the polysilicon resistor from underlying oxides, as is possible in prior art embodiments where a polysilicon resistor is placed on top of an oxide region.
- the SRAM cells utilized NMOS transistors.
- the conductivity types could be changed to form SRAM cells still within the contemplated purview of the present invention.
- the preferred embodiment utilizes SOI technology.
- the invention could also be implemented using wafers produced using Separation by Implantation of Oxygen (SIMOX) technology. Accordingly, the disclosure of the present invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.
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Abstract
Description
Claims (6)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US08/145,450 US5400277A (en) | 1993-10-29 | 1993-10-29 | Semiconductor on insulator static random access meory cell utilizing polysilicon resistors formed in trenches |
PCT/US1994/011175 WO1995012215A1 (en) | 1993-10-29 | 1994-10-03 | Semiconductor on insulator static random access memory cell utilizing polysilicon resistors formed in trenches |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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US08/145,450 US5400277A (en) | 1993-10-29 | 1993-10-29 | Semiconductor on insulator static random access meory cell utilizing polysilicon resistors formed in trenches |
Publications (1)
Publication Number | Publication Date |
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US5400277A true US5400277A (en) | 1995-03-21 |
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US08/145,450 Expired - Fee Related US5400277A (en) | 1993-10-29 | 1993-10-29 | Semiconductor on insulator static random access meory cell utilizing polysilicon resistors formed in trenches |
Country Status (2)
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US (1) | US5400277A (en) |
WO (1) | WO1995012215A1 (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996029738A1 (en) * | 1995-03-23 | 1996-09-26 | Micron Technology, Inc. | Integrated circuit resistor fabrication method |
US5578854A (en) * | 1995-08-11 | 1996-11-26 | International Business Machines Corporation | Vertical load resistor SRAM cell |
US5614738A (en) * | 1994-04-01 | 1997-03-25 | Fuji Electric Co., Ltd. | Insulated gate thyristor having a polysilicon resistor connected to its base |
US5770881A (en) * | 1996-09-12 | 1998-06-23 | International Business Machines Coproration | SOI FET design to reduce transient bipolar current |
US5852573A (en) * | 1997-10-08 | 1998-12-22 | Mosel Vitelic Inc. | Polyload sram memory cell with low stanby current |
US5959335A (en) * | 1998-09-23 | 1999-09-28 | International Business Machines Corporation | Device design for enhanced avalanche SOI CMOS |
US5981329A (en) * | 1995-12-06 | 1999-11-09 | Micron Technology, Inc. | SRAM cell employing substantially vertically elongated pull-up resistors and methods of making, and resistor constructions and methods of making |
US6057590A (en) * | 1997-08-23 | 2000-05-02 | Winbond Electronics Corp. | Structure of polysilicon load for static random access memory |
US6114730A (en) * | 1997-05-16 | 2000-09-05 | Texas Instruments Incorporated | Semiconductor device and its manufacturing method |
US6683345B1 (en) | 1999-12-20 | 2004-01-27 | International Business Machines, Corp. | Semiconductor device and method for making the device having an electrically modulated conduction channel |
US20070010078A1 (en) * | 2005-07-07 | 2007-01-11 | Micron Technology, Inc. | Methods of forming integrated circuitry and methods of forming local interconnects |
US20110062508A1 (en) * | 2009-09-15 | 2011-03-17 | Yoonmoon Park | Semiconductor device including resistor and method of fabricating the same |
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US20240063115A1 (en) * | 2022-08-19 | 2024-02-22 | Nanya Technology Corporation | Semiconductor structure having fuse below gate structure and method of manufacturing thereof |
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US4933739A (en) * | 1988-04-26 | 1990-06-12 | Eliyahou Harari | Trench resistor structures for compact semiconductor memory and logic devices |
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JPH06101547B2 (en) * | 1985-05-13 | 1994-12-12 | 株式会社日立製作所 | Semiconductor integrated circuit device and manufacturing method thereof |
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JPH04219974A (en) * | 1990-12-20 | 1992-08-11 | Matsushita Electron Corp | Static ram |
JP3108447B2 (en) * | 1991-03-08 | 2000-11-13 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
US5185535A (en) * | 1991-06-17 | 1993-02-09 | Hughes Aircraft Company | Control of backgate bias for low power high speed CMOS/SOI devices |
US5159430A (en) * | 1991-07-24 | 1992-10-27 | Micron Technology, Inc. | Vertically integrated oxygen-implanted polysilicon resistor |
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1993
- 1993-10-29 US US08/145,450 patent/US5400277A/en not_active Expired - Fee Related
-
1994
- 1994-10-03 WO PCT/US1994/011175 patent/WO1995012215A1/en active Application Filing
Patent Citations (1)
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US4933739A (en) * | 1988-04-26 | 1990-06-12 | Eliyahou Harari | Trench resistor structures for compact semiconductor memory and logic devices |
Non-Patent Citations (6)
Title |
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