US5191335A  Method and apparatus for floatingpoint data conversion with anomaly handling facility  Google Patents
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Abstract
Description
The present invention relates to a method and apparatus for conversion of floatingpoint values between two dissimaler bases or notation systems and handling of conversion anomalies to permit recovery of any lost accuracy.
In recent years, the American National Standards Institute (ANSI) and the Institute of Electrical and Electronic Engineers (IEEE) have provided standards for enhancing and establishing commonality for floatingpoint notation and processing among the computing industry.
The current engineering/scientific workstation, highperformance mainframe, and supercomputing markets seem to be strongly signalling support of IEEE Standard for Binary FloatingPoint Arithmetic (ANSI/IEEE 7541985) as the industry standard for binary floatingpoint notation and processing.
Recognizing the significance of both the IEEE standard and the IBM hexadecimal formats in heterogeneous cooperative processing, the preferred embodiment offers an application development facility for floatingpoint interchange to support coexistence and migration between the ANSI/IEEE notation and IBM hexadecimal floatingpoint notations used by the ESA/370 and ESA/390 processing systems.
Although prior floatingpoint conversion aids exist, as shown for example, in U.S. Pat. No. 4,792,793 of Rawlinson, etal and U.S. Pat. No. 4,831,575 of Kuroda, there is need for additional facility that provides enhancements for supporting more accurate heterogenous coexistence and cooperative processing among systems using IBM hexadecimal floatingpoint facilities and systems using ANSI/IEEE 7541985 binary floatingpoint facilities, and facility for analyzing accuracy exposure and hence, balancing system accuracy relative to performance among heterogeneous cooperative processing systems.
Although the method and apparatus disclosed relates to any pair of floatingpoint notation systems that are not totally coincident in value coverage, a brief description of the relationship between an example pair used in one embodiment is useful to contextually demonstrate the field of the invention.
The IBM hexadecimal floatingpoint (hereinafter referred to as hexadecimal floatingpoint) short and the ANSI/IEEE 7541985 binary floatingpoint (hereinafter referred to as binary floatingpoint) single are each 32 bits (and both commonly referred to as real *4), but the field formats and the notation semantics are different from one another. The hexadecimal floatingpoint long and the binary floatingpoint double are each 64 bits (and both commonly referred to as real *8), but the field formats and notation semantics also are different from one another.
For a more detailed description of each of the formats, refer to IEEE Standard for Binary FloatingPoint Arithmetic (ANSI/IEEE 7541985) for binary floatingpoint and to IBM Enterprise Systems Architecture/370 Principles of Operation, SA227200, for hexadecimal floatingpoint.
Although the short and single formats are the same size (32 bits), the field definition is different in size and semantics. The fraction field in both formats may have coincidence in value, but the hexadecimal fraction is actually six sets of four binary digits, hence, the hexadecimal floatingpoint fraction is multiplied by a power of 16 determined by its characteristic (biased exponent), whereas the binary floatingpoint fraction is multiplied by a power of 2 determined by its biased exponent.
Furthermore, the normalized hexadecimal floatingpoint fraction is a number between 0 and 1, whereas the normalized binary floatingpoint fraction is a number between 1 and 2, and the denormalized binary floatingpoint fraction is a number between 0 and 1.
Consequently, the binary floatingpoint format can describe some finer precision numbers than the hexadecimal floatingpoint format, but the hexadecimal floatingpoint format can describe a larger range of numbers. The relationship between the short and single formats is illustrated as follows: ##STR1##
The range of numbers and the significant fraction bits for each format follows: ##STR2##
As with the short/single formats, the field sizes and semantics differ, although each use 64 bits. The fractions differ in the same way as the short/single fractions, but the hexadecimal floatingpoint binary fractions use more bits, and the biased exponent for the binary floatingpoint multiplier uses more bits. Consequently, the hexadecimal floatingpoint format can describe some finer precision numbers, but the binary floatingpoint format can describe a larger range of numbers. The relationship between the short and single formats is illustrated as follows: ##STR3##
The range of numbers and the significant fraction bits for each format follows: ##STR4##
Because the hexadecimal base numbering is periodically consistent with the binary base numbering system (2^{4} =16^{1}), the binary exponent and fraction can be adjusted to fit the exponent harmonics between the two notation systems.
Unfortunately, as the fraction is adjusted to accommodate the periodic equivalence for exponents and the restricted fraction field, loworder significance can be lost. Also, because the fraction field of the binary double notation is smaller than the fraction field of the hexadecimal long notation, loworder significance can be lost during conversion. This loss of precision, or units in the last place (ULPs), can occur when converting from short to single (denormalized result), from single to short and from long to double.
When such a loss occurs, the result may be rounded to provide tolerable accuracy, but the need remains for a facility to detect, compensate, evaluate effect, and permit recovery from this precision loss.
The binary floatingpoint format also includes a representation for infinity and symbolic entities that are not numbers (NaNs) encoded in the floatingpoint format, but the hexadecimal floatingpoint notation does not provide for these symbols.
______________________________________binary floatingpoint singleIn e=111 1111 1 f=000 0000 0000 0000 0000 0000finityNaN e=111 1111 1 f=nonzerobinary floatingpoint doubleIn e=111 1111 1111 f=0000 0000 0000 0000 0000 0000 ... 0000finityNaN e=111 1111 1111 f=nonzero______________________________________
For the current invention an anomaly is defined as a floatingpoint value in a first floatingpoint notation format that cannot unambiguously, accurately, and completely be represented in the second floatingpoint notation format. For example, when converting from hexadecimal floatingpoint short notation format to binary floatingpoint single notation format, the hexadecimal floatingpoint values that excede the range of representable binary floatingpoint values are recognized as anomalies; also, when converting from hexadecimal floatingpoint long notation format to binary floatingpoint double notation format, the hexadecimal floatingpoint values that have finer precision, that is, more significant bits, than can be represented by the binary floatingpoint notation format are recognized as anomalies; and as further example, when converting from binary floatingpoint notation formats to hexadecimal floatingpoint notation formats, the floatingpoint values previously described as infinity and symbolic entities, which cannot be unambiguously represented by the hexadecimal floatingpoint notation formats.
Cooperative processing among heterogeneous systems is increasing with the variety of workstation, mainframe, and supercomputing interconnections and ever expanding ways of combining these varied systems to provide entry and display interaction, dynamic visualization of computational processing, large distributed data repositories and data servers for search, retrieval and maintenance, and distributed computational servers to apply greater computational power to problems and reduce elapsed time required to complete problem solutions. The heterogeneous nature of these coupled systems and the asymmetry of the system structure that ensues manifests the need for floatingpoint data conversion anomaly handling facilities that permit accuracy recovery, accuracy loss analyses, floatingpoint data characteristic analyses, as well as conversion algorithm selection flexibility.
U.S. Pat. No. 4,792,793 of Rawlinson, etal provides an example of typical prior art in the field, which provides a means for conversion between one floatingpoint base and a different floatingpoint base. In that apparatus coincidence of value coverage is assumed, ignoring possibility for anomalies relative to the conversion algorithm. Coincidence of value coverage is also assumed in U.S. Pat. No. 4,831,575 of Kuroda. U.S. Pat. No. 3,872,442 of Boles, etal provides a means for detecting anomalies during a conversion sequence and selecting a predetermined alternative algorithm for the detected anomalies and producing and indication of unexpected anomalies that are detected during conversion, but it does not provide for recovery of accuracy loss due to the selection of an alternative algorithm nor does it provide accuracy recovery information nor does it provide floatingpoint data characteristic analysis tabulation.
A search for art related to accuracy recovery facility and characteristic analysis facility for floatingpoint data conversion among heterogeneous floatingpoint notation and processing systems has revealed nothing yet in this field.
The anomaly handling facility provides a system for controlling conversion, detecting anomalies, providing analysis of anomaly content in an array of floatingpoint elements, and preserving reconstruction data to recover value accuracy typically lost when anomalies are encountered during conversion.
In accordance with the preferred embodiment of the present invention, there is provided means for rounding or constant substitution to provide a reason of accuracy of the conversion and further, means for determining the frequency of rounding or constant substitution action and for recording and tabulating such frequency and further a means for capturing and preserving accuracy recovery and reconstruction data that can be used to recover the lost precision of value in the converted environment.
Although the preferred embodiment specifically handles anomalies relative to the commonality of value representation by both IBM ESA/370 hexadecimal floatingpoint notations and ANSI/IEEE 7541985 binary floatingpoint standard notations, the systematic design provided by the disclosed floatingpoint notation conversion anomaly handling facility can be applied to an pair of floatingpoint notation systems that are not totally coincident in value coverage.
A detailed description of the present invention is provided along with the accompanying drawings wherein
FIG. 1 illustrates an overview summary of the floatingpoint data conversion and anomaly handling facility.
FIG. 2 presents an overview schematic depicting a multiplicity of contextual system environments in which the present invention could be included.
FIG. 5 and Table 2 illustrate flow position and structure of an array of control and status registers.
FIG. 3 depicts a model for classifying conversion algorithm ranges by floatingpoint value.
FIG. 4 and accompanying textual description shows how the floatingpoint value requiring conversion can be compared with the rules for classification (maxx, maxi, max, min, mind, mindt, minz, and 0) to select conversion algorithms and recovery reconstruction data preservation algorithms.
This floatingpoint data conversion system converts floatingpoint data between IBM System/370 and ESA/390 hexadecimal floatingpoint data formats and ANSI/IEEE 7541985 binary floatingpoint data formats and provides additional anomaly handling facility for reprogramming selection rules for selecting conversion algorithms by floatingpoint value class, reprogramming conversion algorithms for reprogrammable algorithm classes, anomaly frequency recording and tabulation, anomaly value accuracy recovery and reconstruction data capturing and preservation, and usage error detection and reporting capabilities. The anomaly handling facilities are key for recovering accuracy that would be lost during conversion. Currently available conversion systems sacrifice accuracy.
FIG. 1 presents an overview summary of the floatingpoint data conversion and anomaly handling facility. In this illustration, the conversion system assumes the availability of some means for program 115 and data storage 116 external to the conversion system but with means for interconnecting and interacting with the conversion system means for sensing external stimuli as described in the subsequent paragraphs and adequate means for sensing, interpreting, capturing, and as necessary preserving conversion system signal presentation, indication, and delivery devices. The anomaly handling facility comprises a set of programmable controls 101 for selecting conversion algorithms, recovery data preservation, floatingpoint data array analysis, controlling conversion and analysis operation, and indicating status, a set of conversion algorithms 102, a means 103 for stimulating the controls, a means 104 for receiving floatingpoint values for conversion, a means 105 for delivering converted floatingpoint values, a means 106 for detecting anomalies, classifying them according to available conversion algorithms and selecting appropriate algorithms, a means 107 for accumulating anomaly quantity tabulation relative to available conversion algorithms, recovery data preservation, and floatingpoint notation characteristics, a means 108 for capturing and preserving value attributes useful for accurately reconstructing anomaly values with factoring or other recovery techniques appropriate to the converted floatingpoint notation and processing system, a means 109 for delivering reconstruction data to the data storage 116, a means 110 for delivering anomaly quantity tabulation useful for analyzing floatingpoint data arrays to the data storage 115, a means 111 for receiving controls for algorithm detection and selection 106 and delivering status information to data storage, a means 112 for cycle repetition, a means 113 for presenting cycle repetition states, which are useful for stepping through storage locations, a path 114 from algorithm selection controls 106 to conversion algorithms 102, value preservation algorithms 108, and counters 107, and a means 117 for determining state of the conversion facility.
FIG. 1 presents an overview schematic of the anomaly handling facility using a program storage as a repository for stimulus and a data storage as a repository for programmable control information, control and operational status indications, floatingpoint values requiring conversion, converted floatingpoint values, anomaly quantity tabulation, and recovery reconstruction data.
FIG. 2 presents an overview schematic depiciting a multiplicity of computing systems coupled by either networks or shared data storage with three variations for including floatingpoint data conversion systems: one included with a computational server (computer A), one included in the network path (between computational server N and computer network N as a part of a data repository server), and one built into a shared data storage used for memory coupled computational clusters. This environment assumes a variation of floatingpoint notation systems among the computational engines.
The external stimulus for function selection can be presented with as few as three signals or as many as sixteen signals to select combinations of functions as indicated in the table in Table 1. The stimulus can excite combinations of conversion, rules changes for algorithm selection, preservation of recovery reconstruction data, and quantity analysis tabulation.
In the preferred embodiment, this means is provided by the register 101 or ndx(1), referred to as enhancement control and identified in the on entry definition column of an array of control and status registers illustrated in Table 2.
The value of ndx(1) on entry is the primary control for determining results, selecting counters, and defining the report format desired. Any negative value enables enhanced anomaly handling. Further definition of the anomaly handling is determined by the value of ndx(1) as indicated by Table 1.
TABLE 1______________________________________ Reconndx(1) Convert Alt Table Data Count______________________________________≧0 yes no no no1 yes yes yes yes2 no yes yes no**3 no yes no yes4 yes yes no no5 yes no yes yes6 no no yes no**7 no no no yes 8* no *** no no______________________________________ Note: *ndx(1)<8 causes input argument error report **summary counter ndx(15) is included with recon data ***defaults returned in ndx(2144)
A state/control array labelled ndx provides both the anomaly handling definition (on entry) and the anomaly report (on return). The state/control array is depicted in the context of the conversion flow in FIG. 5, and Table 2 shows the structure and use of ndx. Note that the element labelled "completion status" is also used for enhancement control on excitation to select the enhancement facilities.
Table 2 describes the structure the array of registers used to present the function selection stimulus, alternate conversion algorithm selection rules, and recovery reconstruction data preservation limit control. These registers are identified by number in the column labeled "Element", and by purpose description in the column labeled "On Entry".
Table 2 also demonstrates how the same set of registers can be used for presenting control and operational status as identified in the column labeled "On Return". Further, as suggested by the register descriptions, these registers can be used to present the anomaly quantity tabulator used for floatingpoint data array analyses.
TABLE 2______________________________________Element On Entry On Return______________________________________ 1 enhancement control anomaly index or error code 2 recon data area size not used 315 not used counters, see Table 716 reserved nin value warning17 reserved nzm value warning18,19 reserved reserved20 check code not used2144 anomaly control table not used4550 reserved reserved51end not used recon data areachk check code not used______________________________________ Notes: 1. end = 51+(ndx(2)*4) 2. chk = end+1
The required dimension and elements of the ndx array varies according to the enhancement facilities selected. The ndx array dimension and elements required are shown in Table 3.
Note: The excitation may define only the minimum required or it may define more. If more is defined, the facility will ignore the excess.
TABLE 3______________________________________ndx(1) dimension elements used______________________________________≧0 1 11 52+(ndx(2)*4) all2 52+(ndx(2)*4) all except 3143 44 1, 3444 44 1, 16445 52+(ndx(2)*4) all except 16,17,and 21446 52+(ndx(2)*4) 1, 2, 15, 1820, 50chk7 20 1, 315, 18208 44 1, 1820, 2144______________________________________
Additional external stimulus can be presented with at least one signal to begin the system operation cycle and provide cycle repetition control. In the preferred embodiment, a CALL signal is presented with a 32bit register 112 labeled knt, whose contents are interpreted as a binary integer, to provide cycle repetition control and deliver such cycle repetition state via 113.
To provide optional definition for handling anomalies, a conceptual model of the value ranges is defined and rules for conversion and reporting are prescribed in the context of that model.
In the model, the absolute value range for floatingpoint number representation is divided into three categories relative to the range of absolute values that can be represented by both notation schemes.
1. source>destination
2. normal
3. source<destination
Although zero provides a boundary, it is excluded from all categories because it has the same semantics for both notation schemes. This model is depicted in FIG. 3.
The normal category includes absolute numeric values that can be represented in both notation schemes, ignoring precision of the ULPs of the fraction, as normalized values. A normalized floatingpoint number has a nonzero leftmost hexadecimal fraction digit for hexadecimal floatingpoint and a nonzero leftmost fraction bit for binary floatingpoint. For reference, the lower bound of this category is defined by min and the upper bound is defined by max.
The source>destination category includes values that are excessive in absolute value relative to the largest number in the normal category including values that are not considered as numbers (NaN's) and other values that are not representable in the destination form (infinity). The upper bound of this category is defined by maxx, which is a value composed of all bits equal to one, ignoring the sign bit.
The source>destination category includes values that are diminutive in absolute value relative to the smallest number in the normal category, except zero. However, the lower bound of this category is defined by zero.
As shown in FIG. 3, both the source>destination and the source<destination categories are further divided into more definitive parts. The division point for source>destination is defined by maxi and the two divisions for source<destination are defined by mind and minz. Additionally, mindt defines the diminutive boundary extension limit for mind values.
Conversion rules are then identified by the following terms, which can be prescribed by values in the ndx (2144) subarray, with each CALL, or by the BLOCK DATA array initialization established during load of the application program.
Boundary terms are values in source notation and result terms are values in destination notation.
nix to define the result of action required to produce the result when the source number is maxx or lies between maxi and maxx, except when binary source is NaN or infinity and except when hexadecimal source is unnormalized.
maxi to define the lower boundary for nix and the upper boundary for nin. This is a flexible boundary that can be varied with the CALL parameter.
nin to define the result for numbers that equal maxi or lie between max and maxi, except when hexadecimal source is unnormalized.
mind to define the diminutive boundary extension allowed for denormalized destination values. This is a flexible boundary that can be varied with the CALL parameter.
nzm to define the result or action for source numbers that equal minz or lie between min and minz, except when hexadecimal source is unnormalized.
minz to define the lower boundary for nzm and the upper boundary for nzz. This is a flexible boundary that can be varied with the CALL parameter.
nzz to define the result or action for source numbers that lie between zero and minz, except when hexadecimal source is unnormalized.
inf to define the result for infinity source
nan to define the result for NaN source
nanu to define the result for unnormalized hexadecimal source. If one or more leftmost fraction digits are zeros, the number is said to be unnormalized.
nrd to indicate whether inexact due to loss of precision should be counted as an anomaly. 0=result is rounded toward zero, not recognized as anomaly; 1=result is rounded toward zero, counted as anomaly, included with report; 0>nrd>1, invalid.
Applying the model, the range categories identify a set of nine conversion algorithms grouped into six classes for selection during the conversion cycle. FIG. 4 shows how the floatingpoint value requiring conversion can be compared with the rules for classification (maxx, maxi, max, min, mind, mindt, minz, and 0) to provide the means 106 to select conversion algorithms and recovery reconstruction data preservation algorithms. Referring to FIG. 4, data received via 104 is converted to provide a result in register 10222 in the target format. The algorithm used to produce the result in register 10222 is determined by comparisons among registers 1061 through 1069 in set as illustrated and identified by selection lines 11424 through 11429. Lines 11424 through 11429 also feed the anomaly counters 107. Additionally, accuracy recovery and reconstruction data is produced in register array 10823 in parallel with that produced for delivery via 105. In the preferred embodiment, the algorithm used to produce the recovery and reconstruction data is selected by the same comparisons used to select the algorithm for producing the result for delivery via 105, however, a separate and similar algorithm selection control could be used to provide greater flexibility.
As illustrated in FIG. 4, algorithms are paired in six sets: 1) 10210, 10811 (nix); 2) 10212, 10813 (nin); 3) 10214, 10815 (normal); 4) 10216, 10817 (denorm); 5) 10218, 10819 (nzm); 6) 10220, 10821 (nzz). In the preferred embodiment, algorithms for sets 1, 2, 5, and 6 can be dynamically programmed and comparands in registers 1063, 1066, and 1068 can be dynamically programmed, whereas algorithms for set 3 and 4 are fixed in the design as are constant comparand registers 1062, 1064, 1065, 1067, and 1069. However, variations of fixed and programmable registers might prove useful for alternate embodiments in certain environments.
Referring again to Table 2 for context, Table 4 further describes the same register set identified as the anomaly control table, which can be programmed during the excitation but prior to the conversion algorithm selection cycle period. In FIG. 3, the dashed lines labeled maxi, mind, and minz are programmable, while the solid lines are fixed boundaries, which is not restrictive by the design, but rather representative of the preferred embodiment. The same classes and comparisons are used to select the algorithm for preserving recovery reconstruction data to make it easy to use for the converted environment.
TABLE 4______________________________________ndx(n) bytes 03 bytes 47 type of term______________________________________21,22 nix 03 nix 47 result (destination)23,24 maxi 03 maxi 47 boundary (source)25,26 nin 03 nin 47 result (destination)27,28 mind 03 mind 47 boundary (source)29,30 nzm 03 nzm 47 result (destination)31,32 minz 03 minz 47 boundary (source)33,34 nzz 03 nzz 47 result (destination)35,36 inf 03 inf 47 result (destination)37,38 nan 03 nan 47 result (destination)39,40 reserved reserved na41,42 nanu 03 nanu 47 result (destination)43,44 nrd check code na______________________________________ Note: 32bit conversions do not use bytes 47, but the area is reserved. maxx, max, min, and mindt cannot be redefined. all values are absolute values, hence the sign bit is ignored.
The optional reporting facility can aid in attaining accuracy when using converted data. The report provides the following anomaly information:
quantity
index
reconstruction data.
The anomaly quantity report provides several counters to permit analyzing the types of anomalies encountered. The anomaly index provides a reference to locate an anomaly within an array of converted elements. And, the anomaly reconstruction data provides adequate information to reconstruct the source value in the destination environment.
To permit performanceoriented tradeoff, on entry to the subroutine, the call parameters can prescribe limited reporting. The least report is a single index of the last anomaly encountered.
The reconstruction data is provided in the context of the destination environment. That is, when hexadecimal floatingpoint is converted to binary floatingpoint, the reconstruction data is presented in a binary floatingpoint form, and when binary floatingpoint is converted to hexadecimal floatingpoint, the reconstruction data is presented in an hexadecimal floatingpoint form. For each form, the representation has three components plus an anomaly code and index to locate it relative to the context of the converted array.
The three components of the reconstruction data are: an unbiased exponent, a sign for the composite value, and a significand. The format of the reconstruction data follows: ##STR5##
The value of 10830 ndx(2) on entry indicates the maximum quantity of anomaly reconstruction entries allowed. When the limit is reached, the entry of each additional anomaly encountered is written over the last entry. Hence, the first n anomaly reconstruction entries can be recorded, where n=ndx(2).
Note: The value of ndx(2) determines the location of end and chk to validate the anomaly reconstruction data area.
Table 5 depicts a structure of registers for capturing anomaly recovery reconstruction data. This data is further described for the preferred embodiment in FIG. 7 and the textual description following the heading "Reconstruction Data".
Anomaly reconstruction data is reported in theregister array 10823 ndx(51end). Each entry contains the anomaly index and the reconstruction data. When the reconstruction report is selected, ndx must be defined as an array with a dimension equal to 52+(ndx(2)*4).
TABLE 5______________________________________ndx(51+n) ndx(52+n) ndx(53+n) ndx(54+n)______________________________________anomaly code, unbiased expo sign, significand significandindex nent 131 3263______________________________________ Note: n may equal 0 to ndx(2)*4 in increments of 4
Each anomaly index is a single integer whose value can be used as an index into the source or result array to select the element that was treated as an anomaly.
The reconstruction data for each anomaly encountered provides an encoded representation that identifies the anomaly and permits reconstruction of the source value in the destination environment. The more likely uses will be:
to develop scaling factors for processing out of range anomalies by factoring the reconstruction data and using the factors for scaling during subsequent processing, for example:
______________________________________if exponent n = 128 + (n128) fraction f = fthen real*4 a = 2.sup.n *for real*4 a = 2.sup.128 *2.sup.(n128) *f______________________________________
thus, the reconstruction data fraction can be used with a factor of the reconstruction data exponent to form a real *4 or a real *8 value that can be used with a second factor formed by the remaining exponent factor and a simulated fraction that forms a mantissa of one.
to redevelop the value in a larger precision format, for example:
ULPs lost from a value when HS2BS results in a denormalized value can be recovered by adding the binary double bias to the reconstruction data exponent, shifting it left into bits 111, and ANDing it with the highorder word (031) of the reconstruction data fraction; then load this value into a real *8 variable for processing
a similar technique may be used for recovering ULPs lost during BS2HS conversions, that is, the converted value may be loaded into a real *8 variable that has equivalence as an integer *4(2) variable, and the loworder word (3263) of the reconstruction data fraction can be ANDed into the second integer *4 element to provide the lost value
no standard larger precision format is defined for recovering ULPs lost during HL2BD conversions, so the fraction has been adjusted to begin with bit 1 and a similar procedure may be used to align it to fit any supported format.
NaNs may be recognized as operand initialization requirements and appropriate preprocessing done prior to using the values.
When the anomaly reconstruction data is included in the report, associated with each anomaly code and index entry is a threecomponent reconstruction value, including:
1. unbiased exponent
2. sign for composite value
3. significand
This information will be adequate to completely reconstruct the source value in the destination environment. The format of the threecomponent reconstruction value was previously described.
The first component, the unbiased exponent, is an integer *4 containing the value of the exponent for the destination environment if the destination environment's exponent were expanded to an integer *4. That is, when hexadecimal floatingpoint is converted to binary floatingpoint, the unbiased exponent is an unbiased binary floatingpoint, the unbiased exponent is an unbiased hexadecimal floatingpoint exponent.
The second component, the sign of the composite value is the highorder bit of the significand.
The third component, the significand is equivalent to a real *8 value that can be multiplied by the unbiased exponent to accurately produce the source value. However, for the binary floatingpoint values, the highorder bit (bit 8) is the bit to the left of the radix point and for the hexadecimal floatingpoint values, the highorder digit (bits 811) is the digit to the right of the radix point.
Additionally, to make these values easier to reconstruct for processing, the significand is aligned to the most likely destination format to be used for value recovery and processing. For example, significands preserved to recover lost ULPs during HS2BS conversion are aligned with the highorder bit in bit position 12 to permit easy formation of binary double numbers. Similarly, values preserved for recovery from lost ULPs during BS2HS conversions are aligned with the highorder bit in bit position 8 to permit easy formation of hexadecimal long numbers.
The anomaly code, stuffed into the highorder digit of the index, is an encoded classification of the anomaly represented by this entry. Table 6 describes the encoded classifications.
TABLE 6______________________________________Anomaly ndx(315) ndx(2144)code counter entry Description______________________________________3 3,5 nix Undesirable source  beyond range5 5* nin Inexact  beyond range near max7 7* nzm Inexact  beyond range near min9 7,9 nzz Inexact  beyond range near zeroA 5,10 inf Infinity  **B 5,11* nan NaN  **,***D 13 nanu Unnormalized source  ***E 14 nrd Inexact  lost preci sion______________________________________ Note: All anomalies increment counter 15 *summary counter, see Table 7 **unbiased exponent invalid ***significand contains significant bits unmodified
The anomaly counters 107 are accumulated in the ndx(315) register array, as cited in Table 2, using the assignments defined in Table 7. The four columns in the right portion of the table refer to the embodiment conversion descriptions that follows. The anomaly count is an integer whose value indicates the quantity of anomalies encountered during each call of the subroutine. The value is reset to zero when the subroutine is called and increased by one for each anomaly encountered. Table 1 indicates how ndx(1) enables the counters.
TABLE 7______________________________________ndx(n) Definition H2BS H2BL B2HS B2HD______________________________________ 3 inexact results due to x x x excessive source > maxi(nix) 4 summary of source x x x x characteristic/ex ponent = all ones 5 summary of inexact x x x x results due to ex cessive source (nin, nix., inf, nan, nans) 7 summary of inexact x x x x results due to diminutive source (nzm, nzz) 9 inexact results due to x x x diminutive source < minz (nzz)10 source is infinity (inf) x x11 summary of source x x NaN's (nan)13 source unnormalized x x (nanu)14 inexact results due to x x x lost fraction ULPs (nrd)15 summary of all x x x x anomalies (inexact results)______________________________________
On completion of cyclerepetition sequences, all anomaly reports can be observed in the ndx array.
The value representing conversion facility state 117 returned in ndx(1) is an index that identifies the last anomaly encountered. The index is relative to the first element of the source variable. When no anomalies are encountered, ndx(1) remains unchanged.
Note: The index of the last anomaly encountered is reported for all ndx(1) functions except 8 (return default ACT).
When invalid excitation is detected, no conversion occurs and ndx(1) indicates the invalidity as follows:
2 ndx(2)≦0
9 ndx(1)<8
10 knt≦0
20 ndx(20)≠check code
23 maxx=ndx(23) or ndx(23)≦max
27 min<ndx(27) or ndx(27)<mindt
31 ndx(27)≦ndx(31) or ndx(31)≦0
43 1<ndx(43) or ndx(43)<0
44 ndx(44)≠check code
51 ndx(chk)≠check code,
Table 8 indicates the order in which arguments are examined for errors.
TABLE 8______________________________________≧01 2 3 4 5 6 7 8______________________________________10 9 9 9 9 9 9 9 920 20 20 20 20 20 20 2010 10 10 10 10 10 1044 44 44 44 2 231 31 31 31 51 5127 27 27 2723 23 23 2343 43 43 432 251 51______________________________________
Table 9 shows the relationship between selected functions and input argument errors.
TABLE 9______________________________________input argument error value on returnfunction ≧0 1 2 3 4 5 6 7 8______________________________________con 10 10 10 10 10 10 10 10 10versionen 9 9 9 9 9 9 9 9hance 20 20 20 20 20 20 20 20mentsal 23 23 23 23ternate 27 27 27 27ACT 31 31 31 31 43 43 43 43 44 44 44 44recon 2 2 2 2struc 51 51 51 51tiondata______________________________________
Note: Remember that some input argument values affect others. For example, ndx(27) and ndx(31), in this case, although ndx(27) may be the only value redefined, it could cause ndx(1), to be set to 31 if the ndx(27) value were less than or equal to the ndx(31) value.
The following conversion descriptions show how four embodiments of the present invention can provide conversion and anomaly handling flexibility for the four conversion cases of the preferred embodiment by showing a comparison of the two floatingpoint notation formats and the conversion algorithm used for the normal range (between max and min) values, the substitution algorithms used for the other classes, the registers that can define alternate algorithm selection rules and the range of values that can be provided for the substitution algorithms, and the anomalies detected and tabulated for analysis for each of the conversions provided by the preferred embodiment.
HS2BS provides identity and reference to previous counter descriptions
Convert hexadecimal short formal real*4 numbers into binary single format real*4 numbers.
TABLE 4______________________________________ndx(n) bytes 03 bytes 47 type of term______________________________________21,22 nix 03 nix 47 result (destination)23,24 maxi 03 maxi 47 boundary (source)25,26 nin 03 nin 47 result (destination)27,28 mind 03 mind 47 boundary (source)29,30 nzm 03 nzm 47 result (destination)31,32 minz 03 minz 47 boundary (source)33,34 nzz 03 nzz 47 result (destination)35,36 inf 03 inf 47 result (destination)37,38 nan 03 nan 47 result (destination)39,40 reserved reserved na41,42 nanu 03 nanu 47 result (destination)43,44 nrd check code na______________________________________ Note: 32bit conversions do not use bytes 47, but the area is reserved. maxx, max, min, and mindt cannot be redefined. all values are absolute values, hence the sign bit is ignored.
Normal range algorithm
______________________________________binary floatingpoint______________________________________f: f(bin) = f(hex)*J1e: e(bin) = 4*(c(hex)64) + J2 + 126 = 4*c(hex) + J2 130s: Sign (bin) = Sign(hex)______________________________________ Where J1 and J2 are both a function of the 4 leftmost bits of hex fraction. ccharacteristic ebiased exponent ffraction ssign
Note: No precision is lost when source numbers are in normal range. Denorm range algorithm
______________________________________binary floatingpoint______________________________________f: f(bin) = f(hex)*J1/2**(131C+J2)e: e(bin) = 0s: s(bin) = s(hex)______________________________________ Where J1 and J2 are both a function of the 4 leftmost bits of hex fraction. ccharacteristic ebiased exponent ffraction ssign
Note: A loss of precision can occur if the least significant bits of the fraction are nonzero.
TABLE 10__________________________________________________________________________ destination ndxmodelsource default default (2144) ndx (2144) limits*__________________________________________________________________________maxx 7FFF FFFF 7F80 FE00 nanix maxi<s≦maxx 7F80 FE00 21 7FFF FFFF  0000 0000maxi 7FFF FFFE 7F80 0000 23 max<maxi<maxxnin max<s≦maxi 7F80 0000 25 7FFF FFFF  0000 0000**max 60FF FFFF 7F7F FFFF nanormal60FF FFFF 7F7F FFFF na 2140 0000 0080 0000min 2140 0000 0080 0000 nadenorm213F FFFF na mind≦denorm≦min1B80 0000mind 1B80 0000 0000 0001 27 mindt≦mind≦minmindt1B80 0000 0000 0001 nanzm minz≦s≦mind 0000 0000 29 7FFF FFFF**  0000 0000minz 0010 0000 0000 0000 31 0<minz<mindnzz 0<s<minz 0000 0000 33 7FFF FFFF  0000 0000±00000 0000 0000 0000 na8000 0000 8000 0000inf na 0000 0000 35 nanan na 0000 0000 37 nananu unnormalized 0000 0000 41 7FFF FFFF  0000 0000nrd 43 0000 0001  0000 0000__________________________________________________________________________ Note: *na not available for alternate definition **warnings provided if nin < max and if nzm > min
TABLE 11__________________________________________________________________________ destination ndx (315)modelsource default default code A1 counters*__________________________________________________________________________maxx 7FFF FFFF 7F80 FE00 3 3,5nix maxi<s≦maxx 7F80 FE00 3 3,5maxi 7FFF FFFE 7F80 0000 5 5nin max<s≦maxi 7F80 0000 5 5max 60FF FFFF 7F7F FFFFnormal60FF FFFF 7F7F FFFF 2140 0000 0080 0000min 2140 0000 0080 0000denorm213F FFFF E** 14**1B80 0000mind 1B80 0000 0000 0001 E** 14**mindt1B80 0000 0000 0001 E** 14**nzm minz≦s<mind 0000 0000 7 7minz 0010 0000 0000 0000 7 7nzz 0<s<minz 0000 0000 9 7,9±00000 0000 0000 00008000 0000 8000 0000nanu unnormalized 0000 0000 D 13characteristic = ones 4__________________________________________________________________________ Note: *all anomalies increment counter 15 **lost fraction bits (not recognized when ndx(43)=0)
When input argument errors are detected, no conversion occurs and ndx(1) is set to indicate one of the input argument error codes as follows:
2 ndx(2)≦0
9 ndx(1)<8
10 knt≦0
20 ndx(20)≠check code
23 maxx=ndx(23) or ndx(23)≦max
27 min<ndx(27) or ndx(27)<mindt
31 ndx(27)≦ndx(31) or ndx(31)≦0
43 1<ndx(43)or ndx(43)<0
44 ndx(44)≠check code
51 ndx(chk)≠check code,
HL2BD provides identity for crossreference
Convert hexadecimal long format real*8 numbers into binary double format real*8 numbers. ##STR6##
Normal range algorithm
______________________________________binary floatingpoint______________________________________f: fraction (bin) = fract(hex)/J1c: exp (nin) = 4*(char(hex)  64) + 1019  J2 = 4*char(hex) + 763  J2s: sign (bin) = Sign (hex)______________________________________ Where J1 and J2 are both function of the 4 leftmost bits of hex fraction.
Note: A loss of precision can occur if the least significant bits of the fraction are nonzero.
TABLE 12__________________________________________________________________________ ndxmodel source default destination default (2144) ndx (2144) limits*__________________________________________________________________________maxx 7FFF FFFF FFFF FFFF 7FF0 1FC0 0000 0000 nanix maxi<s≦maxx 7FF0 1FC0 0000 0000 21 7FFF FFFF FFFF FFFFF  0000 0000 0000 0000maxi 7FFF FFFE FFFF FFFF 7FF0 0000 0000 0000 23 max<maxi<maxxnin max<s≦maxi 7FF0 0000 0000 0000 25 7FFF FFFF FFFF FFFF  0000 0000 0000 0000**max 7EFF FFFF FFFF FFFF 4F6F FFFF FFFF FFFF nanormal 7EFF FFFF FFFF FFFF 4F6F FFFF FFFF FFFF na   0010 0000 0000 0000 2FB0 0000 0000 0000min 0010 0000 0000 0000 2FB0 0000 0000 0000 nanzm minz≦s<min 0000 0000 0000 0000 29 0010 0000 0000 0000 minz 0010 0000 0000 0000 0000 0000 0000 0000 31 0010 0000 0000 0000nzz 0<s<minz 0000 0000 0000 0000 33 0010 0000 0000 0000±0 0000 0000 0000 0000 0000 0000 0000 0000 na 8000 0000 0000 0000 8000 0000 0000 0000inf na 0000 0000 0000 0000 35 nanan na 0000 0000 0000 0000 37 nananu unnormalized 0000 0000 0000 0000 41 7FFF FFFF FFFF FFFF  0000 0000 0000 0000nrd 43 0000 0001  0000 0000__________________________________________________________________________ Note: *na not available for alternate definition **warning provided if nin < max
TABLE 13__________________________________________________________________________ code ndx (315)model source default destination default A1 counters*__________________________________________________________________________maxx 7FFF FFFF FFFF FFFF 7FF0 1FC0 0000 0000 3 3,5nix maxi<s≦maxx 7FF0 1FC0 0000 0000 3 3,5maxi 7FFF FFFE FFFF FFFF 7F80 0000 0000 0000 5 5nin max<s≦maxi 7F80 0000 0000 0000 5 5max 7EFF FFFF FFFF FFFF 4F6F FFFF FFFF FFFFnormal 7EFF FFFF FFFF FFFF 4F6F FFFF FFFF FFFF E** 14**   0010 0000 0000 0000 2FB0 0000 0000 0000min 0010 0000 0000 0000 2FB0 0000 0000 0000nzm minz≦s<min 0000 0000 0000 0000 7 7minz 0010 0000 0000 0000 0000 0000 0000 0000 7 7nzz 0<s<minz 0000 0000 0000 0000 9 7,9±0 0000 0000 0000 0000 0000 0000 0000 0000 8000 0000 0000 0000 8000 0000 0000 0000nanu unnormalized 0000 0000 0000 0000 D 13 characteristic = ones__________________________________________________________________________ Note: *all anomalies increment counter 15 **lost fraction bits (not recognized when ndx(43)=0)
When input argument errors are detected, no conversion occurs and ndx(1) is set to indicate one of the input argument error codes as follows:
2 ndx(2)≦0
9 ndx(1)<8
10 knt≦0
20 ndx(20)≠check code
23 maxx=ndx(23) or ndx(23)≦max
43 1<ndx(43) or ndx(43)<0
44 ndx(44)≠check code
51 ndx(chk)≠check code,
BS2HS provides identity for crossreference
Convert binary single format real*4 numbers into hexadecimal short format real*4 numbers. ##STR7##
Normal range algorithm
______________________________________hexadecimal floatingpoint______________________________________f: fraction(hex) = (00800000+ Mant (bin))/J1c: Exp (hex) = (Exp (bin)126+J2)/4 + 64 = (Exp (bin)+130+J2)/4s: Sign (hex) = Sign (bin)______________________________________ Where J1 and J2 are both function of the 2 rightmost bits of bin exponent
Note: A loss of precision can occur if the least significant bits of the fraction are nonzero.
TABLE 14______________________________________ destina tion ndx ndx (2144)model source default default (2144) limits*______________________________________maxx 7FFF FFFF 7FFF FFFF nanix maxi<s≦maxx 7FFF FFFF 21 namaxi 7F80 0000 7FFF FFF0 23 nanin max<s≦maxi 7FFF FFF0 25 namax 7F7F FFFF 60FF FFFF nanormal 7F7F FFFF 60FF FFFF na   0000 0001 1B80 0000min 0000 0001 1B80 0000 nadenorm na na namind 0000 0001 1B80 0000 27 namindt 0000 0001 1B80 0000 nanzm minz≦s<mind 0000 0000 29 naminz 0000 0001 1B80 0000 31 nanzz 0<s<minz 0000 0000 33 na±0 0000 0000 0000 0000 na 8000 0000 8000 0000inf na 7FFF FFF0 35 7FFF FFFF  0000 0000nan na 7FFF FFFF 37 7FFF FFFF  0000 0000nanu na 0000 0000 41 nanrd 43 0000 0001  0000 0000______________________________________ Note: *na not available for alternate definition **warnings provided if nin < max
TABLE 15______________________________________ ndx destination (315)model source default default code A1 counters*______________________________________max 7F7F FFFF 60FF FFFFnormal 7F7F FFFF 60FF FFFF E** 14**   0000 0001 1B80 0000min 0000 0001 1B80 0000±0 0000 0000 0000 0000 8000 0000 8000 0000inf 7F80 0000 7FFF FFF0 A 5,10nan 7F8x xxxx 7FFF FFFF B 5,11 exponent = ones 4______________________________________ Note: x nonzero *all anomalies increment counter 15 **lost fraction bits (not recognized when ndx(43)=0)
When input argument errors are detected, no conversion occurs and ndx(1) is set to indicate one of the input argument error codes as follows:
2 ndx(2)≦0
9 ndx(1)<8
10 knt≦0
20 ndx(20)≠check code
43 1 <ndx(43) or ndx(43)<0
44 ndx(44)≠check code
51 ndx(chk)≠check code,
BD2HL provides identity for crossreference
Convert binary double format real*8 numbers into hexadecimal long format real*8 numbers. ##STR8##
Normal range algorithm
______________________________________hexadecimal floatingpoint______________________________________f: Mant (hex) = (00100000 + Mant (bin))*J1c: Exp (hex) = (Exp (bin)1019+J2)/4 + 64 = = (Exp (bin) 763+J2)/4s: Sign (hex) = Sign (bin)______________________________________ Where J1 and J2 are both function of the 2 rightmost bits of I3E exponent
Note: No precision is lost when source numbers are in normal range.
TABLE 16__________________________________________________________________________ ndxmodel source default destination default (2144) ndx (2144) limits*__________________________________________________________________________maxx 7FFF FFFF FFFF FFFF 7FFF FFFF 0000 0000 nanix maxi<s≦maxx 7FFF FFFF 0000 0000 21 7FFF FFFF FFFF FFFF  0000 0000 0000 0000maxi 7FF0 0000 0000 0000 7FFF FFF0 0000 0000 23 max<maxi<maxxnin max<s≦maxi 7FFF FFF0 0000 0000 25 7FFF FFFF FFFF FFFF  0000 0000 0000 0000**max 4F6F FFFF FFFF FFFF 7EFF FFFF FFFF FFFF nanormal 4F6F FFFF FFFF FFFF 7EFF FFFF FFFF FFFF na   2FB0 0000 0000 0000 0010 0000 0000 0000min 2FB0 0000 0000 0000 0010 0000 0000 0000 nadenorm na namind 2FB0 0000 0000 0000 0010 0000 0000 0000 27 namindt 2FB0 0000 0000 0000 0010 0000 0000 0000 na nanzm minz≦s<mind 0000 0000 0000 0000 29 7FFF FFFF FFFF FFFF  0000 0000 0000 0000**minz 0000 0000 0000 0001 0000 0000 0000 0000 31 7FFF FFFF FFFF FFFF  0000 0000 0000 0000nzz 0<s<minz 0000 0000 0000 0000 33 7FFF FFFF FFFF FFFF  0000 0000 0000 0000±0 0000 0000 0000 0000 0000 0000 0000 0000 na 8000 0000 0000 0000 8000 0000 0000 0000inf 7FF0 0000 0000 0000 7FFF FFF0 0000 0000 35 7FFF FFFF FFFF FFFF  0000 0000 0000 0000nan 7FFF FFFF FFFF FFFF 7FFF FFFF 0000 0000 37 7FFF FFFF FFFF FFFF   7FF0 0000 0000 0001 0000 0000 0000 0000nanu unnormalized 0000 0000 0000 0000 41 nanrd 43 na__________________________________________________________________________ Note: *na not available for alternate definition **warning provided if nin < max
TABLE 17__________________________________________________________________________ code ndx (315)model source default destination default A1 counters*__________________________________________________________________________maxx 7FFF FFFF FFFF FFFF 7FFF FFFF 0000 0000 3 3,5nix maxi<s≦maxx 7FFF FFFF 0000 0000 3 3,5maxi 7FF0 0000 0000 0000 7FFF FFF0 0000 0000 5 5nin max<s≦maxi 7FFF FFF0 0000 0000 5 5max 4F6F FFFF FFFF FFFF 7EFF FFFF FFFF FFFFnormal 4F6F FFFF FFFF FFFF 7EFF FFFF FFFF FFFF E 14   2FB0 0000 0000 0000 0010 0000 0000 0000min 2FB0 0000 0000 0000 0010 0000 0000 0000nzm minz≦s<min 0000 0000 0000 0000 7 7minz 0000 0000 0000 0001 0000 0000 0000 0000 7 7nzz 0<s<minz 0000 0000 0000 0000 9 7,9±0 0000 0000 0000 0000 0000 0000 0000 0000 8000 0000 0000 0000 8000 0000 0000 0000inf 7FF0 0000 0000 0000 7FFF FFF0 0000 0000 A 5,10nan 7FFF FFFF FFFF FFFF 7FFF FFFF 0000 0000 B 5,11  7FF0 0000 0000 0001 exponent = ones 4__________________________________________________________________________ Note: *all anomalies increment counter 15
When input argument errors are detected, no conversion occurs and ndx(1) is set to indicate one of the input argument error codes as follows:
2 ndx(2)≦0
9 ndx(1)<8
10 knt≦0
20 ndx(20)≠check code
23 maxx=ndx(23) or ndx(23)≦max
31 ndx(27)≦ndx(31) or ndx(31)≦0
44 ndx(44)≠check code
51 ndx(chk)≠check code,
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Cited By (6)
Publication number  Priority date  Publication date  Assignee  Title 

US5687106A (en) *  19950331  19971111  International Business Machines Corporation  Implementation of binary floating point using hexadecimal floating point unit 
US5729481A (en) *  19950331  19980317  International Business Machines Corporation  Method and system of rounding for quadratically converging division or square root 
US5825678A (en) *  19950331  19981020  International Business Machines Corporation  Method and apparatus for determining floating point data class 
US20020095451A1 (en) *  20010118  20020718  International Business Machines Corporation  Floating point unit for multiple data architectures 
US20050240614A1 (en) *  20040422  20051027  International Business Machines Corporation  Techniques for providing measurement units metadata 
DE102004030384A1 (en) *  20040623  20060119  Siemens Ag  System and method for the lossless transmission of floating point numbers in XML 
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Publication number  Priority date  Publication date  Assignee  Title 

US5966085A (en) *  19980409  19991012  Lockheed Martin Corporation  Methods and apparatus for performing fast floating point operations 
CN101916182B (en) *  20090909  20140820  威盛电子股份有限公司  Transmission of fast floating point result using nonarchitected data format 
US20110060892A1 (en) *  20090909  20110310  Via Technologies, Inc.  Speculative forwarding of nonarchitected data format floating point results 
Citations (5)
Publication number  Priority date  Publication date  Assignee  Title 

US3389379A (en) *  19651005  19680618  Sperry Rand Corp  Floating point system: single and double precision conversions 
US3872442A (en) *  19721214  19750318  Sperry Rand Corp  System for conversion between coded byte and floating point format 
US4038538A (en) *  19750818  19770726  Burroughs Corporation  Integer and floating point to binary converter 
US4792793A (en) *  19870528  19881220  Amdahl Corporation  Converting numbers between binary and another base 
US4831575A (en) *  19860109  19890516  Nec Corporation  Apparatus for conversion between IEEE standard floatingpoint numbers and two's complement floatingpoint numbers 
Family Cites Families (2)
Publication number  Priority date  Publication date  Assignee  Title 

JPH0542697B2 (en) *  19840905  19930629  Hitachi Ltd  
US4805128A (en) *  19851122  19890214  Geophysical Service Inc.  Format conversion system 

1990
 19901113 US US07/612,726 patent/US5191335A/en not_active Expired  Fee Related

1991
 19910914 JP JP3263171A patent/JPH05127871A/en active Pending
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Patent Citations (5)
Publication number  Priority date  Publication date  Assignee  Title 

US3389379A (en) *  19651005  19680618  Sperry Rand Corp  Floating point system: single and double precision conversions 
US3872442A (en) *  19721214  19750318  Sperry Rand Corp  System for conversion between coded byte and floating point format 
US4038538A (en) *  19750818  19770726  Burroughs Corporation  Integer and floating point to binary converter 
US4831575A (en) *  19860109  19890516  Nec Corporation  Apparatus for conversion between IEEE standard floatingpoint numbers and two's complement floatingpoint numbers 
US4792793A (en) *  19870528  19881220  Amdahl Corporation  Converting numbers between binary and another base 
Cited By (9)
Publication number  Priority date  Publication date  Assignee  Title 

US5687106A (en) *  19950331  19971111  International Business Machines Corporation  Implementation of binary floating point using hexadecimal floating point unit 
US5729481A (en) *  19950331  19980317  International Business Machines Corporation  Method and system of rounding for quadratically converging division or square root 
US5737255A (en) *  19950331  19980407  International Business Machines Corporation  Method and system of rounding for quadratically converging division or square root 
US5825678A (en) *  19950331  19981020  International Business Machines Corporation  Method and apparatus for determining floating point data class 
US20020095451A1 (en) *  20010118  20020718  International Business Machines Corporation  Floating point unit for multiple data architectures 
US6829627B2 (en) *  20010118  20041207  International Business Machines Corporation  Floating point unit for multiple data architectures 
US20050240614A1 (en) *  20040422  20051027  International Business Machines Corporation  Techniques for providing measurement units metadata 
US7246116B2 (en) *  20040422  20070717  International Business Machines Corporation  Method, system and article of manufacturing for converting data values quantified using a first measurement unit into equivalent data values when quantified using a second measurement unit in order to receive query results including data values measured using at least one of the first and second measurement units 
DE102004030384A1 (en) *  20040623  20060119  Siemens Ag  System and method for the lossless transmission of floating point numbers in XML 
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