KR19990039002U - Floating-point normalizer - Google Patents

Abstract

The present invention relates to a floating-point type normalizer. In the conventional apparatus, all the exponents of the operators are analyzed and compared with each other for normalization, and after comparison, normalization is performed using the result value. There was a problem that it takes a lot of time to compare all. Accordingly, the present invention provides a first and second encoders that separate two input numbers into mantissa and exponent; A precision register for storing significant digits associated with the reliability of the numerical value; First and second subtractors for calculating the number of times of shifting by comparing the numerical value passing through the first and second encoders with the significant number of the precision register; First and second comparison units for comparing the values stored in the first and second index registers with the values output from the first and second subtractors and storing the minimum values in the first and second index registers; First and second exponent registers, each of which is initialized to the maximum value to be shifted initially and whose minimum value is compared with the values of the first and second subtractors in the first and second comparison parts; A third comparing unit which receives the numerical values of the first and second index registers and outputs the minimum value thereof; A scaling register configured to receive a minimum value output from the third comparator and store the same in a control signal; Comprised of the current value of the first and second index registers, the minimum value stored in the scaling register and the current minimum value output from the third comparator and an exponent selector for selecting and outputting one of them by a function selection signal. In the process of normalization and multiple normalization, valid data can be processed immediately, which reduces the comparison time.

Description

Floating-point normalizer

The present invention relates to a floating point format normalizer, and more particularly to a floating point format normalizer for effectively sorting floating point data representing numbers in engineering and scientific applications.

For applications that require many floating point operations, hardware is required for the arithmetic operations of floating point instructions, which may be implemented directly in CPI, or have dedicated coprocessors for C floating point operations in addition to C To execute a floating point instruction.

In engineering or scientific applications dealing with transcendental functions, such as exponential, logarithmic, and trigonometric functions, they take up a lot of space if they are supported by hardware.

Data types used in such engineering or scientific applications are represented as floating point numbers, with the sign as S (S), the exponent as E, and the mantissa as M (Mt Mantissa). do. The S, E, M can be expressed in a number of ways within the range of the number of bits that represent the number, one of the most representative of the methods is the standard set by the Institute of Electrical and Electronics Engineers (IEEE).

The standards of the Institute of Electrical and Electronics Engineers define Single precision, Single-Extended precision, Double precision, Double-Extended precision, respectively, Figure 1 is an 80-bit extension As a double-format format diagram, numbers represented by the above format are (-1) ^S × (1M) × 2 ^{(E + Bias)} values. Here, S is a sign and M is 63 bits except for the most significant bit (MSB) 1 of the 64-bits of the significant number.

In engineering or scientific applications, operations on many floating-point operators may be required. In this case, each operator must be sorted by the same number of digits. This is called normalization, and complex block scaling, There are three cases: complex normalization and scale normalization.

First, in the case of complex block scaling, normalizing a series of complex numbers according to a predetermined number of valid bits. In this case, the number of significant bits is stored in an internal register, and complex normalization refers to normalizing all other numbers smaller than the number of significant bits with which the largest number is normalized. Multiple normalization involves conversion from integer to floating point, which is used with inverse, square root, and inverse square root.

However, in the conventional apparatus, since all the exponents of the operators are analyzed and compared with each other for normalization, and normalized using the result value after comparison, if there are N operators, a long time is required to compare them all. there was.

Accordingly, an object of the present invention is to provide a floating point type normalizer for reducing the comparison time by immediately processing valid data in the case of complex normalization and multiple normalization.

1 is a format diagram of a conventional 80-bit extended double format.

Figure 2 is a block diagram of a floating point type normalizer to which the present invention is applied.

***** Description of the symbols for the main parts of the drawings *****

10: first encoder 20: precision register

30: second encoder 40: first subtractor

50: second subtractor 60: first exponent register

70: first comparator 80: second comparator

90: second index register 100: third comparison unit

120: scaling register 130: exponent selector

The structure of the present invention floating-point type normalizer for achieving the above object comprises: a first and second encoders for separating the input two numbers into mantissa and exponent; A precision register for storing significant digits associated with the reliability of the numerical value; First and second subtractors for calculating the number of times of shifting by comparing the numerical value passing through the first and second encoders with the significant number of the precision register; First and second comparison units for comparing the values stored in the first and second index registers with the values output from the first and second subtractors and storing the minimum values in the first and second index registers; First and second exponent registers, each of which is initialized to the maximum value to be shifted initially and whose minimum value is compared with the first and second subtractors in the first and second comparison parts; A third comparing unit which receives the numerical values of the first and second index registers and outputs the minimum value thereof; A scaling register configured to receive a minimum value output from the third comparator and store the same in a control signal; It is achieved by configuring an exponent selector for selecting one of the current value of the first and second exponent registers, the minimum value stored in the scaling register, and the current minimum value output from the third comparator by selecting a function among them. When described in detail with reference to the accompanying drawings, an embodiment according to the present invention as follows.

FIG. 2 is a block diagram showing the configuration of a floating point type normalizer to which the present invention is applied. As shown in FIG. 2, first and second encoders 10 and 30 that separate two input numbers NUM1 and NUM2 into mantissa and exponent. )Wow; A precision register 20 for storing significant digits related to the reliability of the numerical value; First and second subtractors (40 and 50) for calculating the number of times of shifting by comparing the numerical value passing through the first and second encoders (10 and 30) with the effective number of the precision register (20); The value stored in the first and second index registers 60 and 90 is compared with the value output from the first and second subtractors 40 and 50, and the minimum value is again converted into the first and second index registers 60 and 90. First and second comparison parts (70, 80) to be stored in); The first value is initialized to the maximum value to be shifted first, and the first and second comparison parts 70 and 80 store the minimum value compared with the values of the first and second subtractors 40 and 50. 2 exponent registers 60 and 90; A third comparison unit (100) for receiving the numerical values of the first and second index registers (60,90) and comparing the magnitudes and outputting the minimum values; A scaling register 120 which receives the minimum value output from the third comparator 100 and stores it by a control signal CS2; A function selection signal S _F between a current value of the first and second index registers 60 and 90, a minimum value stored in the scaling register 120, and a current minimum value output from the third comparison unit 100. It is composed of the exponent selector 130 to select and output one of them, and the operation and operation of the present invention configured as described above are as follows.

In determining the outputs P _OUT1 and P _OUT2 of the exponent selection unit 130 by the function selection signal S _F , in the case of complex block scaling, the output value of the scaling register 120 is selected, and in the case of complex normalization, The output value of the third comparison unit 100 is selected as it is, and in the case of multiple normalization, the value of the first index register 60 is selected. This indicates the number of shifts indicating how many shifts should be performed for the square root, inverse square root, and reciprocal.

Complex block scaling receives and processes complex numbers to be stored in the memory, but uses the value stored in the precision register 20 as the effective number of bits.

The two numbers NUM1 and NUM2 received as inputs are separated by mantissa and exponent via the first and second encoders 10 and 30, and output the position of the most significant bit MSB.

The first and second subtractors 40 and 50 subtract the output values of the first and second encoders 10 and 30 from the value of the precision register 20 to find a new index for scaling the data. The subtraction result of the first and second subtractors 40 and 50, that is, the number of shifts is input to the inputs of the first and second comparators 70 and 80, and the first and second index registers 60 and 90 are first input. The maximum value to be shifted is input, and the number of shifts of the first and second comparison units 70 and 80 is compared with the number of small and large, and the small value is returned to the first and second index registers 60 and 90. The operation of storing and comparing the values input to the first and second comparison units 70 and 80 and the values of the first and second index registers 60 and 90 is repeated.

As a result, the values of the first and second exponent registers 60 and 90 are again compared by the third comparison unit 100 to determine which one is the smaller value, and as a result, the smallest value is converted into the scaling register 120 and the exponent. Output to the selector 130.

In addition, the first and second comparison units 70 and 80 enable or disable the first and second comparison units 70 and 80 by the control signal CS1 to control the operation thereof.

As described above, the inventive floating-point type normalizer can immediately process data valid in complex normalization and multiple normalization, thereby reducing the comparison time.

Claims (1)

First and second encoders for separating the input two numbers into mantissa and exponent; A precision register for storing significant digits associated with the reliability of the numerical value; First and second subtractors for calculating the number of times of shifting by comparing the numerical value passing through the first and second encoders with the significant number of the precision register; First and second comparison units for comparing the values stored in the first and second index registers with the values output from the first and second subtractors and storing the minimum values in the first and second index registers; First and second exponent registers, each of which is initialized to the maximum value to be shifted initially and whose minimum value is compared with the values of the first and second subtractors in the first and second comparison parts; A third comparing unit which receives the numerical values of the first and second index registers and outputs the minimum value thereof; A scaling register configured to receive a minimum value output from the third comparator and store the same in a control signal; And an exponent selector configured to select one of the current value of the first and second index registers, the minimum value stored in the scaling register, and the current minimum value output from the third comparator, and select one of them by a function selection signal. Floating point format normalizer, characterized in that.