US4561006A - Integrated circuit package with integral heating circuit - Google Patents
Integrated circuit package with integral heating circuit Download PDFInfo
- Publication number
- US4561006A US4561006A US06/395,551 US39555182A US4561006A US 4561006 A US4561006 A US 4561006A US 39555182 A US39555182 A US 39555182A US 4561006 A US4561006 A US 4561006A
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- integrated circuit
- predetermined
- circuit package
- support members
- heat generating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/345—Arrangements for heating
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0212—Printed circuits or mounted components having integral heating means
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83234—Applying energy for connecting using means for applying energy being within the device, e.g. integrated heater
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- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/14—Integrated circuits
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15322—Connection portion the connection portion being formed on the die mounting surface of the substrate being a pin array, e.g. PGA
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
- H05K1/167—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed resistors
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
- H05K2201/09181—Notches in edge pads
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/10295—Metallic connector elements partly mounted in a hole of the PCB
- H05K2201/10303—Pin-in-hole mounted pins
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
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- H05K2201/10439—Position of a single component
- H05K2201/10477—Inverted
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10727—Leadless chip carrier [LCC], e.g. chip-modules for cards
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
- H05K2203/1115—Resistance heating, e.g. by current through the PCB conductors or through a metallic mask
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/17—Post-manufacturing processes
- H05K2203/176—Removing, replacing or disconnecting component; Easily removable component
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3405—Edge mounted components, e.g. terminals
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3447—Lead-in-hole components
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3494—Heating methods for reflowing of solder
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Definitions
- This invention relates to an improved circuit package. More particularly, it relates to an integrated circuit package having an integral heating circuit for use in raising the temperature of the integrated circuit package sufficiently to melt solder for use in removing the integrated circuit package from a system, or making reflow reconnect into a system.
- the fabrication of integrated circuit components involves the fabrication of an integrated circuit die, often referred to as a chip, that performs the desired electrical or logical function. Chips are of varying sizes, with the main thrust of development to further miniaturize. Miniaturization leads to availability of ever-increasing logic of circuit functions on smaller substrates. Miniaturization increases circuit density and tends to require more leads to be provided for input and output signals and application of power. As leads were made smaller, manual installation and removal techniques became inefficient and in many cases almost impossible to accomplish.
- the package In order to make interconnection to the integrate circuit substrate or chip, it is common to provide a package that will make interconnection with the terminals on the chip and provide means for making electrical interconnection into the system with which the chip will be used.
- the package characteristically supports the chip, and includes circuit interconnections for making electrical connection to terminals on the chip, and for making electrical interconnection to pins for interconnecting the wiring in a support assembly.
- step soldering techniques This involves selecting solders that melt at different temperatures for use in different steps of fabrication. For example, a relatively high melting temperature solder is utilized for soldering the chip to the leads of the integrated circuit package. When a cover is to be soldered over the chip cavity, a medium temperature solder is selected. A relatively low melting temperature solder is selected for making the electrical interconnection of the terminals of the integrated circuit package to the pins that mount to the support chassis.
- Another prior art technique to remove integrated circuit packages is to simply apply a conventional soldering iron to the surface of the package. This allows the heat from the iron to permeate through the package and melt the solder at the chassis pins for either removal or reinsertion of the integrated circuit package.
- This system has many disadvantages but presently is the most widely used system due to general availability of soldering irons at rework or test facilities.
- a primary problem is the unknown temperature of the tip of the iron when it is applied to the integrated circuit package. Characteristically, the iron is pre-heated, and a 100 Watt iron can have tip temperature on the order of 420° Centigrade.
- the present invention provides an improved integrated circuit package having a support structure for supporting an associated integrated circuit element wherein electrical circuits are deposited in layers for making interconnection of the integrated circuit leads to pins for making connections on a supporting assembly.
- An additional circuit element capable of having a source of external power applied to it is incorporated in the package and is electrically insulated from the conductive circuits that are electrically interconnected to the integrated circuit chip. The arrangement is such that when a source of external power is applied to the additional circuit element, a current passes therethrough and results in the generation of heat within the integrated circuit package. The level of temperature elevation is controlled by the resistance of the circuit element in combination with the power applied.
- Sufficient resistance is incorporated in the additional circuit element to allow a temperature rise to a level such that solder utilized for interconnecting the pins to the integrated circuit package will be caused to melt and flow, thereby allowing the integrated circuit package to be removed from an existing system or to be reinstalled in the system.
- Still another object of the invention is to provide an improved integrated circuit package that includes an additional circuit element that is a resistive element, to which a source of external power can be applied for raising the temperature of the integrated package in a controlled manner, thereby eliminating the need of applying conductive heat to the integrated circuit package or associated pins for soldering.
- Yet a further object of the invention is to provide an improved integrated circuit package having an additional circuit element that is a heating element integrated therein that permits the temperature of the integrated circuit package to be raised to a predetermined temperature level by application of an external power source to the heating element where the temperature level can be controlled within a step solder system.
- Another object of the invention is to provide an improved integrated circuit package having an externally controlled additional circuit element that is a heat generating resistive element incorporated therein for use in solder reflow installation and removal operations, whereby damage to the integrated circuit package or integrated circuit element is minimized by controlling the temperature rise to only those levels necessary to cause solder to melt and flow.
- Yet a further object of the invention is to provide an improved integrated circuit package having an externally controlled circuit element that includes a resistive element integrated therein, capable of raising the integrated circuit to a predetermined temperature causing solder reflow, whereby the integrated circuit package can reliably be removed and reinstalled in a system without having to make physical contact with the interconnection pins with a heating element.
- FIG. 1 is a three-dimensional view of the integrated circuit package that incorporates the additional circuit element externally controlled as a heat generating circuit of the present invention.
- FIG. 2 is a sectional view taken along line 2--2 and FIG. 1, and illustrates the layered structure of the integrated circuit package.
- FIG. 3 is a bottom plan view of the integrated circuit package.
- FIG. 4 is an illustrative plan view of a first metallic layer.
- FIG. 5 is an illustrative plan view of a second metallic layer.
- FIG. 6 is an illustrative plan view of a third metallic layer utilized for bonding of the package terminals to the terminals of the integrated circuit.
- FIG. 7 is an illustrative plan view of a fourth metallic layer.
- FIG. 8 is a plan view of a fifth metallic layer and illustrates the serpentine pattern of the additional circuit element of the subject invention.
- FIG. 9 is an illustrative plan view of a sixth metallic layer.
- FIG. 10 is a simplified schematic diagram of a system for applying external power to the integrated circuit package for raising its temperature.
- FIG. 1 is a three-dimensional view of the integrated circuit package that incorporates the additional circuit element externally controlled as a heat generating circuit of the present invention.
- the body 10 is comprised of a plurality of layers of alumina ceramic, each having patterns of conductive material coated thereon.
- a plurality of edge slots 14 are adapted for interconnection with conductive pins 16, each of the pins being soldered in a respectively associated slot 14.
- the pins 16 are utilized for making interconnection to the integrated circuit chip supported in the integrated circuit package, as will be described in more detail below, to the printed circuit assembly for making circuit interconnections between integrated circuits.
- pin electrical interconnection is known and will not be described further, it being understood that the present invention relates to solder reflow interconnection or removal of the integrated circuit package 10 in connection with the pins 16.
- An exposed conductive surface 20 is deposited on the upper layer of the integrated circuit package 10, and in this configuration is utilized for establishing ground connection to the integrated circuit package during testing of the part.
- Interconnection tabs 22 are also deposited on the upper surface of integrated circuit package 10, and form structural support and electrical interconnection for mounting to the pin 16 along the sides of the integrated circuit housing.
- Apertures 24 and 26 provide access to the additional circuit element (not shown) that forms the heat generating element, and that is embedded within the integrated circuit package. Aperture 24 and 26 comprise the points of physical access at which power is applied to the additional circuit element when reflow soldering is desired.
- FIG. 2 is a sectional view taken along line 2--2 in FIG. 1, and illustrates the layered structure of the integrated circuit package.
- a printed circuit support assembly with edge, pins 16 and hidden pins 30 soldered thereto by solder connections 32. It should be understood that only a limited number of the pins 16 and the hidden pins 30 are shown, and that in actual use, there would be many more such pins.
- the integrated circuit package 10 has a first ceramic layer 34, a second ceramic layer 36, a third ceramic layer 38, a fourth ceramic layer 40, and a fifth ceramic layer 42.
- the number of layers can vary in different packages. In the configuration illustrated, there are six metal layers 44, 46, 48, 50, 52, and 54, interleaved with the ceramic layers.
- the additional circuit element used as the heat generating element when external power is applied is situated in metallic layer 52.
- Aperture 26 (and 24) provides opening (s) for physical access through ceramic substrate 42 to the surface of the additional circuit element that forms the heat generating resistive element in metallic layer 52, such that external electrical power can be applied thereto.
- An integrated circuit chip 56 is mounted within cavity 58, and when mounted in place is covered by lid 60.
- the solder joints 62 are selected to melt and flow by application of heat at a first temperature.
- the first temperature is selected in a range of 180° Centigrade to 190° Centigrade, and nominally is selected at 183° Centigrade.
- the second solder step at solder interconnection 64 is for holding lid 60 in place, and is selected to be a solder connection that will melt and flow at a temperature higher than the first temperature.
- the solder connection 64 is selected to have a nominal solder melt and flow temperature at 280° Centigrade.
- the connection of the integrated circuit die 56 to the fourth metallic layer 50 is by solder connections 65, and is selected to require the highest application of temperature to cause the solder to melt and flow.
- solder for making solder connections 65 is selected to require temperatures in the range of 370° Centigrade.
- the solder selected for making solder connections 32 is the same as that used on solder connections 32.
- Solder connections 62 do not melt during application of heat to the package 10 because the edge pins 16 and the hidden pins 30 do not conduct enough heat to the printed circuit board 28. This is desirable since the removal of the pins from board 28 results in a very difficult task of reinsertion for normal integrated circuit chip rework. Instead soldered bonds 62 melt and allow the removal (or reconnection) of package 10 from the pins 16 and 30. After the die 56 is soldered to layer 50, its terminals are wire bonded to the tabs and layer 48.
- the ceramic layers 34, 36, 38, 40 and 42 are selected as aluminum oxide.
- the manufacturing of the total assembly is through a process known in the art which includes depositing the predetermined patterns of conductive materials on the surfaces of the ceramic substrates, assembling the substrates thus processed in the form of the integrated circuit package, and co-firing the entire combination of elements. The co-firing results in the levels bonding to one another, and the body 10 becoming a unitary block structure.
- Known processes are utilized to coat exposed electrical conductive elements with gold plate. It should be understood also, that various portions of the metalized layers 44, 46, 48, 50 and 54 are deposited, depending upon the nature of the integrated circuit that is being interconnected. It is essential, however, that the additional circuit element that forms the heat producing element deposited in metallic layer 52 be maintained electrically insulated from the other conductive paths within the integrated circuit package.
- FIG. 3 is a bottom plan view of the integrated circuit package 10.
- the cover 60 is removed, thereby exposing a cavity 58 in which the integrated circuit die would be situated.
- Metal layer 44 is shown surrounding the cavity 58 and is utilized to provide power V CC .
- Pin openings 14' for edge pins 16 and 30' for hidden pins 30 are shown for receiving associated pins.
- a portion of the third metallic layer 48 is shown comprising the bonding to the leads of the integrated circuit die.
- Power pins V CC , V CCO , and V EE are shown for illustrative purposes, it being understood that various other configurations of power and signal pins can be implemented.
- the dimensions of the integrated circuit package 10 has a length L of 0.7 inch, and a width W of 0.4 inch.
- the opening of cavity 58 has a length L' of 0.245 inch, and a width W' of 0.205 inch. It is of course understood that these dimensions are illustrative only for purposes of demonstrating the small size of the integrated circuit package. Many other size configurations and combinations of metallic layers can be utilized in combination with the additional circuit element that forms the heat producing element deposited in metallic layer 52.
- FIG. 4 is an illustrative plan view of the first metallic layer 44, and illustrates the power interconnection points V CC .
- FIG. 5 is an illustrative view of the second metallic layer 46, and illustrates the power connections V CCO .
- FIG. 6 is an illustrative view of the third metallic layer 48 utilized for bonding to the terminals of the integrated circuit die (not shown) in the vicinity of cavity 58, and making electrical interconnections to the outer periphery at bonding points 14' and to bond to the hidden pins 30 at bonding points 30".
- FIG. 7 is an illustrative plan view of the fourth metallic layer 48, and illustrates the power connection V EE .
- FIG. 8 is a plan view of the fifth metallic layer 52, and illustrates the serpentine pattern of the additional circuit element that is a continuous electrically conductive circuit connection between contact pads 24' and 26'.
- the contact pads 24' and 26' are physically accessible through apertures 24 and 26, as previously described, for purposes of applying electrical power from an external source (not shown).
- the element 52 is primarily electrically resistive and is nominally constructed to exhibit approximately 4.5 Ohms resistance at 23° Centigrade to approximately 8 Ohms at 230° Centigrade, and is designed to attain a temperature of approximately 200° Centigrade with the application of approximately 10 watts of power, and preferably not more than 15 watts of power.
- the additional circuit element 52 is constructed from a refractory metal, otherwise referred to as high temperature metals.
- FIG. 9 is an illustrative plan view of the sixth metallic layer 54 with surface 20 being maintained at power potential V CC through a vertical interconnection (not shown) with the first metallic layer 44. Conductive tabs 22 are in electrical contact with slots 14 for making interconnection with edge pins 16.
- the six metallic layers illustrated in FIG. 4 through FIG. 9, are each deposited on associated ceramic substrates, which substrates are then stacked and subjected to co-firing for bonding into a unitary integrated circuit package.
- greater or fewer metallic layers can be utilized with the inventive integral heating element, and that other configurations of the metallic layers can be utilized for interconnection with different selections of integrated circuit dies.
- the resistance of additional circuit element 52 in combination with the applied power can vary without departing from the scope of the invention, for integrated circuit package embodiments that are different from that of the illustrated preferred embodiment, or for use with solders having reflow temperatures different from those described.
- FIG. 10 is a simplified schematic diagram of a system for applying external power to the integrated circuit package for raising its temperature.
- a source of power 70 is coupled to transformer T which has its secondary 72 coupled to a Rectifier and Control circuit 74.
- the Rectifier and Control circuit 74 functions to establish a voltage level that is compatible with providing the low wattage output across lines 76 and 78.
- a switch SW-1 has one terminal 80 coupled to line 76 and a second terminal 82 coupled via line 84 through insulated probe handle 86 to probe contact 88.
- Line 78 is coupled through probe handle 86 to probe contact 90.
- Probe contacts 88 and 90 are held in spaced apart relationship for cooperation with apertures 24 and 26 in accessing and making electrical contact with contact tabs 24' and 26'.
- the arrangement is such that the probe contacts 88 and 90 are placed in contact with tabs 26' and 24' respectively, and switch SW-1 is then closed for applying electrical power thereto.
- the power is dissipated across additional circuit element 52 and its resistive characteristics generates the levels of heat previously described. It can be seen that the use of the integral additional circuit element 52 in combination with the external power source causes heating while it eliminates the thermal shock to the integrated circuit package inherent in the use of application of heat from a contact source, such as a soldering iron, directly to the integrated circuit package.
Abstract
Description
Claims (14)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/395,551 US4561006A (en) | 1982-07-06 | 1982-07-06 | Integrated circuit package with integral heating circuit |
JP58120424A JPS5922392A (en) | 1982-07-06 | 1983-07-04 | Integrated circuit package with integrated heating circuit, method of producing same and method of soldering by reflow of same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/395,551 US4561006A (en) | 1982-07-06 | 1982-07-06 | Integrated circuit package with integral heating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
US4561006A true US4561006A (en) | 1985-12-24 |
Family
ID=23563527
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US06/395,551 Expired - Fee Related US4561006A (en) | 1982-07-06 | 1982-07-06 | Integrated circuit package with integral heating circuit |
Country Status (2)
Country | Link |
---|---|
US (1) | US4561006A (en) |
JP (1) | JPS5922392A (en) |
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3639420A1 (en) * | 1985-11-20 | 1987-05-27 | Kollmorgen Tech Corp | ELECTRICAL CONNECTING COMPONENT AND METHOD FOR THE PRODUCTION THEREOF |
US4798439A (en) * | 1985-03-29 | 1989-01-17 | British Telecommunications, Plc | Optical component mounting |
US4802099A (en) * | 1986-01-03 | 1989-01-31 | International Business Machines Corporation | Physical parameter balancing of circuit islands in integrated circuit wafers |
US4839717A (en) * | 1986-12-19 | 1989-06-13 | Fairchild Semiconductor Corporation | Ceramic package for high frequency semiconductor devices |
US4908696A (en) * | 1986-09-19 | 1990-03-13 | Hitachi, Ltd. | Connector and semiconductor device packages employing the same |
DE3931634A1 (en) * | 1989-09-22 | 1991-04-04 | Telefunken Electronic Gmbh | SEMICONDUCTOR COMPONENT |
US5027191A (en) * | 1989-05-11 | 1991-06-25 | Westinghouse Electric Corp. | Cavity-down chip carrier with pad grid array |
US5047837A (en) * | 1988-08-15 | 1991-09-10 | Hitachi, Ltd. | Semiconductor device with heat transfer cap |
US5098864A (en) * | 1989-11-29 | 1992-03-24 | Olin Corporation | Process for manufacturing a metal pin grid array package |
US5103292A (en) * | 1989-11-29 | 1992-04-07 | Olin Corporation | Metal pin grid array package |
EP0493089A1 (en) * | 1990-12-25 | 1992-07-01 | Ngk Insulators, Ltd. | Wafer heating apparatus and method for producing the same |
US5173767A (en) * | 1990-05-28 | 1992-12-22 | Siemens Aktiengesellschaft | Integrated circuit housing composed of three coated, dielectric plates |
US5177595A (en) * | 1990-10-29 | 1993-01-05 | Hewlett-Packard Company | Microchip with electrical element in sealed cavity |
US5360942A (en) * | 1993-11-16 | 1994-11-01 | Olin Corporation | Multi-chip electronic package module utilizing an adhesive sheet |
US5485039A (en) * | 1991-12-27 | 1996-01-16 | Hitachi, Ltd. | Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a second main surface |
US5735450A (en) * | 1996-06-21 | 1998-04-07 | International Business Machines Corporation | Apparatus and method for heating a board-mounted electrical module for rework |
US5841190A (en) * | 1995-05-19 | 1998-11-24 | Ibiden Co., Ltd. | High density multi-layered printed wiring board, multi-chip carrier and semiconductor package |
US6163456A (en) * | 1998-01-30 | 2000-12-19 | Taiyo Yuden, Co., Ltd. | Hybrid module and methods for manufacturing and mounting thereof |
US6201300B1 (en) * | 1998-04-22 | 2001-03-13 | World Wiser Electronics Inc. | Printed circuit board with thermal conductive structure |
US6288560B1 (en) * | 1999-07-30 | 2001-09-11 | Credence Systems Corporation | Self-soldering integrated circuit probe assembly |
US6292365B1 (en) * | 1998-09-18 | 2001-09-18 | Hitachi, Ltd. | Electronic apparatus |
US20020158330A1 (en) * | 2001-04-30 | 2002-10-31 | Ho-Jeong Moon | Circuit board having a heating means and a hermetically sealed multi-chip package |
US20050151161A1 (en) * | 1999-09-24 | 2005-07-14 | Rainer Topp | Electronic assembly |
US20100007367A1 (en) * | 2008-07-14 | 2010-01-14 | Honeywell International Inc. | Packaged Die Heater |
WO2012101611A1 (en) * | 2011-01-30 | 2012-08-02 | Koninklijke Philips Electronics N.V. | Printed circuit board assembly |
US20140043772A1 (en) * | 2012-08-07 | 2014-02-13 | Hosiden Corporation | Device module and method of manufacturing the same |
US20140043771A1 (en) * | 2012-08-07 | 2014-02-13 | Hosiden Corporation | Device module and method of manufacturing the same |
US20140048241A1 (en) * | 2012-08-20 | 2014-02-20 | Shih-Yao Li | Heat sink assembly |
US9125301B2 (en) | 2011-10-18 | 2015-09-01 | Integrated Microwave Corporation | Integral heater assembly and method for carrier or host board of electronic package assembly |
US20150311135A1 (en) * | 2014-04-23 | 2015-10-29 | Fujitsu Limited | Semiconductor device and electronic device |
US20170179066A1 (en) * | 2015-12-18 | 2017-06-22 | Russell S. Aoki | Bulk solder removal on processor packaging |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH0787221B2 (en) * | 1987-02-27 | 1995-09-20 | イビデン株式会社 | Semiconductor mounting board |
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US3419767A (en) * | 1965-12-08 | 1968-12-31 | Telefunken Patent | Controllable electrical resistance |
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JPS51144182A (en) * | 1975-06-05 | 1976-12-10 | Mitsubishi Electric Corp | Indirectly heated semiconductor unit |
JPS54137660A (en) * | 1978-04-17 | 1979-10-25 | Kyoto Ceramic | Ceramic printed board for integrated circuit |
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US3289046A (en) * | 1964-05-19 | 1966-11-29 | Gen Electric | Component chip mounted on substrate with heater pads therebetween |
US3444399A (en) * | 1965-09-24 | 1969-05-13 | Westinghouse Electric Corp | Temperature controlled electronic devices |
US3419767A (en) * | 1965-12-08 | 1968-12-31 | Telefunken Patent | Controllable electrical resistance |
US3551645A (en) * | 1968-02-15 | 1970-12-29 | Milton Stoll | Heater for sealing flat-packs and the like |
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Cited By (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4798439A (en) * | 1985-03-29 | 1989-01-17 | British Telecommunications, Plc | Optical component mounting |
DE3639420A1 (en) * | 1985-11-20 | 1987-05-27 | Kollmorgen Tech Corp | ELECTRICAL CONNECTING COMPONENT AND METHOD FOR THE PRODUCTION THEREOF |
US4802099A (en) * | 1986-01-03 | 1989-01-31 | International Business Machines Corporation | Physical parameter balancing of circuit islands in integrated circuit wafers |
US4908696A (en) * | 1986-09-19 | 1990-03-13 | Hitachi, Ltd. | Connector and semiconductor device packages employing the same |
US4839717A (en) * | 1986-12-19 | 1989-06-13 | Fairchild Semiconductor Corporation | Ceramic package for high frequency semiconductor devices |
US5047837A (en) * | 1988-08-15 | 1991-09-10 | Hitachi, Ltd. | Semiconductor device with heat transfer cap |
US5027191A (en) * | 1989-05-11 | 1991-06-25 | Westinghouse Electric Corp. | Cavity-down chip carrier with pad grid array |
DE3931634A1 (en) * | 1989-09-22 | 1991-04-04 | Telefunken Electronic Gmbh | SEMICONDUCTOR COMPONENT |
US5098864A (en) * | 1989-11-29 | 1992-03-24 | Olin Corporation | Process for manufacturing a metal pin grid array package |
US5103292A (en) * | 1989-11-29 | 1992-04-07 | Olin Corporation | Metal pin grid array package |
US5173767A (en) * | 1990-05-28 | 1992-12-22 | Siemens Aktiengesellschaft | Integrated circuit housing composed of three coated, dielectric plates |
US5177595A (en) * | 1990-10-29 | 1993-01-05 | Hewlett-Packard Company | Microchip with electrical element in sealed cavity |
EP0493089A1 (en) * | 1990-12-25 | 1992-07-01 | Ngk Insulators, Ltd. | Wafer heating apparatus and method for producing the same |
US5280156A (en) * | 1990-12-25 | 1994-01-18 | Ngk Insulators, Ltd. | Wafer heating apparatus and with ceramic substrate and dielectric layer having electrostatic chucking means |
US5485039A (en) * | 1991-12-27 | 1996-01-16 | Hitachi, Ltd. | Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a second main surface |
US5360942A (en) * | 1993-11-16 | 1994-11-01 | Olin Corporation | Multi-chip electronic package module utilizing an adhesive sheet |
US5841190A (en) * | 1995-05-19 | 1998-11-24 | Ibiden Co., Ltd. | High density multi-layered printed wiring board, multi-chip carrier and semiconductor package |
US5735450A (en) * | 1996-06-21 | 1998-04-07 | International Business Machines Corporation | Apparatus and method for heating a board-mounted electrical module for rework |
US6163456A (en) * | 1998-01-30 | 2000-12-19 | Taiyo Yuden, Co., Ltd. | Hybrid module and methods for manufacturing and mounting thereof |
KR100563122B1 (en) * | 1998-01-30 | 2006-03-21 | 다이요 유덴 가부시키가이샤 | Hybrid module and methods for manufacturing and mounting thereof |
CN1319422C (en) * | 1998-01-30 | 2007-05-30 | 太阳诱电株式会社 | Hybrid module and making method thereof and mounting method thereof |
US6201300B1 (en) * | 1998-04-22 | 2001-03-13 | World Wiser Electronics Inc. | Printed circuit board with thermal conductive structure |
US6292365B1 (en) * | 1998-09-18 | 2001-09-18 | Hitachi, Ltd. | Electronic apparatus |
US6288560B1 (en) * | 1999-07-30 | 2001-09-11 | Credence Systems Corporation | Self-soldering integrated circuit probe assembly |
US7138708B2 (en) * | 1999-09-24 | 2006-11-21 | Robert Bosch Gmbh | Electronic system for fixing power and signal semiconductor chips |
US20050151161A1 (en) * | 1999-09-24 | 2005-07-14 | Rainer Topp | Electronic assembly |
US20020158330A1 (en) * | 2001-04-30 | 2002-10-31 | Ho-Jeong Moon | Circuit board having a heating means and a hermetically sealed multi-chip package |
US7692291B2 (en) * | 2001-04-30 | 2010-04-06 | Samsung Electronics Co., Ltd. | Circuit board having a heating means and a hermetically sealed multi-chip package |
US20100007367A1 (en) * | 2008-07-14 | 2010-01-14 | Honeywell International Inc. | Packaged Die Heater |
US7965094B2 (en) | 2008-07-14 | 2011-06-21 | Honeywell International Inc. | Packaged die heater |
US9113584B2 (en) | 2011-01-30 | 2015-08-18 | Koninklijke Philips N.V. | Printed circuit board assembly |
WO2012101611A1 (en) * | 2011-01-30 | 2012-08-02 | Koninklijke Philips Electronics N.V. | Printed circuit board assembly |
US9125301B2 (en) | 2011-10-18 | 2015-09-01 | Integrated Microwave Corporation | Integral heater assembly and method for carrier or host board of electronic package assembly |
US20140043771A1 (en) * | 2012-08-07 | 2014-02-13 | Hosiden Corporation | Device module and method of manufacturing the same |
US20140043772A1 (en) * | 2012-08-07 | 2014-02-13 | Hosiden Corporation | Device module and method of manufacturing the same |
US9872409B2 (en) * | 2012-08-07 | 2018-01-16 | Hosiden Corporation | Device module and method of manufacturing the same |
US10154602B2 (en) | 2012-08-07 | 2018-12-11 | Hosiden Corporation | Method of manufacturing a device module |
US20140048241A1 (en) * | 2012-08-20 | 2014-02-20 | Shih-Yao Li | Heat sink assembly |
US20150311135A1 (en) * | 2014-04-23 | 2015-10-29 | Fujitsu Limited | Semiconductor device and electronic device |
US9627291B2 (en) * | 2014-04-23 | 2017-04-18 | Fujitsu Limited | Semiconductor device and electronic device |
US20170179066A1 (en) * | 2015-12-18 | 2017-06-22 | Russell S. Aoki | Bulk solder removal on processor packaging |
Also Published As
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JPS5922392A (en) | 1984-02-04 |
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