US4517226A - Metallization process of a wafer back - Google Patents

Metallization process of a wafer back Download PDF

Info

Publication number
US4517226A
US4517226A US06/503,255 US50325583A US4517226A US 4517226 A US4517226 A US 4517226A US 50325583 A US50325583 A US 50325583A US 4517226 A US4517226 A US 4517226A
Authority
US
United States
Prior art keywords
gold
aluminium
wafer
layer
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US06/503,255
Inventor
Livio Baldi
Aldo Maggis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS ATES Componenti Elettronici SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS ATES Componenti Elettronici SpA filed Critical SGS ATES Componenti Elettronici SpA
Assigned to SGS-ATES COMPONENTI ELETRONICI S.P.A. reassignment SGS-ATES COMPONENTI ELETRONICI S.P.A. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: BALDI, LIVIO, MAGGIS, ALDO
Application granted granted Critical
Publication of US4517226A publication Critical patent/US4517226A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/001—Interlayers, transition pieces for metallurgical bonding of workpieces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H01L21/244—Alloying of electrode materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
    • B23K35/001—Interlayers, transition pieces for metallurgical bonding of workpieces
    • B23K2035/008—Interlayers, transition pieces for metallurgical bonding of workpieces at least one of the workpieces being of silicium

Definitions

  • the present invention relates to a metallization process of the back of a silicon wafer, on which there have been realized electronic components, in order to facilitate the fixture there of on suitable headers.
  • a metallization process of known kind includes the deposition of a thin gold layer (Au) with impurity traces (silicon or boron), which is preferably alloyed by thermic treatment at eutectic temperature ( ⁇ 450° C.).
  • the alloy operation is made preferable, if not necessary, by the necessity of avoiding instability phenomena, which would change into a silicon migration through the gold layer and the consequent oxidation of the same silicon. This would affect, as known, the successive welding operation.
  • the alloy operation is cause of superficial unevenesses, which cause fluctuations of the contact resistance after the welding. Besides it is required to use greater quantities of gold with consequent additional costs.
  • Another known process includes in its turn the deposition of silicon containing aluminium (Al/Si), which is alloyed by thermic treatment at a temperature lower than the eutectic one and then receives the deposition of a thin gold layer.
  • the object of the present invention is to realize a metallization process of the back of a wafer, which results advantageous with respect to the presently known processes.
  • such an object is reached by means of a process characterized in that it comprises, in succession, the deposition of a first gold layer, the deposition of a second aluminium layer (eventually including a little percent of silicon) and the thermic treatment of the wafer with the two superimposed layers for the migration of the aluminium towards the wafer through said gold layer.
  • FIG. 1 shows a wafer after the deposition of the gold layer
  • FIG. 2 shows the same wafer after the deposition of the aluminium layer (or Al/Si);
  • FIG. 3 shows the same wafer after the thermic treatment.
  • an opportunely doped wafer 1 of the thickness (for example) of 500 ⁇ 600 micron it is first deposited (FIG. 1), by vacuum evaporation, a relatively thick gold layer 2 (for example of 0,3 micron), on which it is then deposited (FIG. 2) an aluminium layer 3 (or Al containing traces of Si, which is preferable because it is usually already available in the electronic firms), whose thickness and quantity are chosen in such a way as to avoid the formation of bad intermetallic compounds.
  • the aluminium quantity must not be greater than 50% of that of gold, and that the optimum ratio for the thickness of aluminium and gold must be about 1:6.
  • the wafer 1 with superimposed layers 2 and 3 is submitted to a thermic treatment of "annealing" at a temperature (for example ⁇ 320° C.) lower than that of the Au-Si eutectic.
  • a temperature for example ⁇ 320° C.
  • the aluminium migrates through the gold towards the silicon (arrows A of FIG. 3) and the gold migrates towards the outer surface (arrows B of FIG. 3), forming an Au-Al film 4, in which the position of gold and aluminium is practically inverted with respect to the situation of FIG. 2.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Die Bonding (AREA)

Abstract

On the back of a wafer there are deposited firstly a gold layer and then an aluminium layer (eventually including a small silicon percent). It is finally carried out a thermic treatment at low temperature, which causes the aluminium migration towards the wafer through the gold layer.

Description

The present invention relates to a metallization process of the back of a silicon wafer, on which there have been realized electronic components, in order to facilitate the fixture there of on suitable headers.
A metallization process of known kind includes the deposition of a thin gold layer (Au) with impurity traces (silicon or boron), which is preferably alloyed by thermic treatment at eutectic temperature (˜450° C.).
In such a process the alloy operation is made preferable, if not necessary, by the necessity of avoiding instability phenomena, which would change into a silicon migration through the gold layer and the consequent oxidation of the same silicon. This would affect, as known, the successive welding operation.
On the other hand, the alloy operation is cause of superficial unevenesses, which cause fluctuations of the contact resistance after the welding. Besides it is required to use greater quantities of gold with consequent additional costs.
Another known process includes in its turn the deposition of silicon containing aluminium (Al/Si), which is alloyed by thermic treatment at a temperature lower than the eutectic one and then receives the deposition of a thin gold layer.
With this process the gold quantity, and consequently the cost, is reduced and a better ohmic contact is realized. However there occurs the drawback that the aluminium tends to oxidate very quickly before the deposition of gold, worsening the Al/Au contact.
Both the processes have also the disadvantage to require thermic treatments at temperatures greater than 400° C., which determine reliability problems deriving from the formation of superficial protuberances ("hillocks") in the aluminium layers possibly present on the wafer front.
The object of the present invention is to realize a metallization process of the back of a wafer, which results advantageous with respect to the presently known processes.
According to the invention such an object is reached by means of a process characterized in that it comprises, in succession, the deposition of a first gold layer, the deposition of a second aluminium layer (eventually including a little percent of silicon) and the thermic treatment of the wafer with the two superimposed layers for the migration of the aluminium towards the wafer through said gold layer.
It has been verified that the process according to the invention offers some important advantages, which can be resumed in this way:
(a) Elimination of the Schottky barrier and consequent good ohmic Si-Al contact, mainly as a result of the fact that the aluminium tends to pass through the gold and to reach the previously doped wafer.
(b) Stabilization of the interface Si-Au, that means that the silicon does not tend to migrate towards the surface through the gold layer, thus oxidating in contact with the atmospherical oxygen.
(c) Welding ease and low electric resistance of contact, due to the fact that the migration of aluminium determines the presence of gold on the surface and at the same time prevents the aluminium oxidation. Particularly, there is made possible the direct welding, without interposition of the so called "preform" plates, to the metallic headers of the ceramic packages, with consequent cost saving.
(d) Possibility of using a thermic treatment of "annealing" at low temperature (lower than the eutectic one) which keeps the Au-Al film uniformity and avoids reliability problems. Such treatment at low temperature is made possible by the fact that there occurs the aluminium migration in the gold layer, but not the alloy formation.
(e) Scribing of the metallized wafer, resulting from the reduced strength of the Au-Al film.
An embodiment of the process according to the invention is illustrated for better clarity, but without any limiting meaning, in the enclosed drawings, in which:
FIG. 1 shows a wafer after the deposition of the gold layer;
FIG. 2 shows the same wafer after the deposition of the aluminium layer (or Al/Si);
FIG. 3 shows the same wafer after the thermic treatment.
With reference to the drawings, on the back of an opportunely doped wafer 1 of the thickness (for example) of 500÷600 micron it is first deposited (FIG. 1), by vacuum evaporation, a relatively thick gold layer 2 (for example of 0,3 micron), on which it is then deposited (FIG. 2) an aluminium layer 3 (or Al containing traces of Si, which is preferable because it is usually already available in the electronic firms), whose thickness and quantity are chosen in such a way as to avoid the formation of bad intermetallic compounds. The present experiences have shown that the aluminium quantity must not be greater than 50% of that of gold, and that the optimum ratio for the thickness of aluminium and gold must be about 1:6.
Finally the wafer 1 with superimposed layers 2 and 3 is submitted to a thermic treatment of "annealing" at a temperature (for example ˜320° C.) lower than that of the Au-Si eutectic. As consequence, the aluminium migrates through the gold towards the silicon (arrows A of FIG. 3) and the gold migrates towards the outer surface (arrows B of FIG. 3), forming an Au-Al film 4, in which the position of gold and aluminium is practically inverted with respect to the situation of FIG. 2.

Claims (6)

We claim:
1. Metallization process of a silicon wafer back, comprising, in succession, the deposition of a first gold layer, the deposition of a second layer of aluminum and the thermic treatment by annealing to temperature lower than the eutectic gold-silicon temperature of the wafer with superimposed layers whereby the aluminum migrates through the gold layer toward the wafer.
2. Process according to claim 1, characterized in that said aluminium layer containes silicon traces.
3. Process according to claim 1, characterized in that said thermic treatment is effected at a temperature lower than that of the gold-silicon eutectic.
4. Process according to claim 3, characterized in that said thermic treatment is effected at a temperature of about 320° C.
5. Process according to claim 1, characterized in that the thickness of said aluminium and gold layers is in a ratio variable about 1:6.
6. Process according to claim 1, characterized in that the quantity of aluminium is not greater than 50% of the quantity of gold.
US06/503,255 1982-07-29 1983-06-10 Metallization process of a wafer back Expired - Lifetime US4517226A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT22627/82A IT1217278B (en) 1982-07-29 1982-07-29 METALLIZATION PROCESS OF THE BACK OF A SLICE OF SILICON
IT22627A/82 1982-07-29

Publications (1)

Publication Number Publication Date
US4517226A true US4517226A (en) 1985-05-14

Family

ID=11198589

Family Applications (1)

Application Number Title Priority Date Filing Date
US06/503,255 Expired - Lifetime US4517226A (en) 1982-07-29 1983-06-10 Metallization process of a wafer back

Country Status (6)

Country Link
US (1) US4517226A (en)
JP (1) JPH0650748B2 (en)
DE (1) DE3321295A1 (en)
FR (1) FR2531106B1 (en)
GB (1) GB2125439B (en)
IT (1) IT1217278B (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5342793A (en) * 1990-02-20 1994-08-30 Sgs-Thomson Microelectronics, S.R.L. Process for obtaining multi-layer metallization of the back of a semiconductor substrate
US6461211B2 (en) 1999-06-01 2002-10-08 Micron Technology, Inc. Method of forming resistor with adhesion layer for electron emission device
US6650043B1 (en) 1999-07-20 2003-11-18 Micron Technology, Inc. Multilayer conductor structure for use in field emission display
US20040061430A1 (en) * 1999-08-26 2004-04-01 Micron Technology, Inc. Field emission device having insulated column lines and method of manufacture
US8946864B2 (en) 2011-03-16 2015-02-03 The Aerospace Corporation Systems and methods for preparing films comprising metal using sequential ion implantation, and films formed using same
US9048179B2 (en) 2009-09-14 2015-06-02 The Aerospace Corporation Systems and methods for preparing films using sequential ion implantation, and films formed using same
US9324579B2 (en) 2013-03-14 2016-04-26 The Aerospace Corporation Metal structures and methods of using same for transporting or gettering materials disposed within semiconductor substrates

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69033234T2 (en) * 1990-02-20 2000-02-03 Stmicroelectronics S.R.L., Agrate Brianza Process for multilayer metallization of the back of a semiconductor wafer

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3239376A (en) * 1962-06-29 1966-03-08 Bell Telephone Labor Inc Electrodes to semiconductor wafers
US3374112A (en) * 1964-03-05 1968-03-19 Yeda Res & Dev Method and apparatus for controlled deposition of a thin conductive layer
US3453724A (en) * 1965-04-09 1969-07-08 Rca Corp Method of fabricating semiconductor device
US3720997A (en) * 1971-01-11 1973-03-20 Motorola Inc Eutectic plating and breaking silicon wafers
JPS4813265B1 (en) * 1963-10-17 1973-04-26
US4293587A (en) * 1978-11-09 1981-10-06 Zilog, Inc. Low resistance backside preparation for semiconductor integrated circuit chips

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3647935A (en) * 1969-12-15 1972-03-07 Motorola Inc Intermetallic passivation of aluminum metallization
FR2135033B1 (en) * 1971-05-03 1973-12-28 Saint Gobain Pont A Mousson
DE2930779C2 (en) * 1978-07-28 1983-08-04 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Semiconductor device
JPS5685832A (en) * 1979-12-14 1981-07-13 Hitachi Ltd Semiconductor device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3239376A (en) * 1962-06-29 1966-03-08 Bell Telephone Labor Inc Electrodes to semiconductor wafers
JPS4813265B1 (en) * 1963-10-17 1973-04-26
US3374112A (en) * 1964-03-05 1968-03-19 Yeda Res & Dev Method and apparatus for controlled deposition of a thin conductive layer
US3453724A (en) * 1965-04-09 1969-07-08 Rca Corp Method of fabricating semiconductor device
US3720997A (en) * 1971-01-11 1973-03-20 Motorola Inc Eutectic plating and breaking silicon wafers
US4293587A (en) * 1978-11-09 1981-10-06 Zilog, Inc. Low resistance backside preparation for semiconductor integrated circuit chips

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5342793A (en) * 1990-02-20 1994-08-30 Sgs-Thomson Microelectronics, S.R.L. Process for obtaining multi-layer metallization of the back of a semiconductor substrate
US6461211B2 (en) 1999-06-01 2002-10-08 Micron Technology, Inc. Method of forming resistor with adhesion layer for electron emission device
US6657376B1 (en) 1999-06-01 2003-12-02 Micron Technology, Inc. Electron emission devices and field emission display devices having buffer layer of microcrystalline silicon
US6650043B1 (en) 1999-07-20 2003-11-18 Micron Technology, Inc. Multilayer conductor structure for use in field emission display
US20040160164A1 (en) * 1999-07-20 2004-08-19 Micron Technology, Inc. Multilayer conductor
US20040061430A1 (en) * 1999-08-26 2004-04-01 Micron Technology, Inc. Field emission device having insulated column lines and method of manufacture
US7052350B1 (en) 1999-08-26 2006-05-30 Micron Technology, Inc. Field emission device having insulated column lines and method manufacture
US7105992B2 (en) 1999-08-26 2006-09-12 Micron Technology, Inc. Field emission device having insulated column lines and method of manufacture
US20070024178A1 (en) * 1999-08-26 2007-02-01 Ammar Derraa Field emission device having insulated column lines and method of manufacture
US9048179B2 (en) 2009-09-14 2015-06-02 The Aerospace Corporation Systems and methods for preparing films using sequential ion implantation, and films formed using same
US8946864B2 (en) 2011-03-16 2015-02-03 The Aerospace Corporation Systems and methods for preparing films comprising metal using sequential ion implantation, and films formed using same
US9324579B2 (en) 2013-03-14 2016-04-26 The Aerospace Corporation Metal structures and methods of using same for transporting or gettering materials disposed within semiconductor substrates

Also Published As

Publication number Publication date
JPS5929429A (en) 1984-02-16
DE3321295C2 (en) 1989-08-03
IT8222627A0 (en) 1982-07-29
GB8315614D0 (en) 1983-07-13
GB2125439B (en) 1985-08-07
GB2125439A (en) 1984-03-07
FR2531106A1 (en) 1984-02-03
IT1217278B (en) 1990-03-22
FR2531106B1 (en) 1986-05-16
JPH0650748B2 (en) 1994-06-29
DE3321295A1 (en) 1984-02-09

Similar Documents

Publication Publication Date Title
CN86101652A (en) semiconductor chip attaching device
US6309965B1 (en) Method of producing a semiconductor body with metallization on the back side that includes a titanium nitride layer to reduce warping
JPS62287641A (en) Semiconductor device
US4517226A (en) Metallization process of a wafer back
US4042951A (en) Gold-germanium alloy contacts for a semiconductor device
US5290588A (en) TiW barrier metal process
US4065588A (en) Method of making gold-cobalt contact for silicon devices
US5614291A (en) Semiconductor device and method of manufacturing the same
GB2103420A (en) Gold-plated package for semiconductor devices
US5057454A (en) Process for producing ohmic electrode for p-type cubic system boron nitride
US4613890A (en) Alloyed contact for n-conducting GaAlAs-semi-conductor material
US3942244A (en) Semiconductor element
JP2762007B2 (en) Metal thin film laminated ceramic substrate
JPS60193337A (en) Manufacture of semiconductor device
US3401316A (en) Semiconductor device utilizing an aual2 layer as a diffusion barrier that prevents "purple plague"
KR0146356B1 (en) Brazing material for forming a bond between a semiconductor wafer and a metal contact
JPS5833833A (en) Electrode formation of semiconductor device
JP2950285B2 (en) Semiconductor element and method for forming electrode thereof
Selikson Failure mechanisms in integrated circuit interconnect systems
SU722429A1 (en) Contact pair for microwelding integrated circuits
JPH07115185A (en) Electrode of semiconductor
JPS61119049A (en) Manufacture of semiconductor device
JPH0376030B2 (en)
JPS6337497B2 (en)
JPS59227119A (en) Silicon semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: SGS-ATES COMPONENTI ELETRONICI S.P.A. STRADALE PRI

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNORS:BALDI, LIVIO;MAGGIS, ALDO;REEL/FRAME:004141/0626

Effective date: 19830509

STCF Information on status: patent grant

Free format text: PATENTED CASE

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12