US4196470A - Method and arrangement for transfer of data information to two parallelly working computer means - Google Patents
Method and arrangement for transfer of data information to two parallelly working computer means Download PDFInfo
- Publication number
- US4196470A US4196470A US05/857,254 US85725477A US4196470A US 4196470 A US4196470 A US 4196470A US 85725477 A US85725477 A US 85725477A US 4196470 A US4196470 A US 4196470A
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- United States
- Prior art keywords
- transfer
- data processor
- data
- information
- input
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
- G06F11/1691—Temporal synchronisation or re-synchronisation of redundant processing components using a quantum
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
Definitions
- the present invention refers to a method for transferring data information units, by means of transfer instructions, to two parallelly working data processor means, each executing one of two accordant instruction sequences in corresponding periods which each, due to demanded information transfers, comprises the execution of only one transfer instruction, the demands for data transfer appearing asynchronously compared with the execution of the instruction sequences, and such time displacements occuring between corresponding periods that a transfer demand is marked during periods which are not mutually correspondent.
- the invention also refers to an apparatus to perform the method.
- a single working data processor which is intended for process control in real time executes an instruction sequence which constitutes the control program of the process.
- Each of the instructions of the sequence is successively executed.
- Each instruction is carried out during an execution clock interval determined by clock pulses. Further, the instructions are carried out in an order which has to be flexible considering that data information units are received from the controlled process quite arbitrarily and are asynchronously related to the clock pulses but must be processed in real time.
- any asynchronism between the execution clock pulses of the sequence and the data information units being received from the process is rather easily mastered by the single working data processor.
- the clock pulses are used to activate the interrupt register for writing or reading, and thanks to subsequences and jump instructions--as it is generally expressed by way of introduction and as will be explained below--executing periods occur. These periods include, due to a demanded information transfer, only one transfer instruction.
- the present invention does not refer to such real-time-single working processors but proposes a method and an arrangement to transfer data information to parallelly working data processor means wherein each executor executes one instruction sequence.
- parallel working is generally known and defines the concept of two substantially identical processor means parallelly processing data information units from a single source by means of corresponding instruction sequences with the results produced by the means being continously mutually compared so that differences of the results due to equipment or program faults start a malfunction alarm. From that it follows that the working in parallel demands, for the execution of the two instruction sequences, a synchronism which absolutely comprises frequency equality of the clock pulses controlling the executions. Certainly the arrangement of delay circuits renders it possible to carry out the comparison operation in spite of a constant phase displacement between corresponding execution periods but preferably the synchronization in addition to the frequency equality should include phase coincidence as well.
- FIG. 1 shows the proposed arrangement and a buffer register from which data information groups are transferred to two parallelly working data processor means and the
- FIGS. 2 to 4 of which show timing diagrams of the execution of instruction sequences and the time-sharing of the information transfers.
- FIG. 1 two parallelly working data processor means DA and DB are indicated. Each of these means is provided with an information input II, a transfer signal input TSI and two outputs 01 and 02.
- FIG. 2 is a timing diagram showing how one of the data processor means executes portions of an instruction sequence.
- the instructions are executed in instruction execution clock time units.
- the execution clock time units for jump instructions are for example designated JIm to JIm+3.
- the jump instructions are modifiable and each terminates one instruction subsequence each.
- the number in instructions of the subsequences varies, consequently different subsequence execution times SS are obtained, in FIG. 2 it is assumed that, for example, the time SSm+3 ⁇ the time SSm+2.
- FIG. 2 shows execution periods EPn and EPn+1.
- the limit between two successive periods is passed when it is too late to modify the only jump instruction being associated with this limit so that it is jumped to a transfer subsequence which comprises a transfer instruction during the execution of which the data processor means receives a unit of data information through the information input II.
- Such modification is initiated by means of a transfer signal TS (an interrupt) which is received on the transfer signal input TSI in connection with a demanded information transfer. It is possible but not necessary that each jump instruction is allotted a period limit.
- the indication pulses IP generated in the respective data processor means are received according to FIG. 1 by two numerators NA and NB respectively.
- the numerators are counters which are set to an equal number when the processor means begin the parallel-synchronous cooperation and which then count the number of execution periods being executed in respective processor means.
- a first comparator C1 in a transfer signal generator TSG compares the count numbers being accumulated by the numerators to indicate together at an arbitrary time whether the data processor means execute the two accordant instruction sequences in corresponding or non-corresponding execution period.
- First comparator C1 is of a conventional type, which when receiving the counting numbers a and b activates either its first or second output if a ⁇ b or b ⁇ a respectively.
- the transfer signal generator TSG also comprises a reversing switch RS in order to feed a number register NR through a gate arrangement G1 with counting numbers coming either from the one or from the other of the numerators NA and NB.
- the reversing switch consists of two gate arrangements, the first of which is connected to the numerator NA and to the first output of the comparator C1 and the second of which is connected to the numerator NB and to the second comparator output of the comparator.
- the gate arrangement G1 is activated the number register NR registers the same or the larger of the counting numbers which is obtained depending on whether the two instruction sequences are executed in corresponding and non-corresponding periods, respectively.
- the transfer signal generator TSG also includes two second comparators C2A and C2B each having its first input connected to one of numerators and its output connected to the transfer signal input TS1 of that data processor means which feeds this numerator, and its second input connected through a gate arrangement G2 to the output of the number register NR.
- the comparators C2A and C2B are of a conventional type, the output of which being activated for equal input values.
- FIG. 1 also shows an information buffer register IB of the known "first in-first out" or FIFO type in which data information units coming in at arbitrary times are buffer stored.
- the buffer register IB is provided with an indication output X which is activated if at least one information unit is stored.
- the data information units are transferred through a gate arrangement G3 to an information register IR in an information registration unit IRU and from there through two gate arrangements GA and GB to the information inputs II of the data processor means DA and DB.
- the indication output X is also connected to the information registration unit, more precisely to the first input of a gate G4 the second input of which is activated by means of a gate G5 only if the two flip-flops FFA and FFB take the same stable first state s1.
- each of the flip-flops FFA and FFB is provided with a first input which is activated by the trailing edge of a signal and which together with the control input of the respective gate arrangements GA and GB is connected to output 01 of the data processor means DA, respectively DB.
- the gate G4 has its output connected to gate arrangement G3 and to the second inputs of the flip-flops FFA and FFB.
- the information registration unit therefore performs the following function: On condition that the transfer of a first data information unit to the processor means is finished and that the buffer register stores a second data information unit, the second information unit is registered in the information register IR from which it is read by means of gate arrangements GA and GB, which are activated when the processor means executes a transfer instruction allotted to this second information unit.
- gate G5 of the information registration unit IRU is deactivated and remains deactivated during the whole of the associated transfer operation but is activated, at least for a short while, when a transfer operation is finished.
- this operation of the gate G5 is utilized by using its logic ZEROS as marking signals, each belonging to a registration in the information register and each controlling gate arrangements G1 and G2 of the transfer signal generator TSG. Consequently a marking of an information transfer demand stops the transfer of the counting numbers to the number register NR, the contents of which during the associated transfer operation being designated as transfer number t.
- the second comparators C2A and C2B compare the instantaneous counting numbers a and b obtained from the numerators NA, NB to the transfer number only, and so two transfer signals belonging to the respective transfer operation are generated, and the data processor means DA and DB, independently of a relative phase displacement, receive separately the transfer signals during the execution period being determined by means of the transfer number t.
- FIG. 3 contains a number of timing diagrams showing an example of how to transfer, by means of the above mentioned arrangement, data information groups to two parallel-synchronously cooperating processor means the coincident start of which, in order to execute accordant instruction sequencies, appear from coincident execution periods having the counting number 0 in the two execution timing diagrams designated EA and EB.
- a phase displacement td arises between execution periods with corresponding counting numbers.
- Such phase displacement results in that the counting numbers being registered according to the timing diagram RN in the number register until the beginning of the period being determined by means of the counting number n+3 coincide with corresponding counting numbers according to the diagram EA.
- a marking timing diagram M and a buffer-in timing diagram BI show that the gate G5 in the information registration unit IRU is activated until two data information units at the instants D1 and D2 come to the buffer register shortly after each other during the execution period having the counting number n+3 in the diagram EA.
- the first incoming information unit is immediately registered in the information register IR while the latter is buffer stored in the buffer register IB.
- n+3 becomes the transfer number t1 which belongs to the instant D1 and which is compared to the counting numbers according to the diagrams EA and EB.
- the comparator C2A generates, immediately after the first information registration, a transfer signal TS1A shown in a timing diagram TSA for transfer signals to the data processor means DA.
- this transfer instruction By means of this transfer instruction is selected, the execution clock time unit TI1A of which is included according to the timing diagram EA in the execution period having a counting number n+4.
- a transfer signal TSIB is transferred according to the timing diagram TSB for transfer signals to the data processor means.
- DB Signal TSIB causes a transfer instruction to be executed during an execution clock time unit TI1B being shown in the timing diagram EB.
- gate arrangements GA and GB respectively are activated through the outputs 01 of the processor means in order to transfer to the processor means the information unit which has come in first.
- the gate G5 is activated at the end of the execution clock unit TI1B but for only a short while because the buffer register still stores the second data information unit which has come in at the instant D2 and which is now registered in the information register IR.
- the timing diagram RN for registered counting numbers shows that the short activation of gate G5 results in that number n+4 is registered as transfer number t2 which belongs to the second information unit having come at instant D2.
- both numerators NA and NB contain the counting number n+4 and therefore the timing diagrams TSA and TSB show second transfer signals TS2A and TS2B with coincident leading edges.
- transfer instructions are selected whose execution clock time units TI2A and TI2B according to the timing diagrams EA and EB are included in the respective transfer execution period having the counting number n+5.
- the timing diagram M shows that the marking signal for the second information transfer finishes at the same time as the transfer execution clock time unit TI2B which causes according to the time diagram RN the number register to register n+6 as the instantaneously larger counting number according to the time diagrams EA and EB.
- the use of the now described method and arrangement guarantees the quickest possible transfer operations and that the instruction sequences of the processor means remain accordant independent of asynchronism between the demands for information transfer and the instruction executions, and above all independent of phase dispacements between the instruction executions of the processor means.
- the data processor means DA and DB according to FIG. 1 should be designed in such a way that the numerators NA and NB do not count the execution periods EP being defined by means of FIG. 2, but instead that executed subsequences are counted then the transfer number being generated in the transfer signal generator TSG is modified by means of a conventional +1-adder which is series connected to the number register NR.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE7614222 | 1976-12-17 | ||
SE7614222A SE397013B (sv) | 1976-12-17 | 1976-12-17 | Sett och anordning for att overfora datainformationer till tva parallellt arbetande datamaskindelar |
Publications (1)
Publication Number | Publication Date |
---|---|
US4196470A true US4196470A (en) | 1980-04-01 |
Family
ID=20329777
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US05/857,254 Expired - Lifetime US4196470A (en) | 1976-12-17 | 1977-12-05 | Method and arrangement for transfer of data information to two parallelly working computer means |
Country Status (14)
Country | Link |
---|---|
US (1) | US4196470A (fr) |
AU (1) | AU515012B2 (fr) |
BR (1) | BR7708274A (fr) |
CA (1) | CA1087747A (fr) |
ES (1) | ES465171A1 (fr) |
FR (1) | FR2374693A1 (fr) |
GB (1) | GB1565320A (fr) |
HU (1) | HU177434B (fr) |
IT (1) | IT1089170B (fr) |
MX (1) | MX143306A (fr) |
NL (1) | NL7713910A (fr) |
SE (1) | SE397013B (fr) |
SU (1) | SU733525A3 (fr) |
YU (1) | YU298177A (fr) |
Cited By (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4399504A (en) * | 1980-10-06 | 1983-08-16 | International Business Machines Corporation | Method and means for the sharing of data resources in a multiprocessing, multiprogramming environment |
EP0104490A2 (fr) * | 1982-09-28 | 1984-04-04 | Fried. Krupp Gesellschaft mit beschränkter Haftung | Méthode et dispositif pour la synchronisation de système de traitement de données |
EP0164414A1 (fr) * | 1983-12-12 | 1985-12-18 | Parallel Computers, Inc. | Controleur de processeur d'ordinateur |
US4703421A (en) * | 1986-01-03 | 1987-10-27 | Gte Communication Systems Corporation | Ready line synchronization circuit for use in a duplicated computer system |
US5068780A (en) * | 1989-08-01 | 1991-11-26 | Digital Equipment Corporation | Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones |
US5153881A (en) * | 1989-08-01 | 1992-10-06 | Digital Equipment Corporation | Method of handling errors in software |
US5163138A (en) * | 1989-08-01 | 1992-11-10 | Digital Equipment Corporation | Protocol for read write transfers via switching logic by transmitting and retransmitting an address |
US5175847A (en) * | 1990-09-20 | 1992-12-29 | Logicon Incorporated | Computer system capable of program execution recovery |
US5185877A (en) * | 1987-09-04 | 1993-02-09 | Digital Equipment Corporation | Protocol for transfer of DMA data |
US5251227A (en) * | 1989-08-01 | 1993-10-05 | Digital Equipment Corporation | Targeted resets in a data processor including a trace memory to store transactions |
US5255367A (en) * | 1987-09-04 | 1993-10-19 | Digital Equipment Corporation | Fault tolerant, synchronized twin computer system with error checking of I/O communication |
GB2340627A (en) * | 1998-08-13 | 2000-02-23 | Plessey Telecomm | Two-processor lockstep arrangement for fault monitoring incorporates delay |
US6247144B1 (en) * | 1991-01-31 | 2001-06-12 | Compaq Computer Corporation | Method and apparatus for comparing real time operation of object code compatible processors |
US20020010880A1 (en) * | 1998-06-30 | 2002-01-24 | Sun Microsystems, Inc. | Determinism in a multiprocessor computer system and monitor and processor therefor |
US20050060605A1 (en) * | 2003-09-16 | 2005-03-17 | Gibart Anthony Gerard | High speed synchronization in dual-processor safety controller |
US7185184B1 (en) * | 1999-10-06 | 2007-02-27 | Infineon Technologies Ag | Processor system, especially a processor system for communications devices |
US20110078246A1 (en) * | 2009-09-28 | 2011-03-31 | Bjorn Michael Dittmer-Roche | System and method of simultaneous collaboration |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4541094A (en) * | 1983-03-21 | 1985-09-10 | Sequoia Systems, Inc. | Self-checking computer circuitry |
AU568977B2 (en) * | 1985-05-10 | 1988-01-14 | Tandem Computers Inc. | Dual processor error detection system |
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US3303474A (en) * | 1963-01-17 | 1967-02-07 | Rca Corp | Duplexing system for controlling online and standby conditions of two computers |
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US3909795A (en) * | 1973-08-31 | 1975-09-30 | Gte Automatic Electric Lab Inc | Program timing circuitry for central data processor of digital communications system |
US3913074A (en) * | 1973-12-18 | 1975-10-14 | Honeywell Inf Systems | Search processing apparatus |
US3931505A (en) * | 1974-03-13 | 1976-01-06 | Bell Telephone Laboratories, Incorporated | Program controlled data processor |
US4020459A (en) * | 1975-10-28 | 1977-04-26 | Bell Telephone Laboratories, Incorporated | Parity generation and bus matching arrangement for synchronized duplicated data processing units |
US4021784A (en) * | 1976-03-12 | 1977-05-03 | Sperry Rand Corporation | Clock synchronization system |
-
1976
- 1976-12-17 SE SE7614222A patent/SE397013B/xx unknown
-
1977
- 1977-12-05 US US05/857,254 patent/US4196470A/en not_active Expired - Lifetime
- 1977-12-07 GB GB51033/77A patent/GB1565320A/en not_active Expired
- 1977-12-07 AU AU31300/77A patent/AU515012B2/en not_active Expired
- 1977-12-08 MX MX171635A patent/MX143306A/es unknown
- 1977-12-09 HU HU77EI773A patent/HU177434B/hu unknown
- 1977-12-13 BR BR7708274A patent/BR7708274A/pt unknown
- 1977-12-15 YU YU02981/77A patent/YU298177A/xx unknown
- 1977-12-15 NL NL7713910A patent/NL7713910A/xx not_active Application Discontinuation
- 1977-12-16 ES ES465171A patent/ES465171A1/es not_active Expired
- 1977-12-16 SU SU772555303A patent/SU733525A3/ru active
- 1977-12-16 IT IT30807/77A patent/IT1089170B/it active
- 1977-12-16 FR FR7738074A patent/FR2374693A1/fr active Granted
- 1977-12-16 CA CA293,201A patent/CA1087747A/fr not_active Expired
Patent Citations (9)
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US3303474A (en) * | 1963-01-17 | 1967-02-07 | Rca Corp | Duplexing system for controlling online and standby conditions of two computers |
US3252149A (en) * | 1963-03-28 | 1966-05-17 | Digitronics Corp | Data processing system |
US3864670A (en) * | 1970-09-30 | 1975-02-04 | Yokogawa Electric Works Ltd | Dual computer system with signal exchange system |
US3898621A (en) * | 1973-04-06 | 1975-08-05 | Gte Automatic Electric Lab Inc | Data processor system diagnostic arrangement |
US3909795A (en) * | 1973-08-31 | 1975-09-30 | Gte Automatic Electric Lab Inc | Program timing circuitry for central data processor of digital communications system |
US3913074A (en) * | 1973-12-18 | 1975-10-14 | Honeywell Inf Systems | Search processing apparatus |
US3931505A (en) * | 1974-03-13 | 1976-01-06 | Bell Telephone Laboratories, Incorporated | Program controlled data processor |
US4020459A (en) * | 1975-10-28 | 1977-04-26 | Bell Telephone Laboratories, Incorporated | Parity generation and bus matching arrangement for synchronized duplicated data processing units |
US4021784A (en) * | 1976-03-12 | 1977-05-03 | Sperry Rand Corporation | Clock synchronization system |
Cited By (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4399504A (en) * | 1980-10-06 | 1983-08-16 | International Business Machines Corporation | Method and means for the sharing of data resources in a multiprocessing, multiprogramming environment |
EP0104490A2 (fr) * | 1982-09-28 | 1984-04-04 | Fried. Krupp Gesellschaft mit beschränkter Haftung | Méthode et dispositif pour la synchronisation de système de traitement de données |
EP0104490A3 (fr) * | 1982-09-28 | 1987-04-08 | Fried. Krupp Gesellschaft mit beschränkter Haftung | Méthode et dispositif pour la synchronisation de système de traitement de données |
EP0164414A1 (fr) * | 1983-12-12 | 1985-12-18 | Parallel Computers, Inc. | Controleur de processeur d'ordinateur |
EP0164414A4 (fr) * | 1983-12-12 | 1986-06-05 | Parallel Computers Inc | Controleur de processeur d'ordinateur. |
US4703421A (en) * | 1986-01-03 | 1987-10-27 | Gte Communication Systems Corporation | Ready line synchronization circuit for use in a duplicated computer system |
US5185877A (en) * | 1987-09-04 | 1993-02-09 | Digital Equipment Corporation | Protocol for transfer of DMA data |
US5255367A (en) * | 1987-09-04 | 1993-10-19 | Digital Equipment Corporation | Fault tolerant, synchronized twin computer system with error checking of I/O communication |
US5068780A (en) * | 1989-08-01 | 1991-11-26 | Digital Equipment Corporation | Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones |
US5163138A (en) * | 1989-08-01 | 1992-11-10 | Digital Equipment Corporation | Protocol for read write transfers via switching logic by transmitting and retransmitting an address |
US5251227A (en) * | 1989-08-01 | 1993-10-05 | Digital Equipment Corporation | Targeted resets in a data processor including a trace memory to store transactions |
US5153881A (en) * | 1989-08-01 | 1992-10-06 | Digital Equipment Corporation | Method of handling errors in software |
US5175847A (en) * | 1990-09-20 | 1992-12-29 | Logicon Incorporated | Computer system capable of program execution recovery |
US6247144B1 (en) * | 1991-01-31 | 2001-06-12 | Compaq Computer Corporation | Method and apparatus for comparing real time operation of object code compatible processors |
US20020010880A1 (en) * | 1998-06-30 | 2002-01-24 | Sun Microsystems, Inc. | Determinism in a multiprocessor computer system and monitor and processor therefor |
US7155704B2 (en) | 1998-06-30 | 2006-12-26 | Sun Microsystems, Inc. | Determinism in a multiprocessor computer system and monitor and processor therefor |
GB2340627B (en) * | 1998-08-13 | 2000-10-04 | Plessey Telecomm | Data processing system |
GB2340627A (en) * | 1998-08-13 | 2000-02-23 | Plessey Telecomm | Two-processor lockstep arrangement for fault monitoring incorporates delay |
US6519710B1 (en) | 1998-08-13 | 2003-02-11 | Marconi Communications Limited | System for accessing shared memory by two processors executing same sequence of operation steps wherein one processor operates a set of time later than the other |
US7185184B1 (en) * | 1999-10-06 | 2007-02-27 | Infineon Technologies Ag | Processor system, especially a processor system for communications devices |
US20050060605A1 (en) * | 2003-09-16 | 2005-03-17 | Gibart Anthony Gerard | High speed synchronization in dual-processor safety controller |
US7287184B2 (en) * | 2003-09-16 | 2007-10-23 | Rockwell Automation Technologies, Inc. | High speed synchronization in dual-processor safety controller |
US20110078246A1 (en) * | 2009-09-28 | 2011-03-31 | Bjorn Michael Dittmer-Roche | System and method of simultaneous collaboration |
US8732247B2 (en) * | 2009-09-28 | 2014-05-20 | Bjorn Michael Dittmer-Roche | System and method of simultaneous collaboration |
Also Published As
Publication number | Publication date |
---|---|
AU3130077A (en) | 1979-06-14 |
SU733525A3 (ru) | 1980-05-05 |
MX143306A (es) | 1981-04-13 |
BR7708274A (pt) | 1978-08-08 |
ES465171A1 (es) | 1978-10-01 |
NL7713910A (nl) | 1978-06-20 |
CA1087747A (fr) | 1980-10-14 |
FR2374693B1 (fr) | 1985-02-22 |
HU177434B (en) | 1981-10-28 |
FR2374693A1 (fr) | 1978-07-13 |
SE397013B (sv) | 1977-10-10 |
IT1089170B (it) | 1985-06-18 |
AU515012B2 (en) | 1981-03-12 |
YU298177A (en) | 1982-10-31 |
GB1565320A (en) | 1980-04-16 |
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