US4029527A - Method of producing a doped zone of a given conductivity type in a semiconductor body - Google Patents

Method of producing a doped zone of a given conductivity type in a semiconductor body Download PDF

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Publication number
US4029527A
US4029527A US05/587,966 US58796675A US4029527A US 4029527 A US4029527 A US 4029527A US 58796675 A US58796675 A US 58796675A US 4029527 A US4029527 A US 4029527A
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Prior art keywords
zone
emitter
layer
semiconductor body
doped
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Expired - Lifetime
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US05/587,966
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English (en)
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Andreas Glasl
Helmuth Murrmann
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Siemens AG
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Siemens AG
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/923—Diffusion through a layer

Definitions

  • the invention relates to a method producing a doped zone of one conductivity type in a semiconductor body and somewhat more particularly to a method of producing such a zone which eliminates the "emitter-dip effect" within the semiconductor body.
  • high frequency transistors In the design of high frequency transistors, it is desirable to maintain the maximum oscillation frequency as high as possible. This feature is generally equivalent to a high cut-off frequency at a low base resistance. Further, high frequency transistors generally require as thin a base zone as possible.
  • Such advancement of the base diffusion front may be explained, for example, in situations where an emitter zone has an unusually high dopant (i.e. phosphorus) concentration in the surface region of a silicon semiconductor body, since such high dopant concentration causes lattice distortion, crystal faults, phosphorus precipitation and the like to occur and expand in the region of the base zone lying beneath the emitter zone so as to cause an increased diffusion coefficient. This in turn causes the region of the base zone lying beneath the emitter zone to buckle out and during the necessary subsequent deepening of the emitter zone, to project out in relation to the emitter zone.
  • the diffusion profile of the emitter zone must therefor be made deeper than would be necessary without the so-called "emitter-dip effect.” As a result, an undesirable high inner base resistance occurs in the region below the emitter.
  • the invention provides a method of producing a doped zone of a given conductivity type in a semiconductor body whereby the emitter-dip effect is avoided.
  • an undoped polycrystalline semiconductor layer is deposited onto a select surface or surface area of a semiconductor body and a dopant of a desired conductivity type is diffused through the polycrystalline layer into the semiconductor body below such layer so as to produce a zone of the desired conductivity type within the body.
  • Semiconductor components produced in accordance with the invention do not exhibit the emitter-dip effect.
  • the invention is particularly suitable for the production of low noise npn-silicon transistors having high current amplification. Such transistors have a desirable very low inner base resistance. Short circuits between the emitter and the collector zones almost never occur with these transistors and they have a higher collector-emitter breakdown voltage.
  • FIG. 1 is a partial cross-sectional view of a npn-transistor undergoing production in accordance with the principles of the invention.
  • FIG. 2 is a somewhat similar view of a npn-transistor at another stage of the production process in accordance with the principles of the invention.
  • the invention provides semiconductor components having no "emitter-dip effect,” provides a semiconductor body having a polycrystalline semiconductor layer deposited thereon and provides a process for producing such semiconductor elements.
  • the invention comprises depositing an undoped polycrystalline layer onto a select surface or surface area of a semiconductor body, providing a dopant of a given conductivity type for instance in a gaseous phase or in a doping layer and diffusing such dopant through the polycrystalline semiconductor layer into the select surface of the semiconductor body.
  • a highly n-doped zone 2 is introduced into a surface 12 of a p-conductive semiconductor substrate 1 by conventional photo lacquer-etching techniques.
  • the n-doped zone 2 has a specific resistance of 8 ohm.cm and functions as a buried layer which is doped with arsenic or antimony.
  • a center portion of the surface 12 is at least partially shown by broken lines.
  • the dopants diffuse into layer 3 from zone 2 as schematically indicated by broken line 20.
  • spaced-apart highly p-doped zones 4 and a highly n-doped zone 5 are introduced into the substrate 1 via the surface 13 of the epitaxial layer 3.
  • the spaced-apart zones 4 form an insulating wall around the transistor which is being produced and together with the semiconductor substrate 1 define an insulated island.
  • the zone 5 functions as the connection to the collector zone which overall comprises of the epitaxial layer 3 between the zones 4 and zones 2 and 5, respectively.
  • a base zone 6 is introduced into the epitaxial layer 3 via the surface 13 thereof.
  • Such base zone may be produced by diffusion or by ion implantation and in the exemplary embodiment herein described, is p-conductive.
  • the base zone 6 is then provided with a highly p-doped base terminal zone 7, again by diffusion or ion implantation techniques.
  • a silicon dioxide layer 8 is provided on the surface 13 of the epitaxial layer 3 at the end of these processing steps and windows 16 and 17 are etched into layer 8 by conventional photo lacquer-etching techniques.
  • the window 16 provides access to zone 5 and the window 17 provides access to an area of the base zone 6 for producing an emitter zone thereat.
  • FIG. 1 This stage of the production process of a npn-transistor is illustrated at FIG. 1.
  • an undoped polycrystalline semiconductor material such as undoped polycrystalline silicon
  • an undoped polycrystalline semiconductor material is deposited in a layer thickness of about 0.3 ⁇ m onto the entire free surface of the arrangement shown at FIG. 1 so that a polycrystalline semiconductor layer 9 forms on the overall surface of the structure (the layer 9 is illustrated at FIG. 1 in broken line since portions thereof are removed after deposition).
  • the polycrystalline silicon layer 9 is deposited from a suitable thermally decomposable gaseous silicon compound at a temperature of about 650° C. and with a rate of 0.1 ⁇ m/min.
  • the emitter diffusion for producing emitter zone 15 is then effected at about 900° C. through the polycrystalline layer 9, typically using PH 3 as a dopant.
  • the polycrystalline semiconductor layer 9 is then etched away so that only the areas thereof which overlap the emitter and collector zone remain and only the polycrystalline semiconductor "residues" 9', such as shown at FIG. 2, are present on the resultant structure.
  • a window 10 is etched into the silicon dioxide layer 8 to provide access to the base terminal zone 7 and metal contacts 11 are introduced in a conventional manner into window 10 and onto the polycrystalline semiconductor residues 9'. These residues 9' provide contact to the emitter zone 15 and the zone 5.
  • the metal contacts 11 are typically composed of, for example, titanium and/or aluminum.
  • the phosphorus dopant used in producing the emitter zone 15 is diffused into the base zone 6 through the undoped polycrystalline semiconductor (typically silicon) layer 9. In this manner, the migration of phosphorus atoms is delayed by such polycrystalline semiconductor material and the phosphorus cannot produce any additional crystal defect or the like which would result in an increased diffusion coefficient of the boron dopant in base layer 6.
  • the undoped polycrystalline semiconductor typically silicon
  • the emitter dopant profile below the polycrystalline semiconductor layer 9 in the monocrystalline zone is very steep so that the emitter efficiency is correspondingly high.
  • the base zone 6 which in accordance with the invention is less disturbed, a reduced recombination rate must be expected.
  • the high emitter efficiency and the low recombination rate lead to a higher current amplification of the resultant transistor and the greater base width of such a transistor leads to an increase in the collector-emitter breakdown voltage which is desirable in many applications.
  • the greater base width and the lack of the emitter-dip effect causes a small base resistance in the region of the base zone 6 located below the emitter zone 15, which prevents current crowding effects until currents of larger magnitudes than normal are encountered.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
US05/587,966 1974-06-21 1975-06-18 Method of producing a doped zone of a given conductivity type in a semiconductor body Expired - Lifetime US4029527A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE2429957A DE2429957B2 (de) 1974-06-21 1974-06-21 Verfahren zur Herstellung einer dotierten Zone eines bestimmten Leitungstyps in einem Halbleiterkörper
DT2429957 1974-06-21

Publications (1)

Publication Number Publication Date
US4029527A true US4029527A (en) 1977-06-14

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US05/587,966 Expired - Lifetime US4029527A (en) 1974-06-21 1975-06-18 Method of producing a doped zone of a given conductivity type in a semiconductor body

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US (1) US4029527A (it)
JP (1) JPS5118474A (it)
CA (1) CA1032660A (it)
DE (1) DE2429957B2 (it)
FR (1) FR2275881A1 (it)
GB (1) GB1492830A (it)
IT (1) IT1038812B (it)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4118250A (en) * 1977-12-30 1978-10-03 International Business Machines Corporation Process for producing integrated circuit devices by ion implantation
US4144106A (en) * 1976-07-30 1979-03-13 Sharp Kabushiki Kaisha Manufacture of an I2 device utilizing staged selective diffusion thru a polycrystalline mask
US4199386A (en) * 1978-11-28 1980-04-22 Rca Corporation Method of diffusing aluminum into monocrystalline silicon
US4199378A (en) * 1977-08-25 1980-04-22 U.S. Philips Corporation Method of manufacturing a semiconductor device and semiconductor device manufactured while using such a method
US4283733A (en) * 1975-12-05 1981-08-11 Nippon Electric Co., Ltd. Semiconductor integrated circuit device including element for monitoring characteristics of the device
US4375999A (en) * 1980-02-18 1983-03-08 Vlsi Technology Research Association Method of manufacturing a semiconductor device
US4378260A (en) * 1979-05-18 1983-03-29 Fujitsu Limited Process for producing a semiconductor device
US4534806A (en) * 1979-12-03 1985-08-13 International Business Machines Corporation Method for manufacturing vertical PNP transistor with shallow emitter
US5830939A (en) * 1996-04-25 1998-11-03 Xerox Corporation Viscosity reduction method
US20080171826A1 (en) * 2007-01-16 2008-07-17 Xerox Corporation Adhesion promoter

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7604445A (nl) * 1976-04-27 1977-10-31 Philips Nv Werkwijze ter vervaardiging van een halfgelei- derinrichting, en inrichting vervaardigd door toepassing van de werkwijze.

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3621346A (en) * 1970-01-28 1971-11-16 Ibm Process for forming semiconductor devices with polycrystalline diffusion pathways and devices formed thereby
US3703420A (en) * 1970-03-03 1972-11-21 Ibm Lateral transistor structure and process for forming the same
US3719535A (en) * 1970-12-21 1973-03-06 Motorola Inc Hyperfine geometry devices and method for their fabrication
US3897282A (en) * 1972-10-17 1975-07-29 Northern Electric Co Method of forming silicon gate device structures with two or more gate levels

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1052379A (it) * 1963-03-28 1900-01-01
DE1913681A1 (de) * 1969-03-18 1970-10-01 Siemens Ag Silicium-Hochfrequenz-Planartransistor
US3664896A (en) * 1969-07-28 1972-05-23 David M Duncan Deposited silicon diffusion sources
NL161920C (nl) * 1971-03-12 1980-03-17 Hitachi Ltd Werkwijze voor het vervaardigen van een half- geleiderinrichting, waarbij de roostervervorming t.g.v. doteerstoffen wordt gecompenseerd.
JPS499186A (it) * 1972-05-11 1974-01-26

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3621346A (en) * 1970-01-28 1971-11-16 Ibm Process for forming semiconductor devices with polycrystalline diffusion pathways and devices formed thereby
US3703420A (en) * 1970-03-03 1972-11-21 Ibm Lateral transistor structure and process for forming the same
US3719535A (en) * 1970-12-21 1973-03-06 Motorola Inc Hyperfine geometry devices and method for their fabrication
US3897282A (en) * 1972-10-17 1975-07-29 Northern Electric Co Method of forming silicon gate device structures with two or more gate levels

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4283733A (en) * 1975-12-05 1981-08-11 Nippon Electric Co., Ltd. Semiconductor integrated circuit device including element for monitoring characteristics of the device
US4144106A (en) * 1976-07-30 1979-03-13 Sharp Kabushiki Kaisha Manufacture of an I2 device utilizing staged selective diffusion thru a polycrystalline mask
US4199378A (en) * 1977-08-25 1980-04-22 U.S. Philips Corporation Method of manufacturing a semiconductor device and semiconductor device manufactured while using such a method
US4118250A (en) * 1977-12-30 1978-10-03 International Business Machines Corporation Process for producing integrated circuit devices by ion implantation
US4199386A (en) * 1978-11-28 1980-04-22 Rca Corporation Method of diffusing aluminum into monocrystalline silicon
US4378260A (en) * 1979-05-18 1983-03-29 Fujitsu Limited Process for producing a semiconductor device
US4534806A (en) * 1979-12-03 1985-08-13 International Business Machines Corporation Method for manufacturing vertical PNP transistor with shallow emitter
US4375999A (en) * 1980-02-18 1983-03-08 Vlsi Technology Research Association Method of manufacturing a semiconductor device
US5830939A (en) * 1996-04-25 1998-11-03 Xerox Corporation Viscosity reduction method
US20080171826A1 (en) * 2007-01-16 2008-07-17 Xerox Corporation Adhesion promoter

Also Published As

Publication number Publication date
FR2275881B1 (it) 1980-01-04
IT1038812B (it) 1979-11-30
JPS5118474A (it) 1976-02-14
DE2429957B2 (de) 1980-08-28
GB1492830A (en) 1977-11-23
CA1032660A (en) 1978-06-06
DE2429957A1 (de) 1976-01-08
FR2275881A1 (fr) 1976-01-16
DE2429957C3 (it) 1987-04-16

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