US3925775A - Multiple digit display employing single digit readout - Google Patents

Multiple digit display employing single digit readout Download PDF

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Publication number
US3925775A
US3925775A US410166A US41016673A US3925775A US 3925775 A US3925775 A US 3925775A US 410166 A US410166 A US 410166A US 41016673 A US41016673 A US 41016673A US 3925775 A US3925775 A US 3925775A
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United States
Prior art keywords
digit
digits
duration
display
readout device
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Expired - Lifetime
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US410166A
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English (en)
Inventor
Leslie W Gay
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NCR Voyix Corp
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NCR Corp
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Publication date
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Priority to US410166A priority Critical patent/US3925775A/en
Priority to JP49079709A priority patent/JPS5084195A/ja
Priority to GB4043474A priority patent/GB1446686A/en
Priority to DE19742450046 priority patent/DE2450046A1/de
Priority to CH1415574D priority patent/CH1415574A4/xx
Priority to CH846475A priority patent/CH586440A5/xx
Priority to CH1415574A priority patent/CH592336B5/xx
Priority to FR7435657A priority patent/FR2249399B1/fr
Application granted granted Critical
Publication of US3925775A publication Critical patent/US3925775A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G9/00—Visual time or date indication means
    • G04G9/08—Visual time or date indication means by building-up characters using a combination of indicating elements, e.g. by using multiplexing techniques
    • G04G9/082—Visual time or date indication means by building-up characters using a combination of indicating elements, e.g. by using multiplexing techniques using multiplexing techniques

Definitions

  • the blanking periods between successive digits within a group having a common range of significance may have a first duration approximating the duration for which each digit is displayed whereas the blanking periods between the last digit within a group and the first digit within a succeeding group may have a second, longer duration, typically twice the digit display duration.
  • FIG. IA is a diagrammatic representation of FIG. IA
  • This invention relates to information display and, more particularly, to a multiple digit display employing a single digit alphanumeric readout.
  • Displays for effecting communication of multiple digit alphanumeric information take many forms well known in the art.
  • the prior art displays have one common characteristic; viz.: a plurality of digits, generally the complete information set, is displayed simultaneously utilizing a corresponding plurality of display digits.
  • a cash register display given a simultaneous readout of all digits in dollars and cents or other exchange medium
  • a digital clock display simultaneously presents hours and minutes and sometimes also seconds
  • a computer console display typically includes a great deal of simultaneously presented information.
  • FIGS. la and lb, taken together, are a generalized flow diagram setting forth the method of the present invention. and i FIGS. 2a and 2b, taken together, constitute a logic diagram of an exemplary environment in which the invention may be practiced.
  • the fundamental basis of the method of the present invention lies in the realization that serially presented multiple digit information can be readily assimilated if the total number of digits is not excessive, if the type of information being conveyed is known, and if the presentation is keyed by periods during which the display is blanked for predetermined durations, More particularly, it has been found that such multiple digit information can be assimilated with accuracy similar to that achieved with parallel, simultaneous displays when the serial display rate flashes each digit for one-fourth second or less.
  • six digit time may be displayed on a one digit readout according to the present invention by serially ordering the digits from most significant (tens of hours) to least significant (units of minutes) and further providing distinguishing pauses between the hours digits, between the minutes digits, and between the seconds digits.
  • a complete display cycle is divided into 16 equal time periods of approximately one-fourth second each.
  • the tens of hours digit is flashed on the display element for one time period.
  • the display is then blanked for one time period after which the units of hours digit is presented for one time period.
  • the display is blanked for two time periods to indicate the separation between hours and minutes information.
  • the two minutes digits are each flashed on for one time period separated by a single time period during which the display is blanked, and the seconds digits are similarly presented. After the units of seconds digit has been displayed for one time period, the readout is blanked for three time periods to signify the beginning of another complete display cycle.
  • FIG. 2 (2a and 2b taken together), a logic diagram of a six-digit clock utilizing a single read-out element, will not be discussed.
  • a time base signal is developed by a hz generator 1.
  • the time base generator 1 may be dependent upon power line frequency, a frequency subdivided crystal oscillator, a low frequency relaxation oscillator, or such other standard as may be appropriate. It will be understood, of course, that 60 hz is simply convenient for the specific apparatus of FIG. 2, and other time base frequencies find use in appropriate applications.
  • Four binary frequency divider stages 2, 3, 4, and 5 reduce the 60 hz time base signal to 3O, 15, 7 /2 and 3% hz.
  • the 7 /2 hz signal is applied to the first of four additional cascaded binary frequency dividers 6, 7, 8, and 9, each of which has a 1 output when the corresponding stage is in a first state.
  • the output from the binary divider stage 6 is applied to input terminals of logic inverters 16 and 24.
  • the output from binary stage 7 is applied to the input terminals of inverters l4 and 22, and the output of binary stage 8 is coupled to the input terminals of inverters 12 and 20.
  • the output from the divider stage 9,'in addition to being directly connected to the input of inverter'18, is also connected to the input of an I inverter 43 which, in turn, drives inverter 10.
  • Inverters 10-24 respectively drive a second array of inverters 11-25 to provide logically reinverted signals for combi- 1 nation with'the inverted signals to develop 16 sequential time periods.
  • Inverters 11 and 19 are not used and are shown only because they are present in the specific integrated circuits (which will be referenced below) from which the exemplary embodiment of the apparatus has been fabricated.
  • each gate of an array of 16 NAND gates 26-42 inclusive is provided with four inputs. These inputs receive the outputs of the inverters 10-25 in 16 unique combinations as shown in FIG. '2;
  • the NAND gates 26-42 w ill therefor sequentially issue respective output signals T-T16.
  • the logic equation which will cause the NAND gate 26 to issue the signal T0 is A0- -A1-A2'A3.
  • the logic combin a tion which will ca use the NAND gate 36 to issue the T signal is A0- It will be observed that the signal A0 changes logic level at a frequency of 3.75 hz. Since A1, A2, and A3 are slower by powers of 2, A0 governs the rate at which the logic pattern issued by the dividers 6, 7, 8, and 9 changes. The duration of each time period for the logic than necessary.
  • a 60 hz signal from the time base generator 1 is also applied to the reference frequency input of clock chip 44.
  • the logic within the clock chip 44 is quite complex. However, only the functions carried out by the clock chip are of direct pertinence to the present invention,
  • the clock chip 44 accepts the 60 hz time base signal and issues a multiplexed BCD output to logic inverters .45, 46, 47, and 48 to provide, respectively, the signals 1 2 2 2 and 2.
  • the digit value signals are applied to appropriate inputs of a single digit readout device 49.
  • the readout device'49 also includes logic circuitry V which is of no direct import to an understanding of the present invention. It should be noted, however, that the exemplary embodiment utilizes a readout device which includes a 4-bit latch such that a strobe pulse is necessary to introduce new information to the display. A commercially available readout device incorporating this end and other functions to be described will be referenced below.
  • the clock chip 44 also issues, at any given time, one of six signals to indicate which digit of the clock presentation is currently available at the BCD outputs. These signals, after passing through inverters 50-55, are assigned the mnemonicdesignations HT, HU, MT, MU, ST, and SU representing tens of hours through units of seconds.
  • the strobe pulse necessary to introduce a new digit into the readout device 49 is developed by combining certain of the clock pulses with the digit multiplex information from the clock chip 44.
  • TO and HT are applied as the two input signals to NAND gate '56; T2 and HU signals are applied as the two inputs to NAND gate 57; and T5 and MT are applied as the two inputs to NAND gate 58.
  • NAND gates 59-61 are selectively enabled. All outputs from the NAND gates 56-61 are connected together and applied to the strobe input to the readout device 49.
  • the clock chip 44 utilized in the exemplary embodiment of the apparatus incorporates an internal multiplexing oscillator which can however be externally frequency controlled.
  • the multiplexing frequency is not critical so long as it is well above the step frequency from time period to time period.
  • a multiplex frequency of approximately 1 Khz has been found to be satisfactory in the exemplary embodiment.
  • digit information from clock chip 44 will be strobed into the internal 4-bit latch of the readout device 49 only when the signal HT is present to fully enable NAND gate 56.
  • the signal .ST can cause a strobe pulse to be generated by fully enabling the NAND gate 60.
  • the readout device 49 can accept only tens of seconds information from the clock chip 44 during T10.
  • a full 6-digit display cycle takes place as follows.
  • T0 the tens of hours digit is displayed.
  • T1 the readout device 49 is blanked to separate the tens of hours digit from the units of hours digit.
  • T2 the units of hours digit is displayed.
  • T3 and T4 the readout device is blanked to separate the units of hours and the tens of minutes digits and also, as a result of the extended blanking duration, provide an indication of the separation between the hours digit pair and the minutes digit pair.
  • the tens the tens,
  • the relationship of the time durations of the various blanking phases to the time durations during which digits are displayed has been found to be readily implemented with binary logic. That is, equal blanking duration is provided between successive digits having the same order of significance (such as the hour digits, dollar digits, etc.) while the extended duration between successive digits which constitute the last digit of a group of digits in one range of significance and the first digit in the next digit group (hours to minutes, dollars to cents, etc.) may usefully be twice as long.
  • the duration of blanking between the end of a complete display and the institution of a succeeding display may be accommodated to a particular application.
  • One time period increment in excess of the maximum blanking period used during a display has been found to give entirely sufficient psychological warning of the beginning of a display event.
  • the 60 hz generator 1 may take any one of many forms well known to all skilled in the art. For high accuracy, a superior crystal oscillator and appropriate countdown logic may be utilized. Alternatively, a useful signal may be developed from a 60 hz power line of suitable frequency integrity. For simplicity, a 60 hz relaxation oscillator may be used.
  • the binary divider stages 2-9 are two 4-bit integrated circuit binary counters, designated 9316, manufactured by Fairchild Semiconductor.
  • Inverters 10-25 and NAND gates 26-42 comprise two integrated circuit one-of-lO decoders utilized as one-of-8 decoders and manufactured under the disignation 9301 by Fairchild.
  • the inverters 43, 45-55, and 63-58 available on three integrated circuits designated 9016 by Fairchild.
  • the NAND gates 56-61 are contained on two Fairchild 9002 integrated circuits.
  • the NOR gate 62 is contained on two Fairchild type 9007 integrated circuits.
  • the single digit readout device 49 is a Texas Instruments type T1L3ll light emitting diode unit.
  • the clock chip 44 is a type MM5313, manufactured by The National Semiconductor Corporation. One may refer to Fairchild TTL Data Book (June, 1972), National Semiconductor Specification Sheet for MM431l/MM531 l, MM4312/MM5312, MM43l3/MM5313, MM43l4/MM5314 Digital Clock Chip (June, 1972), and Texas Instruments Bulletin DL-S 7211653 for Type TIL31 l Hexadecimal Display with Logic (March, 1972) for detail of the internal logic and circuitry of the elements employed in the exemplary apparatus. Those skilled in the art will understand that the selection of logic type and readout device type is strictly a matter of design choice and that many different choices are available to the practitioner.
  • switches 69, 70, and 71 are provided to provide fast slew, slow slew, and hold functions, respectively, by momentarily applying a V signal to appropriate inputs of the clock chip 44.
  • switch 69 When switch 69 is closed, the internal logic of the clock chip 44 responds by advancing the internal time by 1 hour per second. Similarly, actuating switch 70 advances the internal time by one minute per second. Actuation of the switch 71 inhibits incrementing the internal time to effect a hold feature.
  • a method for displaying multiple digit information comprising the steps of:

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Digital Computer Display Output (AREA)
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US410166A 1973-10-26 1973-10-26 Multiple digit display employing single digit readout Expired - Lifetime US3925775A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US410166A US3925775A (en) 1973-10-26 1973-10-26 Multiple digit display employing single digit readout
JP49079709A JPS5084195A (sl) 1973-10-26 1974-07-11
GB4043474A GB1446686A (en) 1973-10-26 1974-09-17 Information display apparatus
DE19742450046 DE2450046A1 (de) 1973-10-26 1974-10-22 Anzeigevorrichtung zur anzeige von vielzeichen-informationen
CH1415574D CH1415574A4 (sl) 1973-10-26 1974-10-23
CH846475A CH586440A5 (sl) 1973-10-26 1974-10-23
CH1415574A CH592336B5 (sl) 1973-10-26 1974-10-23
FR7435657A FR2249399B1 (sl) 1973-10-26 1974-10-24

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Application Number Priority Date Filing Date Title
US410166A US3925775A (en) 1973-10-26 1973-10-26 Multiple digit display employing single digit readout

Publications (1)

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US3925775A true US3925775A (en) 1975-12-09

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US410166A Expired - Lifetime US3925775A (en) 1973-10-26 1973-10-26 Multiple digit display employing single digit readout

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US (1) US3925775A (sl)
JP (1) JPS5084195A (sl)
CH (3) CH586440A5 (sl)
DE (1) DE2450046A1 (sl)
FR (1) FR2249399B1 (sl)
GB (1) GB1446686A (sl)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4090247A (en) * 1975-08-11 1978-05-16 Arthur D. Little, Inc. Portable data entry device
US4097924A (en) * 1975-09-11 1978-06-27 Ing. C. Olivetti & C., S.P.A. Computer operator guide device
US4141208A (en) * 1976-01-19 1979-02-27 Hughes Aircraft Company Digitally tuned timepiece
US4394653A (en) * 1980-11-24 1983-07-19 General Instrument Corporation Bi-directional drive multiplexed display system
US4401262A (en) * 1982-06-18 1983-08-30 Honeywell Inc. Energy saving thermostat with means to shift offset time program
US4668994A (en) * 1983-05-20 1987-05-26 Canon Kabushiki Kaisha Facsimile apparatus
US4970502A (en) * 1979-08-27 1990-11-13 Sharp Kabushiki Kaisha Running character display
US5596554A (en) * 1993-06-04 1997-01-21 Hagadorn; Hubert W. Set operation in a timepiece having an electrooptical display

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS547377A (en) * 1977-06-17 1979-01-20 Seiko Instr & Electronics Ltd Digital electronic watch

Citations (14)

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US2754360A (en) * 1951-12-24 1956-07-10 Ibm Character synthesizer
US2862144A (en) * 1958-03-21 1958-11-25 Gen Dynamics Corp Simplified system for character selection in a shaped beam tube
US2907995A (en) * 1957-01-17 1959-10-06 American Sign & Indicator Co Display signs
US2909972A (en) * 1958-09-15 1959-10-27 Ibm Display apparatus employing electro-optical devices
US3047851A (en) * 1958-03-21 1962-07-31 Marquardt Corp Electronic character generating and displaying apparatus
US3122734A (en) * 1960-06-24 1964-02-25 Ibm Code conversion and display system
US3276200A (en) * 1964-08-27 1966-10-04 Gen Time Corp Electronic clock
US3320585A (en) * 1964-12-23 1967-05-16 James L R Hines Time informing display device
US3401385A (en) * 1964-11-03 1968-09-10 Polarad Electronics Corp Serial pulse continuous message indicator system
US3416133A (en) * 1963-01-07 1968-12-10 Ultronic Systems Corp Shift register controlled market ticker information display
US3555505A (en) * 1969-03-17 1971-01-12 Ladislaw G Srogi Air space traffic simulator
US3585296A (en) * 1969-10-28 1971-06-15 Ibm Synchronized reciprocating lens photocomposer
US3760581A (en) * 1971-10-18 1973-09-25 Y Wakabayashi Electro-mechanical digital world clock
US3846784A (en) * 1972-05-22 1974-11-05 C Sinclair Electronic digital displays

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5017933A (sl) * 1973-06-19 1975-02-25

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2754360A (en) * 1951-12-24 1956-07-10 Ibm Character synthesizer
US2907995A (en) * 1957-01-17 1959-10-06 American Sign & Indicator Co Display signs
US2862144A (en) * 1958-03-21 1958-11-25 Gen Dynamics Corp Simplified system for character selection in a shaped beam tube
US3047851A (en) * 1958-03-21 1962-07-31 Marquardt Corp Electronic character generating and displaying apparatus
US2909972A (en) * 1958-09-15 1959-10-27 Ibm Display apparatus employing electro-optical devices
US3122734A (en) * 1960-06-24 1964-02-25 Ibm Code conversion and display system
US3416133A (en) * 1963-01-07 1968-12-10 Ultronic Systems Corp Shift register controlled market ticker information display
US3276200A (en) * 1964-08-27 1966-10-04 Gen Time Corp Electronic clock
US3401385A (en) * 1964-11-03 1968-09-10 Polarad Electronics Corp Serial pulse continuous message indicator system
US3320585A (en) * 1964-12-23 1967-05-16 James L R Hines Time informing display device
US3555505A (en) * 1969-03-17 1971-01-12 Ladislaw G Srogi Air space traffic simulator
US3585296A (en) * 1969-10-28 1971-06-15 Ibm Synchronized reciprocating lens photocomposer
US3760581A (en) * 1971-10-18 1973-09-25 Y Wakabayashi Electro-mechanical digital world clock
US3846784A (en) * 1972-05-22 1974-11-05 C Sinclair Electronic digital displays

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4090247A (en) * 1975-08-11 1978-05-16 Arthur D. Little, Inc. Portable data entry device
US4097924A (en) * 1975-09-11 1978-06-27 Ing. C. Olivetti & C., S.P.A. Computer operator guide device
US4141208A (en) * 1976-01-19 1979-02-27 Hughes Aircraft Company Digitally tuned timepiece
US4970502A (en) * 1979-08-27 1990-11-13 Sharp Kabushiki Kaisha Running character display
US4394653A (en) * 1980-11-24 1983-07-19 General Instrument Corporation Bi-directional drive multiplexed display system
US4401262A (en) * 1982-06-18 1983-08-30 Honeywell Inc. Energy saving thermostat with means to shift offset time program
US4668994A (en) * 1983-05-20 1987-05-26 Canon Kabushiki Kaisha Facsimile apparatus
US5596554A (en) * 1993-06-04 1997-01-21 Hagadorn; Hubert W. Set operation in a timepiece having an electrooptical display

Also Published As

Publication number Publication date
JPS5084195A (sl) 1975-07-07
GB1446686A (en) 1976-08-18
DE2450046A1 (de) 1975-04-30
CH592336B5 (sl) 1977-10-31
FR2249399B1 (sl) 1977-03-25
CH1415574A4 (sl) 1977-02-28
FR2249399A1 (sl) 1975-05-23
CH586440A5 (sl) 1977-03-31

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