US3925766A - Dynamically variable priority access system - Google Patents

Dynamically variable priority access system Download PDF

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Publication number
US3925766A
US3925766A US419312A US41931273A US3925766A US 3925766 A US3925766 A US 3925766A US 419312 A US419312 A US 419312A US 41931273 A US41931273 A US 41931273A US 3925766 A US3925766 A US 3925766A
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Prior art keywords
priority
central processor
request
signal
peripheral
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Expired - Lifetime
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US419312A
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English (en)
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Angelo Bardotti
Renzo Pederzini
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Bull HN Information Systems Italia SpA
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Honeywell Information Systems Italia SpA
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4831—Task transfer initiation or dispatching by interrupt, e.g. masked with variable priority
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Definitions

  • the data processing system of FIG. 1 comprises: a central processor 1, a main working memory 2, an information exchange control unit 3 which forms part of central processor 1, and a plurality of peripheral units 4 to 13.
  • FIG. 2 shows physical structure of an exemplary interconnection channel.
  • central processor 1 forwards to peripheral control unit 14, through channel on wire set DO thereof, the appropriate character.
  • This character is accompanied by a signal on wire C0 of channel 15, characterizing said character as an address for peripheral unit 4, and by a strobe pulse on wire STO of channel 15.
  • Peripheral control unit 14 stores this information in a suitable input register and selects peripheral unit 4.
  • the leads 54, 55, 56, 58, 59, 60, 66, 67, 69 and 70 form a set of transmission leads for interrupt requests, whose priority may be established in a fixed manner.
  • a priority selecting matrix 72 shown in FIG. 5, and further described hereinafter, arranges the input leads thereof according to a criterion of relative priority and permits only the signals accorded the highest priority relative to the others to be transmitted.
  • one additional lead INT 13 may be provided, but some wires of the set DI may be assigned to forwarding interrupt signals.
  • the signals appearing on such assigned wires of set DI are interpreted as interrupt signals.
  • the signal on lead INT 1B may be used also as strobe signal for such wires, thus avoiding the risk of a wrong interpretation of the interrupt requests due to the distribution of the signals.
  • lead INT 1C is one of the wires of wire set D]. Therefore lead INT 18 carries only a characterizing and strobing signal. Thus, only two different types of interrupt requests may be represented on the two leads INT 1B and INT 1C.
  • interrupt requests forwarded on leads INT 1B and INT 1C are decoded at the output leads of flipflops 92 and 93 by a decoder 94.
  • lead B is connected to the input lead of an inverter 112.
  • the output lead of inverter 112, the output lead of inverter 110, and input lead C are connected to the respective input leads of a three-input AND gate 113, whose output lead is the third output lead UC of the priority selecting matrix.
  • An interrupt signal on lead C will be transferred to output lead UC only if at that time no signal is present on leads A and lnverters H4 and 115 and AND gates 116 and 117 are employed similarly to deliver output signals on respective output leads UD and UE only if no interrupt signal of a higher priority level is present.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
US419312A 1972-11-29 1973-11-27 Dynamically variable priority access system Expired - Lifetime US3925766A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT32201/72A IT971304B (it) 1972-11-29 1972-11-29 Sistema di accesso a priorita variabile dinamicamente

Publications (1)

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US3925766A true US3925766A (en) 1975-12-09

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US419312A Expired - Lifetime US3925766A (en) 1972-11-29 1973-11-27 Dynamically variable priority access system

Country Status (8)

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US (1) US3925766A (enrdf_load_stackoverflow)
JP (1) JPS5646615B2 (enrdf_load_stackoverflow)
AU (1) AU475654B2 (enrdf_load_stackoverflow)
CA (1) CA994919A (enrdf_load_stackoverflow)
DE (1) DE2358545A1 (enrdf_load_stackoverflow)
FR (1) FR2208147B1 (enrdf_load_stackoverflow)
GB (1) GB1423674A (enrdf_load_stackoverflow)
IT (1) IT971304B (enrdf_load_stackoverflow)

Cited By (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4001784A (en) * 1973-12-27 1977-01-04 Honeywell Information Systems Italia Data processing system having a plurality of input/output channels and physical resources dedicated to distinct and interruptible service levels
US4006466A (en) * 1975-03-26 1977-02-01 Honeywell Information Systems, Inc. Programmable interface apparatus and method
US4010448A (en) * 1974-10-30 1977-03-01 Motorola, Inc. Interrupt circuitry for microprocessor chip
US4024503A (en) * 1969-11-25 1977-05-17 Ing. C. Olivetti & C., S.P.A. Priority interrupt handling system
US4069510A (en) * 1974-10-30 1978-01-17 Motorola, Inc. Interrupt status register for interface adaptor chip
US4096570A (en) * 1974-12-29 1978-06-20 Fujitsu Limited Subchannel memory access control system
US4130864A (en) * 1976-10-29 1978-12-19 Westinghouse Electric Corp. Priority selection circuit for multiported central functional unit with automatic priority reduction on excessive port request
US4224665A (en) * 1974-09-10 1980-09-23 U.S. Philips Corporation Bus-organized computer system with independent execution control
US4271467A (en) * 1979-01-02 1981-06-02 Honeywell Information Systems Inc. I/O Priority resolver
US4302808A (en) * 1978-11-06 1981-11-24 Honeywell Information Systems Italia Multilevel interrupt handling apparatus
US4481583A (en) * 1981-10-30 1984-11-06 At&T Bell Laboratories Method for distributing resources in a time-shared system
US4484275A (en) * 1976-09-07 1984-11-20 Tandem Computers Incorporated Multiprocessor system
US4609995A (en) * 1982-06-25 1986-09-02 Tokyo Shibaura Denki Kabushiki Kaisha Priority controller
US4722046A (en) * 1986-08-27 1988-01-26 Amdahl Corporation Cache storage priority
US4755938A (en) * 1982-06-18 1988-07-05 Fujitsu Limited Access request control apparatus which reassigns higher priority to incomplete access requests
EP0283580A1 (en) * 1987-03-27 1988-09-28 International Business Machines Corporation Computer system with direct memory access channel arbitration
FR2613095A1 (fr) * 1987-03-27 1988-09-30 Ibm Ordinateur comportant une unite de commande d'acces direct en memoire programmable
US4788640A (en) * 1986-01-17 1988-11-29 Intel Corporation Priority logic system
US4789924A (en) * 1984-07-07 1988-12-06 Iwatsu Electric Co. Ltd. Microprocessor emulation apparatus for debugging a microprocessor of an electronic system without utilizing an interrupt signal and a stop signal to temporarily stop an operation of the system
US4794516A (en) * 1985-10-31 1988-12-27 International Business Machines Corporation Method and apparatus for communicating data between a host and a plurality of parallel processors
US4829467A (en) * 1984-12-21 1989-05-09 Canon Kabushiki Kaisha Memory controller including a priority order determination circuit
US4914580A (en) * 1987-10-26 1990-04-03 American Telephone And Telegraph Company Communication system having interrupts with dynamically adjusted priority levels
US4918599A (en) * 1985-09-30 1990-04-17 Fujitsu Limited Interrupt control system
US4941086A (en) * 1984-02-02 1990-07-10 International Business Machines Corporation Program controlled bus arbitration for a distributed array processing system
US4972342A (en) * 1988-10-07 1990-11-20 International Business Machines Corporation Programmable priority branch circuit
US4980820A (en) * 1985-02-28 1990-12-25 International Business Machines Corporation Interrupt driven prioritized queue
US5043937A (en) * 1987-12-23 1991-08-27 International Business Machines Corporation Efficient interface for the main store of a data processing system
US5046041A (en) * 1987-12-17 1991-09-03 Automobiles Peugeot Device for transmitting information between a plurality of elements of an automobile vehicle, and a central information processing unit
WO1991020041A1 (en) * 1990-06-11 1991-12-26 Supercomputer Systems Limited Partnership Multiple request toggling priority arbitration system
US5077662A (en) * 1986-04-11 1991-12-31 Ampex Corporation Microprocessor control system having expanded interrupt capabilities
US5083261A (en) * 1983-11-03 1992-01-21 Motorola, Inc. Dynamically alterable interrupt priority circuit
US5099414A (en) * 1988-06-24 1992-03-24 International Computers Limited Interrupt handling in a multi-processor data processing system
US5115507A (en) * 1987-12-23 1992-05-19 U.S. Philips Corp. System for management of the priorities of access to a memory and its application
US5239629A (en) * 1989-12-29 1993-08-24 Supercomputer Systems Limited Partnership Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system
US5241661A (en) * 1987-03-27 1993-08-31 International Business Machines Corporation DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter
US5241628A (en) * 1990-01-04 1993-08-31 Intel Corporation Method wherein source arbitrates for bus using arbitration number of destination
US5257383A (en) * 1991-08-12 1993-10-26 Stratus Computer, Inc. Programmable interrupt priority encoder method and apparatus
US5257357A (en) * 1991-01-22 1993-10-26 Motorola, Inc. Method and apparatus for implementing a priority adjustment of an interrupt in a data processor
US5265215A (en) * 1991-04-22 1993-11-23 International Business Machines Corporation Multiprocessor system and interrupt arbiter thereof
US5301283A (en) * 1992-04-16 1994-04-05 Digital Equipment Corporation Dynamic arbitration for system bus control in multiprocessor data processing system
AU649642B2 (en) * 1990-02-14 1994-06-02 International Business Machines Corporation Communications interface adapter
US5506966A (en) * 1991-12-17 1996-04-09 Nec Corporation System for message traffic control utilizing prioritized message chaining for queueing control ensuring transmission/reception of high priority messages
US5634060A (en) * 1994-08-09 1997-05-27 Unisys Corporation Method and apparatus for high-speed efficient bi-directional communication between multiple processor over a common bus
US5642488A (en) * 1994-05-23 1997-06-24 American Airlines, Inc. Method and apparatus for a host computer to stage a plurality of terminal addresses
US5822766A (en) * 1997-01-09 1998-10-13 Unisys Corporation Main memory interface for high speed data transfer
US5970253A (en) * 1997-01-09 1999-10-19 Unisys Corporation Priority logic for selecting and stacking data
US20020009098A1 (en) * 2000-07-14 2002-01-24 International Business Machines Corporation Communication control method and device
US20020152419A1 (en) * 2001-04-11 2002-10-17 Mcloughlin Michael Apparatus and method for accessing a mass storage device in a fault-tolerant server
US6604160B1 (en) * 2000-09-28 2003-08-05 International Business Machines Corporation Computing system arbitrating and selectively providing resource-seeking tasks with takeaway of non-shareable resources
US6618780B1 (en) * 1999-12-23 2003-09-09 Cirrus Logic, Inc. Method and apparatus for controlling interrupt priority resolution
US20050055517A1 (en) * 2001-09-14 2005-03-10 Seagate Technology Llc, A Delaware Corporation Prioritizing commands in a data storage device
US7461009B1 (en) 2001-06-29 2008-12-02 Ncr Corporation System and method of sending messages to electronic shelf labels based upon priority
US20090274017A1 (en) * 1998-11-09 2009-11-05 Siamack Nemazie Mixed-signal single-chip integrated system electronics for data storage devices
US10229077B2 (en) 2014-03-25 2019-03-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for data transfer between real-time tasks using a DMA memory controller

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5093055A (enrdf_load_stackoverflow) * 1973-12-17 1975-07-24
GB1468642A (en) * 1975-01-07 1977-03-30 Burroughs Corp Data processing systems
US3984820A (en) * 1975-06-30 1976-10-05 Honeywell Information Systems, Inc. Apparatus for changing the interrupt level of a process executing in a data processing system
FR2346775A1 (fr) * 1975-11-03 1977-10-28 Hugon Jean Processeur de traitement de donnees multiples ayant des priorites diffe
US4035780A (en) * 1976-05-21 1977-07-12 Honeywell Information Systems, Inc. Priority interrupt logic circuits
US4736318A (en) * 1985-03-01 1988-04-05 Wang Laboratories, Inc. Data processing system having tunable operating system means

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3445822A (en) * 1967-07-14 1969-05-20 Ibm Communication arrangement in data processing system
US3473155A (en) * 1964-05-04 1969-10-14 Gen Electric Apparatus providing access to storage device on priority-allocated basis
US3534339A (en) * 1967-08-24 1970-10-13 Burroughs Corp Service request priority resolver and encoder
US3611305A (en) * 1969-02-10 1971-10-05 Scanders Associates Inc Data processor interrupt system
US3611307A (en) * 1969-04-03 1971-10-05 Ibm Execution unit shared by plurality of arrays of virtual processors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3473155A (en) * 1964-05-04 1969-10-14 Gen Electric Apparatus providing access to storage device on priority-allocated basis
US3445822A (en) * 1967-07-14 1969-05-20 Ibm Communication arrangement in data processing system
US3534339A (en) * 1967-08-24 1970-10-13 Burroughs Corp Service request priority resolver and encoder
US3611305A (en) * 1969-02-10 1971-10-05 Scanders Associates Inc Data processor interrupt system
US3611307A (en) * 1969-04-03 1971-10-05 Ibm Execution unit shared by plurality of arrays of virtual processors

Cited By (63)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024503A (en) * 1969-11-25 1977-05-17 Ing. C. Olivetti & C., S.P.A. Priority interrupt handling system
US4001784A (en) * 1973-12-27 1977-01-04 Honeywell Information Systems Italia Data processing system having a plurality of input/output channels and physical resources dedicated to distinct and interruptible service levels
US4224665A (en) * 1974-09-10 1980-09-23 U.S. Philips Corporation Bus-organized computer system with independent execution control
US4010448A (en) * 1974-10-30 1977-03-01 Motorola, Inc. Interrupt circuitry for microprocessor chip
US4069510A (en) * 1974-10-30 1978-01-17 Motorola, Inc. Interrupt status register for interface adaptor chip
US4096570A (en) * 1974-12-29 1978-06-20 Fujitsu Limited Subchannel memory access control system
US4006466A (en) * 1975-03-26 1977-02-01 Honeywell Information Systems, Inc. Programmable interface apparatus and method
US4484275A (en) * 1976-09-07 1984-11-20 Tandem Computers Incorporated Multiprocessor system
US4130864A (en) * 1976-10-29 1978-12-19 Westinghouse Electric Corp. Priority selection circuit for multiported central functional unit with automatic priority reduction on excessive port request
US4302808A (en) * 1978-11-06 1981-11-24 Honeywell Information Systems Italia Multilevel interrupt handling apparatus
US4271467A (en) * 1979-01-02 1981-06-02 Honeywell Information Systems Inc. I/O Priority resolver
US4481583A (en) * 1981-10-30 1984-11-06 At&T Bell Laboratories Method for distributing resources in a time-shared system
US4755938A (en) * 1982-06-18 1988-07-05 Fujitsu Limited Access request control apparatus which reassigns higher priority to incomplete access requests
US4609995A (en) * 1982-06-25 1986-09-02 Tokyo Shibaura Denki Kabushiki Kaisha Priority controller
US5083261A (en) * 1983-11-03 1992-01-21 Motorola, Inc. Dynamically alterable interrupt priority circuit
US4941086A (en) * 1984-02-02 1990-07-10 International Business Machines Corporation Program controlled bus arbitration for a distributed array processing system
US4789924A (en) * 1984-07-07 1988-12-06 Iwatsu Electric Co. Ltd. Microprocessor emulation apparatus for debugging a microprocessor of an electronic system without utilizing an interrupt signal and a stop signal to temporarily stop an operation of the system
US4829467A (en) * 1984-12-21 1989-05-09 Canon Kabushiki Kaisha Memory controller including a priority order determination circuit
US4980820A (en) * 1985-02-28 1990-12-25 International Business Machines Corporation Interrupt driven prioritized queue
US4918599A (en) * 1985-09-30 1990-04-17 Fujitsu Limited Interrupt control system
US4794516A (en) * 1985-10-31 1988-12-27 International Business Machines Corporation Method and apparatus for communicating data between a host and a plurality of parallel processors
US4788640A (en) * 1986-01-17 1988-11-29 Intel Corporation Priority logic system
US5077662A (en) * 1986-04-11 1991-12-31 Ampex Corporation Microprocessor control system having expanded interrupt capabilities
US4722046A (en) * 1986-08-27 1988-01-26 Amdahl Corporation Cache storage priority
FR2613096A1 (fr) * 1987-03-27 1988-09-30 Ibm Dispositif d'arbitrage d'acces a memoire direct
US4901234A (en) * 1987-03-27 1990-02-13 International Business Machines Corporation Computer system having programmable DMA control
BE1001290A4 (fr) * 1987-03-27 1989-09-19 Ibm Dispositif d'arbitrage d'acces a memoire direct.
BE1000819A3 (fr) * 1987-03-27 1989-04-11 Ibm Ordinateur comportant une unite de commande d'acces direct en memoire programmable.
US5241661A (en) * 1987-03-27 1993-08-31 International Business Machines Corporation DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter
EP0288607A1 (en) * 1987-03-27 1988-11-02 International Business Machines Corporation Computer system having a multi-channel direct memory access arbitration
FR2613095A1 (fr) * 1987-03-27 1988-09-30 Ibm Ordinateur comportant une unite de commande d'acces direct en memoire programmable
EP0283580A1 (en) * 1987-03-27 1988-09-28 International Business Machines Corporation Computer system with direct memory access channel arbitration
US4914580A (en) * 1987-10-26 1990-04-03 American Telephone And Telegraph Company Communication system having interrupts with dynamically adjusted priority levels
US5046041A (en) * 1987-12-17 1991-09-03 Automobiles Peugeot Device for transmitting information between a plurality of elements of an automobile vehicle, and a central information processing unit
US5043937A (en) * 1987-12-23 1991-08-27 International Business Machines Corporation Efficient interface for the main store of a data processing system
US5115507A (en) * 1987-12-23 1992-05-19 U.S. Philips Corp. System for management of the priorities of access to a memory and its application
US5099414A (en) * 1988-06-24 1992-03-24 International Computers Limited Interrupt handling in a multi-processor data processing system
US4972342A (en) * 1988-10-07 1990-11-20 International Business Machines Corporation Programmable priority branch circuit
US5168570A (en) * 1989-12-29 1992-12-01 Supercomputer Systems Limited Partnership Method and apparatus for a multiple request toggling priority system
US5239629A (en) * 1989-12-29 1993-08-24 Supercomputer Systems Limited Partnership Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system
US5241628A (en) * 1990-01-04 1993-08-31 Intel Corporation Method wherein source arbitrates for bus using arbitration number of destination
AU649642B2 (en) * 1990-02-14 1994-06-02 International Business Machines Corporation Communications interface adapter
WO1991020041A1 (en) * 1990-06-11 1991-12-26 Supercomputer Systems Limited Partnership Multiple request toggling priority arbitration system
US5257357A (en) * 1991-01-22 1993-10-26 Motorola, Inc. Method and apparatus for implementing a priority adjustment of an interrupt in a data processor
US5265215A (en) * 1991-04-22 1993-11-23 International Business Machines Corporation Multiprocessor system and interrupt arbiter thereof
US5257383A (en) * 1991-08-12 1993-10-26 Stratus Computer, Inc. Programmable interrupt priority encoder method and apparatus
US5506966A (en) * 1991-12-17 1996-04-09 Nec Corporation System for message traffic control utilizing prioritized message chaining for queueing control ensuring transmission/reception of high priority messages
US5301283A (en) * 1992-04-16 1994-04-05 Digital Equipment Corporation Dynamic arbitration for system bus control in multiprocessor data processing system
US5642488A (en) * 1994-05-23 1997-06-24 American Airlines, Inc. Method and apparatus for a host computer to stage a plurality of terminal addresses
US5634060A (en) * 1994-08-09 1997-05-27 Unisys Corporation Method and apparatus for high-speed efficient bi-directional communication between multiple processor over a common bus
US5822766A (en) * 1997-01-09 1998-10-13 Unisys Corporation Main memory interface for high speed data transfer
US5970253A (en) * 1997-01-09 1999-10-19 Unisys Corporation Priority logic for selecting and stacking data
US8060674B2 (en) 1998-11-09 2011-11-15 Broadcom Corporation Systems and methods for data storage devices and controllers
US20090274017A1 (en) * 1998-11-09 2009-11-05 Siamack Nemazie Mixed-signal single-chip integrated system electronics for data storage devices
US6618780B1 (en) * 1999-12-23 2003-09-09 Cirrus Logic, Inc. Method and apparatus for controlling interrupt priority resolution
US20020009098A1 (en) * 2000-07-14 2002-01-24 International Business Machines Corporation Communication control method and device
US6604160B1 (en) * 2000-09-28 2003-08-05 International Business Machines Corporation Computing system arbitrating and selectively providing resource-seeking tasks with takeaway of non-shareable resources
US6971043B2 (en) 2001-04-11 2005-11-29 Stratus Technologies Bermuda Ltd Apparatus and method for accessing a mass storage device in a fault-tolerant server
US20020152419A1 (en) * 2001-04-11 2002-10-17 Mcloughlin Michael Apparatus and method for accessing a mass storage device in a fault-tolerant server
US7461009B1 (en) 2001-06-29 2008-12-02 Ncr Corporation System and method of sending messages to electronic shelf labels based upon priority
US20050055517A1 (en) * 2001-09-14 2005-03-10 Seagate Technology Llc, A Delaware Corporation Prioritizing commands in a data storage device
US8327093B2 (en) * 2001-09-14 2012-12-04 Seagate Technology Llc Prioritizing commands in a data storage device
US10229077B2 (en) 2014-03-25 2019-03-12 Commissariat A L'energie Atomique Et Aux Energies Alternatives Method for data transfer between real-time tasks using a DMA memory controller

Also Published As

Publication number Publication date
DE2358545A1 (de) 1974-06-06
AU6276673A (en) 1975-05-22
AU475654B2 (en) 1976-08-26
JPS4984758A (enrdf_load_stackoverflow) 1974-08-14
GB1423674A (en) 1976-02-04
CA994919A (en) 1976-08-10
FR2208147B1 (enrdf_load_stackoverflow) 1975-03-21
IT971304B (it) 1974-04-30
FR2208147A1 (enrdf_load_stackoverflow) 1974-06-21
JPS5646615B2 (enrdf_load_stackoverflow) 1981-11-04

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