US3917491A - Methods for fabricating resistant MOS devices - Google Patents

Methods for fabricating resistant MOS devices Download PDF

Info

Publication number
US3917491A
US3917491A US431822A US43182274A US3917491A US 3917491 A US3917491 A US 3917491A US 431822 A US431822 A US 431822A US 43182274 A US43182274 A US 43182274A US 3917491 A US3917491 A US 3917491A
Authority
US
United States
Prior art keywords
sodium
oxide
oxide layer
ions
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US431822A
Inventor
Jr Robert B Oswald
Anthony J Baba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Department of Army
Original Assignee
US Department of Army
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by US Department of Army filed Critical US Department of Army
Priority to US431822A priority Critical patent/US3917491A/en
Application granted granted Critical
Publication of US3917491A publication Critical patent/US3917491A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/906—Dram with capacitor electrodes used for accessing, e.g. bit line is capacitor plate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/953—Making radiation resistant device

Definitions

  • the present invention relates to radiation hardening of metal-oxide semiconductor devices, and more particularly, to a method whereby ion bombardment is used to remove substances from a layer of a semiconductor device by ionic migration.
  • a further object of the invention is to provide a simple method of removing sodium from the oxide layer of an MOS device utilizing ion implantation and hydrofluoric acid etching.
  • the invention is a simple method for removing sodium from the SiO layer once the layer is grown.
  • the thickness of the layer is first increased by approximately 1,000 Angstroms.
  • the layer is then bombarded with negative ions of either oxygen, argon, or helium.
  • the energies of these ions are controlled such that they come to rest in the oxide layer and transfer enough energy to the oxide to release the bound sodium as positive ions of sodium.
  • These sodium ions migrate to the surface of the oxide layer to combine with the large negative charge deposited there by the negative ions.
  • the uppermost layer of the oxide containing the migrated sodium is removed by a buffered hydrofluoric acid etchant.
  • FIG. 1 is a combined isometric and cross sectional view illustrating a typical MOS device with an increased oxide layer grown thereon.
  • FIG. 2 is a flow chart illustrating the essential steps of the invention.
  • the present invention is embodied in a metal-oxidesemiconductor circuit structure having a silicon dioxide (SiO layer depleted of a substantial portion of the sodium atoms normally contained therein.
  • a semiconductor and oxide structure of an MOS device 30 has an increased oxide layer 20 undergoing ionic bombardment.
  • the semiconductor substrate 10 comprises an n-type material of monocrystalline silicon. Other semiconductor materials such as GaAs, GaP, et cetera, may be employed.
  • regions 22 are doped in accordance to methods commonly known in the industry to produce p-regions. This, of course, is done after our method is used to remove the sodium from the oxide layer. After depleting the oxide layer 20 of the sodium, windows are etched into the oxide layer 20 for diffusion of the re gions 22.
  • the final step in the processing of the the MOS device is deposition of the metal source, drain, and gate. 1
  • the oxide layer 20 comprising SiO is permitted to be increased in the growing process by approximately 1,000 Angstroms.
  • the SiO layer is bombarded with negative ions of either oxygen, argon, or helium from an ion implantation machine.
  • the energy of the bombarding ions is maintained ata low level in order to prevent the penetration into the oxide layer beyond the 1,000 uppermost Angstroms.
  • these implanted ions come to rest in the oxide layer their negative charge is deposited on the surface of the oxide and the energy transfer from the bombardment by the ion causes bound sodium in the oxide layer to be released in the form of positive sodium ions.
  • the shallow 1,000 Angstrom upper layer of the oxide contains both the implanted atoms and the sodium atoms. These are removed with a standard buff ered hydrofluoric acid etch solution. Hence, a significant portion of the sodium within the oxide film is reduced. Note: The etching rate of the solution is controlled by means commonly known in the art such that only the uppermost additional 1,000 Angstroms of the oxide layer are removed. The structure is then subjected to impurity diffusion in the conventional manner.
  • the oxide layer thickness is increased by 1,000 Angstroms. Initially in the fabrication of a transistor the oxide thickness is 2,000 Angstroms. For the purpose of radiation hardening, the oxide thickness is increased from 2,000 Angstroms to 3,000 Angstroms by increasing growth time. Once the 3,000 Angstrom thickness is acquired, the active side of the substratum of the transistor is subjected to negative ion beam bombardment with the oxygen ion, 0', produced by a Cameca model IMS 300 ion microanalyzer. It is found that by maintaining the oxygen ion energy at 10 Kev, these ions penetrate only a few hundred Angstroms into the oxide.
  • ion bombardment density 10 ions per square centimeter is sufficient.
  • the transistors are immersed in a dilute solution of acid (HF) to remove the top 1,000 Angstroms of oxide.
  • HF acid
  • the dilute solution of hydrofluoric acid consists of a standard 48 percent solution diluted with high purity water. This dilute solu- 3 tion of hydrofluoric acid reduces the etch rate and provides better control of said etch rate. This insures that the final desired thickness of the oxide layer is accurately obtained.
  • the essential steps of the invention comprise: Step 1 increasing the silicon dioxide layer thickness by approximately 1,000 Angstroms; step 2 bombarding the oxide layer with ions of either oxygen, argon, or helium, of such an energy that these ions only penetrate a few hundred Angstroms into the uppermost portion of the oxide; step 3 allowing the sodium ions to accumulate on the surface of the oxide layer; and, step 4 etching away the uppermost 1,000 Angstroms of the oxide layer.
  • a method for enabling a metal-oxide semiconductor device to withstand the effects of a high radiation environment comprising the steps of:

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Weting (AREA)

Abstract

A method for fabricating radiation resistant MOS devices in which the metal sodium is removed after the oxide is grown by utilizing negative ion implantation. Low energy negative ions penetrate the SiO2 oxide layer depositing their negative charge on the surface of the layer and transferring enough energy to the oxide itself to release the bound sodium in the form of positive ions. The sodium ions drift to the oxide surface due the negative charges thereon. A thin uppermost portion of the SiO2 oxide layer contains both the implanted negative ion charges and the sodium ions. This uppermost layer is etched away using hydrofluoric acid. Removal of the sodium metal from the oxide layer significantly reduces the sensitivity of the MOS device to radiation.

Description

United States Patent 1 1 Oswald, Jr. et al.
[ NOV. 4, 1975 METHODS FOR FABRICATING RESISTANT MOS DEVICES Primary ExaminerG. Ozaki Attorney, Agent, or Firm-Nathan Edelberg; Robert P.
[75] Inventors: Robert B. Oswald, Jr., Bethesda;
Anthony J. Baba, Gaithersburg, Glbson Saul Elbaum b th f Md. O O [57] ABSTRACT [73] Asslgnee: The Umted States of Amenca as A method for fabricating radiation resistant MOS derepresented the Secretary of the vices in which the metal sodium is removed after the Army Washington oxide is grown by utilizing negative ion implantation. [22] Filed: Jan. 8, 1974 Low energy negative ions penetrate the SiO oxide layer depositing their negative charge on the surface [21] Appl 431822 of the layer and transferring enough energy to the oxide itself to release the bound sodium in the form of 52 US. Cl. 148/15; 148/187; 357/91; positive km The sodium ions dn'ft to the Oxide 427/93 face due the negative charges thereon. A thin upper- [51] Int. C1. H0lL.7/54 most Portion of the 2 Oxide layer contains both the 58 Field of Search 148/15, 187; 357/91 implanted negative ion charges and the Sodium ions- This uppermost layer is etched away using hydroflu- [56] Refer Cit d oric acid. Removal of the sodium metal from the oxide UNITED STATES PATENTS layer significantly reduces the sensitivity of the MOS device to radiation. 3,507,709 4/1970 Bower 148/l.5 3,573,454 4/1971 Andersen et al 148/l.5 x 4 Claims, 2 Drawing Figures mg zgbisme i ON QSM T\-\\CKNESS A q ETCHMG 4 SRO).
LAYER US. Patent Nov. 4, 1975 somuM \ON Accumuumou ETG-NG Si 01 LAYER \ON BOMBNZDMENT METHODS FOR FABRICATING RESISTANT MOS DEVICES RIGHTS OF THE GOVERNMENT The invention specified herein may be manufactured, used, or licensed by or for the United States Government for governmental purposes without the payment to the inventor of any royalty thereon.
BACKGROUND OF THE INVENTION The present invention relates to radiation hardening of metal-oxide semiconductor devices, and more particularly, to a method whereby ion bombardment is used to remove substances from a layer of a semiconductor device by ionic migration.
The adverse affects of high energy radiation upon electronic components, particularly of the solid state or semiconductor type, are well known. Gamma-rays, for example, will break sodium-oxygen bonds in oxide layers, producing positive sodium ions. These ions will drift under the influence of the internal electrical fields present during the operation of MOS devices, and will cause the threshold voltage of the devices to shift, rendering them inoperable.
It is accordingly an object of the present invention to provide an improved method for fabricating radiation resistant MOS devices.
A further object of the invention is to provide a simple method of removing sodium from the oxide layer of an MOS device utilizing ion implantation and hydrofluoric acid etching.
SUMMARY OF THE INVENTION The invention is a simple method for removing sodium from the SiO layer once the layer is grown. The thickness of the layer is first increased by approximately 1,000 Angstroms. The layer is then bombarded with negative ions of either oxygen, argon, or helium. The energies of these ions are controlled such that they come to rest in the oxide layer and transfer enough energy to the oxide to release the bound sodium as positive ions of sodium. These sodium ions migrate to the surface of the oxide layer to combine with the large negative charge deposited there by the negative ions. The uppermost layer of the oxide containing the migrated sodium is removed by a buffered hydrofluoric acid etchant.
DESCRIPTION OF THE DRAWINGS These and other objects of this invention will become apparent from the following description and from the accompanying drawings, in which:
FIG. 1 is a combined isometric and cross sectional view illustrating a typical MOS device with an increased oxide layer grown thereon.
FIG. 2 is a flow chart illustrating the essential steps of the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT The present invention is embodied in a metal-oxidesemiconductor circuit structure having a silicon dioxide (SiO layer depleted of a substantial portion of the sodium atoms normally contained therein.
Referring now to FIG. 1, a semiconductor and oxide structure of an MOS device 30 has an increased oxide layer 20 undergoing ionic bombardment. The semiconductor substrate 10 comprises an n-type material of monocrystalline silicon. Other semiconductor materials such as GaAs, GaP, et cetera, may be employed. In accordance with the use of an n-type semiconductor substrate 10 regions 22 are doped in accordance to methods commonly known in the industry to produce p-regions. This, of course, is done after our method is used to remove the sodium from the oxide layer. After depleting the oxide layer 20 of the sodium, windows are etched into the oxide layer 20 for diffusion of the re gions 22. The final step in the processing of the the MOS device is deposition of the metal source, drain, and gate. 1
In our method, once the semiconductor substrate is prepared, the oxide layer 20 comprising SiO is permitted to be increased in the growing process by approximately 1,000 Angstroms. After growth of the additional 1,000 Angstroms, the SiO layer is bombarded with negative ions of either oxygen, argon, or helium from an ion implantation machine. The energy of the bombarding ions is maintained ata low level in order to prevent the penetration into the oxide layer beyond the 1,000 uppermost Angstroms. As these implanted ions come to rest in the oxide layer their negative charge is deposited on the surface of the oxide and the energy transfer from the bombardment by the ion causes bound sodium in the oxide layer to be released in the form of positive sodium ions. These sodium ions then drift to the oxide-surface due to the large negative charge concentrated there by migration of the implanted ion charge after implantation. After bombardment, the shallow 1,000 Angstrom upper layer of the oxide contains both the implanted atoms and the sodium atoms. These are removed with a standard buff ered hydrofluoric acid etch solution. Hence, a significant portion of the sodium within the oxide film is reduced. Note: The etching rate of the solution is controlled by means commonly known in the art such that only the uppermost additional 1,000 Angstroms of the oxide layer are removed. The structure is then subjected to impurity diffusion in the conventional manner.
This method is further explained as illustrated in the following example for the conditions specified and outlined.
EXAMPLE Utilizing a MOS transistor, at the point of the deposition of the SiO oxide layer the oxide layer thickness is increased by 1,000 Angstroms. Initially in the fabrication of a transistor the oxide thickness is 2,000 Angstroms. For the purpose of radiation hardening, the oxide thickness is increased from 2,000 Angstroms to 3,000 Angstroms by increasing growth time. Once the 3,000 Angstrom thickness is acquired, the active side of the substratum of the transistor is subjected to negative ion beam bombardment with the oxygen ion, 0', produced by a Cameca model IMS 300 ion microanalyzer. It is found that by maintaining the oxygen ion energy at 10 Kev, these ions penetrate only a few hundred Angstroms into the oxide. To remove substantially all the sodium ions from the oxide layer an ion bombardment density of 10 ions per square centimeter is sufficient. After bombardment, the transistors are immersed in a dilute solution of acid (HF) to remove the top 1,000 Angstroms of oxide. The dilute solution of hydrofluoric acid consists of a standard 48 percent solution diluted with high purity water. This dilute solu- 3 tion of hydrofluoric acid reduces the etch rate and provides better control of said etch rate. This insures that the final desired thickness of the oxide layer is accurately obtained.
Referring to FIG. 2, the essential steps of the invention comprise: Step 1 increasing the silicon dioxide layer thickness by approximately 1,000 Angstroms; step 2 bombarding the oxide layer with ions of either oxygen, argon, or helium, of such an energy that these ions only penetrate a few hundred Angstroms into the uppermost portion of the oxide; step 3 allowing the sodium ions to accumulate on the surface of the oxide layer; and, step 4 etching away the uppermost 1,000 Angstroms of the oxide layer.
From the above description and drawings it will be apparent that various modifications in the method described in detail may be made within the scope of this invention. Therefore, the invention is not intended to be limited to the specific method described except as may be required by the following claims.
What is claimed is:
l. A method for enabling a metal-oxide semiconductor device to withstand the effects of a high radiation environment comprising the steps of:
a. increasing the thickness of the oxide layer;
b. directing a beam of negative ions into the oxide layer;
c. implanting said beam of negative ions only in the uppermost 1,000 Angstroms of said oxide layer and then d. allowing the sodium atoms in the oxide layer to accumulate on the surface of said layer as sodium atoms and ions; and
e. removing said sodium atoms and ions.
2. The invention according to claim 1 wherein said sodium atoms and ions are removed by etching away the uppermost portion of said oxide layer.
3. The invention according to claim 2 wherein said etching is performed by a diluted buffered hydrofluoric acid solution.
4. The invention according to claim 1 wherein said oxide layer is increased by at least 1,000 additional Angstroms.

Claims (4)

1. A METHOD FOR ENABLING A METAL-OXIDE SEMICONDUCTOR DEVICE TO WITHSTAND THE EFFECTS OF A HIGH RADIATION ENVIRONMENT COMPRISING THE STEPS OF: A. INCREASING THE THICKNESS OF THE OXIDE LAYER, B. DIRECTING A BEAM OF NEGATIVE IONS INTO THE OXIDE LAYER, C. IMPLATING SAID BEAM OF NEGATIVE IONS ONLY IN THE UPPERMOST 1,000 ANGSTROMS OF SAID OXIDE LAYER AND THEN D. ALLOWING THE SODIUM ATOMS IN THE OXIDE LAYER TO ACCUMULATE ON THE SURFACE OF SAID LAYER AS SODIUM ATOMS AND IONS, AND E. REMOVING SAID SODIUM ATOMS AND IONS.
2. The invention according to claim 1 wherein said sodium atoms and ions are removed by etching away the uppermost portion of said oxide layer.
3. The invention according to claim 2 wherein said etching is performed by a diluted buffered hydrofluoric acid solution.
4. The invention according to claim 1 wherein said oxide layer is increased by at least 1,000 additional Angstroms.
US431822A 1974-01-08 1974-01-08 Methods for fabricating resistant MOS devices Expired - Lifetime US3917491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US431822A US3917491A (en) 1974-01-08 1974-01-08 Methods for fabricating resistant MOS devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US431822A US3917491A (en) 1974-01-08 1974-01-08 Methods for fabricating resistant MOS devices

Publications (1)

Publication Number Publication Date
US3917491A true US3917491A (en) 1975-11-04

Family

ID=23713588

Family Applications (1)

Application Number Title Priority Date Filing Date
US431822A Expired - Lifetime US3917491A (en) 1974-01-08 1974-01-08 Methods for fabricating resistant MOS devices

Country Status (1)

Country Link
US (1) US3917491A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4178415A (en) * 1978-03-22 1979-12-11 Energy Conversion Devices, Inc. Modified amorphous semiconductors and method of making the same
US5476816A (en) * 1994-03-28 1995-12-19 Motorola, Inc. Process for etching an insulating layer after a metal etching step
US20100203742A1 (en) * 2009-02-06 2010-08-12 Applied Materials, Inc. Negatively Charged Passivation Layer in a Photovoltaic Cell

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3507709A (en) * 1967-09-15 1970-04-21 Hughes Aircraft Co Method of irradiating dielectriccoated semiconductor bodies with low energy electrons
US3573454A (en) * 1968-04-22 1971-04-06 Applied Res Lab Method and apparatus for ion bombardment using negative ions

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3507709A (en) * 1967-09-15 1970-04-21 Hughes Aircraft Co Method of irradiating dielectriccoated semiconductor bodies with low energy electrons
US3573454A (en) * 1968-04-22 1971-04-06 Applied Res Lab Method and apparatus for ion bombardment using negative ions

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4178415A (en) * 1978-03-22 1979-12-11 Energy Conversion Devices, Inc. Modified amorphous semiconductors and method of making the same
US5476816A (en) * 1994-03-28 1995-12-19 Motorola, Inc. Process for etching an insulating layer after a metal etching step
US20100203742A1 (en) * 2009-02-06 2010-08-12 Applied Materials, Inc. Negatively Charged Passivation Layer in a Photovoltaic Cell
US8338220B2 (en) * 2009-02-06 2012-12-25 Applied Materials, Inc. Negatively charged passivation layer in a photovoltaic cell

Similar Documents

Publication Publication Date Title
CA1071333A (en) Tapered mask method of semiconductor manufacture
US6399448B1 (en) Method for forming dual gate oxide
JPH01125935A (en) Manufacture of semiconductor device
US4532698A (en) Method of making ultrashort FET using oblique angle metal deposition and ion implantation
US4863878A (en) Method of making silicon on insalator material using oxygen implantation
US4096509A (en) MNOS memory transistor having a redeposited silicon nitride gate dielectric
US4092209A (en) Silicon implanted and bombarded with phosphorus ions
US3917491A (en) Methods for fabricating resistant MOS devices
JPS6421919A (en) Manufacture of semiconductor device
US4451303A (en) Diffusion of aluminum
US4045252A (en) Method of manufacturing a semiconductor structure for microwave operation, including a very thin insulating or weakly doped layer
US4305086A (en) MNOS Memory device and method of manufacture
JPS61123152A (en) Separation of semiconductor device
US3666567A (en) Method of forming an ohmic contact region in a thin semiconductor layer
JPH0786199A (en) Fabrication of silicon carbide semiconductor device
US6316337B1 (en) Production process of SOI substrate
JPH039612B2 (en)
US6225231B1 (en) Recovery of damages in a field oxide caused by high energy ion implant process
JPH0412629B2 (en)
JPS5850781A (en) Semiconductor variable capacity element and manufacture thereof
JPS6258544B2 (en)
JP2767642B2 (en) Method for manufacturing semiconductor device
JPS6149427A (en) Manufacture of semiconductor device
JPH0585777A (en) Glass substrate and production thereof
JPS60733A (en) Semiconductor device and manufactur thereof