US3913089A - Method and apparatus for generating a traveling display - Google Patents

Method and apparatus for generating a traveling display Download PDF

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Publication number
US3913089A
US3913089A US383257A US38325773A US3913089A US 3913089 A US3913089 A US 3913089A US 383257 A US383257 A US 383257A US 38325773 A US38325773 A US 38325773A US 3913089 A US3913089 A US 3913089A
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United States
Prior art keywords
display
characters
stroke
counter
line
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US383257A
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English (en)
Inventor
Francis E Albrecht
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Siemens AG
Bunker Ramo Corp
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Bunker Ramo Corp
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Application filed by Bunker Ramo Corp filed Critical Bunker Ramo Corp
Priority to US383257A priority Critical patent/US3913089A/en
Priority to CA202,327A priority patent/CA1032675A/en
Priority to GB2863274A priority patent/GB1471284A/en
Priority to SE7409177A priority patent/SE402498B/xx
Priority to DE19742434386 priority patent/DE2434386A1/de
Priority to IT25562/74A priority patent/IT1017441B/it
Priority to FR7426147A priority patent/FR2238983B2/fr
Priority to JP49086518A priority patent/JPS5045525A/ja
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Publication of US3913089A publication Critical patent/US3913089A/en
Assigned to SIEMENS AKTIENGESELLSCHAFT, A GERMAN CORP. reassignment SIEMENS AKTIENGESELLSCHAFT, A GERMAN CORP. ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: SCHUH, GOTTFRIED
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/04—Deflection circuits ; Constructional details not otherwise provided for

Definitions

  • 340/324 AD; 340/336 and a Second Counter f 2 corres on s a u sro emcremen o e is a 51 1m.cl. ..G06F3/14 h P i P Y [58] Field of Searchong 340/324 AD, 334, 337, 339, t 6 emg meme to e mcre' 340/336 mented in response to an overflow from the first counter.
  • the circuit also includes elements for deter- [56] References Cited mining and indicating the number of predetermined fractional stroke increments which the display is to be UNITED STATES PATENTS incremented and for incrementing the first counter by 3,611,348 l0/197l Rogers 340/324 AD the indicated number.
  • the counts in the first and secg rz 52' :2 0nd counters are utilized for controlling both the e a y e stroke and bit of the stroke of the display at which dis- 3,742,482 6/1973 Albrecht et al. 340/324 AD pl y ofythe first of Successive characters pp for display begins.
  • This invention relates to traveling displays, and more particularly to a method and apparatus for causing the display on a display device such as a cathode ray tube (CRT) to travel or advance in fractional stroke increments.
  • a display device such as a cathode ray tube (CRT)
  • Albrecht, et al. patent Another feature of the beforementioned Albrecht, et al. patent is the capability of displaying information of different types (for example stock IDs and related prices) one-half line spaced from each other, the information being received in succession on a single line.
  • the circuit of the Albrecht, et al patent stored the information of different types in different sections of a memory, reading out the information from one section to refresh one line and reading out information from the other section to refresh the line spaced one-half line below.
  • This technique is wasteful of memory in that two sections of memory are required in order to store information which could be stored in a single section of memory.
  • this invention provides a circuit for use in a cyclically refreshed display device, such as a cathode ray tube (CRT), of the type which generates a plurality of writing strokes for each display line, information characters being displayed by selectively changing the visible state of M bits on each of N strokes for each character.
  • the circuit causes the display to travel in fractional stroke increments.
  • the circuit includes a first counter, each unit increment of which corresponds to a predetermined fractional stroke increment of the display and a second counter each unit increment of which corresponds to a full stroke increment of the display, the second counter being connected to be incremented in response to an overflow from the first counter.
  • the circuit also includes means for determining and indicating the numher of predetermined fractional stroke increments which the display is to be incremented; a means responsive to the number indicated by the determining and indicating means for incrementing the first counter by the number; a means for applying successive characters for display on the display device; and a means responsive to the outputs from the first and second counters for controlling both the stroke and bit of the stroke at which display of the first of the successive characters begins.
  • the circuit includes a means operative at the end of each display line for initiating a retrace of the CRT writing beam, and a means for inhibiting the intensifying of the writing beam for a predetermined time period after the initiating of a retrace.
  • the controlling means is then operative to control both the stroke and bit of the stroke of the last of the successive characters applied to the display at which the means for initiating a retrace is operated.
  • a line of characters to be displayed may contain characters of two different types, characters of one type being displayed a fraction of a line below the characters of the other type.
  • a memory is provided for storing the characters of a line to be displayed in successive address positions, the characters of one type having a predetermined identifier stored with them in the memory. There is a means operative when the memory is being read out for detecting the character type from the stored identifier and for utilizing the character type identification to controlthe character position on the display.
  • FIG. 1 is a schematic block diagram of a circuit of a preferred embodiment of the invention.
  • FIG. 2 is a diagram illustrating the contents of a character storing memory for the embodiment of the invention shown in FIG. 1.
  • FIG. 3A is a diagram illustrating a line of the display for a preferred embodiment of the invention.
  • FIG. 3B is a diagram illustrating the line of the display shown in'FIG. 3A one frame time later under a first assumed set of conditions.
  • FIG. 3C is a diagram illustrating the line of the display shown in FIG. 3A one or more frame times later under a second assumed set of conditions.
  • the display will be considered to be of the type described generally in the beforementioned Albrecht, et al. patent and in greater detail in US. Pat. No. 3,428,851 entitled DATA DISPLAY SYSTEM issued Feb. 18, 1967 to C. Greenblum, and in US. Pat. No. 3,500,327, entitled DATA HANDLING APPA- RATUS issued Mar. 10, 1970 to R. D. Belcher, et a].
  • the display described in these patents is formed by generating a plurality of writing strokes for each. line of the display, a character being formed by selectively intensifying seven out of the 9 bit positions on each of five strokes. Two additional strokes are provided for each character for intercharacter spacing.
  • a display of this type is shown in FIG. 3A for a single exemplary line of the display where the display isbeing utilized to display the New York Stock Exchange Ticker.
  • the circuit for the preferred embodiment of the invention includes a random access memory 10 in which is stored characters for display on the display device as well as a selected number of buffered characters awaiting display.
  • a random access memory 10 in which is stored characters for display on the display device as well as a selected number of buffered characters awaiting display.
  • FIG. 2 the contents of a memory 10 for an illustrative embodiment of the invention are shown. For this embodiment of the invention, it is assumed that 48 characters are displayed on a traveling line and 16 buffered character positions are provided.
  • a character counter 12 is provided which indicates the character position in memory 10 at which read out under control of a read out control circuit 14 is to commence for the line of characters being displayed.
  • character position 11 is the character address contained in counter 12.
  • the circuit also contains an input address counter 16 which indicates the address position in memory 10 at which the next received character is stored. For purposes of illustration, it will be assumed that this counter is pointing to character address 4. Arrows have been provided in FIG. .2 to illustrate these two assumed addresses.
  • the stock market ticker information being displayed is seen to contain two types of information, alphabetic stock identification codes and numeric prices (and also sometimes volumes). It is also seen that the price and volume information is displayed a half-line below the stock ID information. In order to permit the two different types of information to be recognized and distinguished between, an extra bit, bit 8, is provided for each character in memory 10 which bit is marked for the numeric price and volume data. It should also at this point be noted that while memory 10 has been indicated above as containing only the traveling message for display on a given line,
  • this information would be. contained in only a portion of a larger memory which contains information to be displayed for an entire frame on a given display device as well as alternative information to be displayed on the given display device and possibly on other display devices as well.
  • Ifdetector 34 determines that thecharac ter in buffer 20 is a price or volume character, it generates an output on line 36, causing bit 8 of the stored characterto be marked.
  • the signal on line 30 is also'applied to increment input address counter 16 tothe address at which the next received character is to be.
  • a character counter 12 is provided for indicating the character position in memory 10 from which the first character is to be read out to display a traveling line.
  • character I counter 12 there is also a seven state stroke counter 38 and a three state bit counter 40. The functions of these played on the line to be successively read out onto line 42, starting with character position 1 1.
  • Bit 8 of each character read out on line 42 is applied to bit 8 detector 44 which determines whether a bit 8 is present. :Since the characterin character position 11 is part of a stock ID, bit 8 is not marked forithis character, resulting in inverter 50 applying one input to AND gate 52.
  • gate 60 is conditioned to pass the video information from generator 58 to display 63.
  • This device also generates clock pulses during frame retrace which are utilized in a manner to be described later.
  • the outputs from source 64 are shown at various points in the circuit and properly labeled, the line 54 being one such output.
  • FR 1 clock frame retrace one
  • the address stored in counter 76 is compared with the address stored in character counter 12 in a comparator 78. If these two addresses are not the same, which would be the case if there are any buffered characters awaiting display in memory 10, comparator 78 generates an output on no-match line. 80 which conditions gate 82 to pass each succeeding FR clock on line 84 to decrement buffer counter 72 and to increment or step address counter 76.
  • Detectors 90 are essentially decoders which generate an output on a given line depending on the count in buffer counter 72. Thus, there would be one output from detectors 90 if the count in buffer counter 72 was zero, another output if the count was 1, a third output if the count was between 3 and 5, another if the count was between 4 and 6 and the like. There would be some overlap between the counts since shift points would vary depending on whether the number of bits by which the shift was being,
  • the outputs from detectors 90 are applied to a shift control circuit 92 which consists of a number of flip flops, one for each possible shift increment, and gating circuitry for controlling the setting of the proper flop depending on the output from detectors 90 and the existing state of the flops. Circuit 92 generates an output on one of seven lines 94. While circuits 90 and 92 have not been shown or described in detail herein, circuits for performing the functions indicated are shown in the beforementioned Albrecht, et al. patent and similar circuitry would be employed herein.
  • the display is to be stepped in one-third stroke increments.
  • display of a character stroke might begin at bit position one, bit position 4, or bit position 7 on the stroke.
  • the outputson lines 94 indicate the number of one-third stroke increments which the display is to be stepped between successive frames, an output on line 94A indicating that the display is to be incremented by three bits, an.
  • Lines 94 are connected as stepping inputs to threestate bit counter 40. Each of the lines 94 causes counter 40 to be incremented by the number written adjacent thereto. Thus, a signal on line 94A causes the counter to be incremented by one, a signal on line 94D causes the counter to be incremented by four while a signal on line 94G causes the counter to be incremented by 10. An overflow from bit counter 40 on line 96 causes seven state stroke counter 38 to be incremented. Similarly, an overflow on line 98 from stroke counter 38 causes character counter 12 to be incremented. The incrementing of the counters 12, 38 and 40 occurs at a selected clock time during frame retrace (FR N time) when a clock signal appears on line 100.
  • FR N time frame retrace
  • Two signals which are utilized with the circuit of FIG. 1 are a travel signal on line 102 and a not-travel (travel') signal on line 104.
  • a signal appears on travel line 102 when a line which is caused to travel across the display is being refreshed.
  • a signal appears on not travel line 104 at all other times.
  • the lines 102 and 104 may, for example, be outputs from a flip flop which is set by a suitable external device or in response to selected clocks, may be derived directly from an external device, or may be outputs from gates controlled by suitable clocks.
  • the three output lines from stroke counter 38 are applied either in direct or inverted form as inputs to each of seven AND gates l06Al06G, (only three of which are shown in FIG. 1) the other inputs to each of these AND gates being a selected stroke clock, travel line 102, and a sync enable line 108.
  • Sync enable line 108 is the output line from OR gate 110, the inputs to which are output lines 112 and 114 from AND gates 116 and 118 respectively.
  • the inputs to AND gate 116 are a character clock line CM, not travel line 104, and output line 120 from OR gate 122.
  • the inputs to OR gate 122 are various selected line clocks (LA etc.).
  • the inputs to AND gate 118 are a character clock line for the character CN travel line 102, and output line 124 from OR gate 126.
  • the inputs to OR gate 126 are various other selected line clocks (for example lines 2 and 3 for the preferred embodiment of this invention).
  • Sync enable line 108 and not travel line 104 are also connected as inputs to AND gate 130, the final input to this AND gate being the stroke 1 clock line.
  • the outputs from AND. gates 106 and 130 are connected as inputs to OR gate 132.
  • character N is character 49. While this 49th character is, as will be described later, is either partially displayed or not displayed at all, it may be considered as the last character to be displayed.
  • travel line 104 is connected as one input to an AND gate 134, the other input to which is a B1 clock line, while travel line 102 is connected as one input to each of three AND gates 136A-136C, the
  • B7 clock lines respectively and a selected combination of direct and inverted outputs on the two output lines from three state bit counter 40.
  • the output lines from AND gates 134 and 136 are connected as inputsto OR gate 138.
  • OR gate 138 an input is applied to OR gate 138 at bit 1 time of each stroke if the display line is not a traveling line or at either B1, B4 or B7 time of a line, depending on the count in counter 40, if the line is a traveling line.
  • Output line 140 from OR gate 132 is connected as the set input to sync flip flop 142 and through inverter 144 as the reset input to this flip flop.
  • the signal on line 140 is also applied through a six character delay 146 as one input to .AND gate 148. Assuming the presence of an enable signal on line 150, this signal normally being present, AND gate 148 is conditioned to pass the output from delay 146 to the set input of video flip flop 62.
  • Output line 152 from OR gate 138 is connected as the clock input to both video flip flop 62 and sync flip flop 142.
  • Output line 154 from the set side of flip flop 142 is connected to the line sync orline retrace input of display 63.
  • Output line 156 from the reset side of flip flop 142 is connected to the invert reset input of video flip flop 62., Thus, video flip flop 62 is reset when sync flip flop 142 is set. A disable input to the reset side of video flip flop 62 is also provided although this input is not utilized for the present invention.
  • AND gate 130 is deconditioned terminating the signal on line 140. This causes inverter 144 to generate an output which resets flip flop 142. It is assumed that line retrace takes exactly six character times. Thus, when line retrace is completed, delay 146 generates an output which is applied to again set flip flop 62, permitting video display to resume.
  • shift control circuit 92 generates an output on line 94A, causing counter 40 to be incremented by one to a count of one.
  • gate 118 will again be conditioned to generate a sync enable signal on line 108, and the count in stroke counter 38 remaining un-1 changed, AND gate 106A will be conditionedat S1 time of this character to cause a set enable input ,to be applied to snyc flip flop 142.
  • OR gate 138 does not generate a clocking signal to flip flops 62 and 142 until bit four time of the stroke.
  • delay 146 generates a set enable signal to video flip flop 62.
  • a clocking input on line 152 to flip flop 62 isnot generated until three bit times later.
  • video is not enabledfor the first .two bits of the first character stroke, these bits are not visible. The result of this is shown in FIG. 33.
  • a signal again appears on line at S1 time of character 49. I-Iow-.
  • stroke two bit four of character 49 Since delay 146 lasts for six full character times, it is not until stroke two of the first character of line two that the write beam is ready to begin tracing characters on a new line and that a set enabling input is applied to video flip flip 62.
  • character generator 58 is still operating in synchronism with clock source 64. Thus, it has com- I pleted generating the outputs for the first stroke of the first character by this time and is in the process of generating bits for the second stroke of the characteruAt.
  • FIG. 3C illustrates the appearance of this first character as a result of the operations indicated above.
  • a line is required between the last traveling line and the first nontraveling line in order to restore proper synchronization between the character generator and the display.
  • a circuit for causing the display to travel in fractional stroke increments comprising:
  • each unit increment of which corresponds to a full stroke increment of the display said second counter being connected to be incremented in response to an overflow from said first counter;
  • control means for determining the number of predetermined fractional stroke increments which the display is to be incremented and for producing a control signal manifesting such number
  • means responsive to the outputs from said first and second counters for controlling both the stroke and bit of said stroke at which display of the first of said successive characters begins.
  • said means for controlling includes means for utilizing the outputs of said counters to control the stroke and bit at which display of said first character begins only for traveling lines of the display. 3.
  • said means for applying characters to the display is operative during each refresh cycle of the display device;
  • a circuit as claimed in claim 1 including a memory for storing said characters which are successively applied to the display, said memory also functioning as a buffer memory for characters awaiting display; and
  • control means includes means for determining the number of characters awaiting display which are stored in said buffer memory, and means responsive to the number of characters determined for determining said number of predetermined fractional stroke increments.
  • a line of characters to be displayed may contain characters of two different types, characters of one type being displayed a fraction of a line below characters of the other type; and 2 including a memory for storing the characters of a line to be displayed in successive address positions, the characters of one type having a predetermined identifier stored with them in said memory; means operative when said memory is being read out for detecting the character type from the stored identifier; and means for utilizing said character type identification to control the character position on the display.
  • said mem- 3 5 ory is read out twice for each line containing characters of different types; and
  • said means for controlling character position includes means for applying to the display only characters of one type during a first read out for display on a given line and for applying to the display only characters of the other type during the second read out for display a fraction of a line below the characters of the one type.
  • said display 45 is a CRT having a writing beam
  • said first counter is a three state counter.
  • each unit increment of which cor responds to a full stroke increment of the display, said secondcounter being connected to be incremented in response to an overlfow from said first counter;
  • control means for determining the number of predetermined fractional stroke increments which the display is to be incremented and for producing a control signal manifesting such number
  • said first counter is a three state counter.
  • a circuit for controlling the display so that characters of one type are displayed a fraction of a line below characters of the other type comprising:
  • a memory for storing the characters of the line to be displayed in successive address positions, the characters of one type having a predetermined identifier stored with them in the memory; means for successively reading'out the contents of said memory;
  • controlling step includes the step of controlling both the stroke and bit of said stroke at which each retrace is initiated.
  • a first counter each unit'increment of which corresponds to a predetermined fractional stroke incre ment of the display
  • a second counter each unit increment of which cor,-
  • said second counter being connected to be incremented in response to an overflow from said first
  • a random access memory for storing representations of characters to be displayed in fixed locations therein; readout control means for periodically reading from said memory representations of characters to'be displayed;
  • a circuit as claimed in claim 15 including input means for receiving input data to be displayed, a buffer register for temporarily storing said input data, said random access memory being connected to receive data from said buffer register, signal producing means connected to said buffer register and operative to produce a signal manifesting the quantity of data stored therein, and means connecting said signal producing meanswith said control means, whereby said control means is responsive to the quantity of data stored in said buffer register.

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  • Engineering & Computer Science (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
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  • Computer Hardware Design (AREA)
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US383257A 1971-09-08 1973-07-27 Method and apparatus for generating a traveling display Expired - Lifetime US3913089A (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
US383257A US3913089A (en) 1973-07-27 1973-07-27 Method and apparatus for generating a traveling display
CA202,327A CA1032675A (en) 1973-07-27 1974-06-11 Method and apparatus for generating a traveling display
GB2863274A GB1471284A (en) 1971-09-08 1974-06-27 Method and apparatus for generating a travelling display
SE7409177A SE402498B (sv) 1973-07-27 1974-07-12 Forfarande for forflyttning av atergivningen hos en atergivningsanordning i steg, som er brakdelar av en kolumn samt anordning for genomforande av detta forfarande
DE19742434386 DE2434386A1 (de) 1971-09-08 1974-07-17 Verfahren und schaltungsanordnung zum zyklisch erneuerten anzeigen von informationszeichen auf einer anzeigeeinrichtung
IT25562/74A IT1017441B (it) 1973-07-27 1974-07-25 Metodo ed apparecchiatura di tipo perfezionato per generare una vi sualizzazione in movimento
FR7426147A FR2238983B2 (it) 1971-09-08 1974-07-26
JP49086518A JPS5045525A (it) 1973-07-27 1974-07-27

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US383257A US3913089A (en) 1973-07-27 1973-07-27 Method and apparatus for generating a traveling display

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US3913089A true US3913089A (en) 1975-10-14

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JP (1) JPS5045525A (it)
CA (1) CA1032675A (it)
IT (1) IT1017441B (it)
SE (1) SE402498B (it)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024531A (en) * 1974-03-05 1977-05-17 National Research Development Corporation Display devices
US4141003A (en) * 1977-02-07 1979-02-20 Processor Technology Corporation Control device for video display module
US4293855A (en) * 1979-12-31 1981-10-06 Perkins Arthur T Communication device
US4500879A (en) * 1982-01-06 1985-02-19 Smith Engineering Circuitry for controlling a CRT beam
WO1987001848A1 (en) * 1985-09-23 1987-03-26 Colour Cells Pty. Limited Multi-coloured illuminated dynamic display
WO1988002908A1 (en) * 1986-10-17 1988-04-21 Colour Cells Pty. Limited Multi-coloured illuminated dynamic display
US5454104A (en) * 1993-02-25 1995-09-26 Steidlmayer Software, Inc. Financial data event flow analysis system with study conductor display

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3611348A (en) * 1969-08-05 1971-10-05 Ultronic Systems Corp Character display system
US3643252A (en) * 1967-08-01 1972-02-15 Ultronic Systems Corp Video display apparatus
US3716842A (en) * 1971-05-05 1973-02-13 Ibm System and method for the continuous movement of a sheet having graphic subject matter thereon through a window of a display screen
US3742482A (en) * 1971-09-08 1973-06-26 Bunker Ramo Method and apparatus for generating a traveling display

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3643252A (en) * 1967-08-01 1972-02-15 Ultronic Systems Corp Video display apparatus
US3611348A (en) * 1969-08-05 1971-10-05 Ultronic Systems Corp Character display system
US3716842A (en) * 1971-05-05 1973-02-13 Ibm System and method for the continuous movement of a sheet having graphic subject matter thereon through a window of a display screen
US3742482A (en) * 1971-09-08 1973-06-26 Bunker Ramo Method and apparatus for generating a traveling display

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4024531A (en) * 1974-03-05 1977-05-17 National Research Development Corporation Display devices
US4141003A (en) * 1977-02-07 1979-02-20 Processor Technology Corporation Control device for video display module
US4293855A (en) * 1979-12-31 1981-10-06 Perkins Arthur T Communication device
US4500879A (en) * 1982-01-06 1985-02-19 Smith Engineering Circuitry for controlling a CRT beam
WO1987001848A1 (en) * 1985-09-23 1987-03-26 Colour Cells Pty. Limited Multi-coloured illuminated dynamic display
WO1988002908A1 (en) * 1986-10-17 1988-04-21 Colour Cells Pty. Limited Multi-coloured illuminated dynamic display
US5454104A (en) * 1993-02-25 1995-09-26 Steidlmayer Software, Inc. Financial data event flow analysis system with study conductor display

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IT1017441B (it) 1977-07-20
JPS5045525A (it) 1975-04-23
SE402498B (sv) 1978-07-03
SE7409177L (it) 1975-01-28
CA1032675A (en) 1978-06-06

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Owner name: SIEMENS AKTIENGESELLSCHAFT, BERLIN AND MUNCHEN, GE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:SCHUH, GOTTFRIED;REEL/FRAME:004038/0813

Effective date: 19810413

AS Assignment

Owner name: ALLIED CORPORATION COLUMBIA ROAD AND PARK AVENUE,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:BUNKER RAMO CORPORATION A CORP. OF DE;REEL/FRAME:004149/0365

Effective date: 19820922