US3900719A - Hybrid arithmetic device - Google Patents

Hybrid arithmetic device Download PDF

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Publication number
US3900719A
US3900719A US355061A US35506173A US3900719A US 3900719 A US3900719 A US 3900719A US 355061 A US355061 A US 355061A US 35506173 A US35506173 A US 35506173A US 3900719 A US3900719 A US 3900719A
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output
resistor
amplifier
input
transistor amplifier
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US355061A
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Satoshi Yamauchi
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Ricoh Co Ltd
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Ricoh Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06J—HYBRID COMPUTING ARRANGEMENTS
    • G06J1/00—Hybrid computing arrangements

Definitions

  • a hybrid arithmetic device in which a load [52] s Cl. 235/5052; 235/1505; 235/194 is connected to a constant current or voltage source, 5 1 C
  • the present invention relates to a hybrid arithmetic device of the type in which multiplication or division may be electrically effected in a digital-to-analog conversion process.
  • Analog and digital multipliers and dividers are widely used in computers and other data processing units.
  • two analog inputs representing the operands such as a multiplicand and multiplier. or dividend and divisor are converted into signals representing the logarithms of the two operands so that the product or quotient may be obtained by the addition or subtraction of the logarithms.
  • the output signal representing the sum of or difference between the logarithms is converted into a signal representing the antilogarithm thereof.
  • the stability of the logarithmic multipliers and dividers must be improved. As a result their circuits become very complex in construction.
  • the control of the registers, adders and subtractors is extremely complicated and the speed is relatively low.
  • One of the objects of the present invention is to provide a hybrid arithematic device comprising in combination analog and digital arithmetic and functional circuits.
  • Another object of the present invention is to provide a high-speed hybrid arithmetic device simple in construction and capable of carrying out arithmetic operations with a higher degree of accuracy and at a considerably higher speed than digital arithmetic devices.
  • a constant voltage circuit or source is connected to a first resistor to which in turn is connected in Series a second resistor.
  • the constant voltage source and the first resistor constitute a constant current source for controlling a constant current flowing through the second resistor.
  • To the second resistor is connected a third resistor to which in turn is connected in series a load resistor.
  • the constant current source and the second resistor constitute a constant voltage circuit for controlling a constant voltage across the third resistor.
  • the constant voltage source and the third resistor constitute a constant current source for controlling a constant current flowing through the load resistor.
  • the resistances of the resistors which determine the constant voltages and currents of the constant current and voltage sources are varied in response to digital signals representing operands such as a multiplicand, multiplier, dividend and divisor.
  • digital-toanalog converters are used.
  • FIGS. I, 2, 3, and 4 are circuit diagrams used for the explanation of the underlying principle of the present invention.
  • FIGS. 5-A, -B. -C and -D are circuit diagrams of the digital-to-analog converters used in the present invention.
  • FIG. 6 is a circuit diagram of a hybrid arithmetic device in accordance with the present invention.
  • FIG. 7 is a circuit diagram used for the explanation of one application of a hybrid arithmetic device in accordance with the present invention.
  • FIG. 8 is a circuit diagram of another hybrid arithmetic device in accordance with the present invention.
  • a first constant voltage circuit or source comprising a resistor R a Zener diode ZD and a transistor Tr, is provided for a resistor R, and a first constant current circuit or source comprising the first constant voltage circuit and the resistor R, is provided for a resistor R R
  • a second constant voltage circuit or source comprising the resistors R R, and R the Zener diode ZD, a diode D and the transistors Tr, and Tr is provided for a resistor R and a second constant current circuit comprising the second constant voltage circuit and the resistor R is provided for a resistor R
  • the voltage E across the zener diode ZD and the voltage drop E across the base and emitter of the transistor Tr are constant so that the current I, flowing through the resistor R, is given by where E, 15 E
  • the voltage across the resistor R is given by (2) In like manner the current flowing through
  • the circuit shown in FIG. I is the most fundamental circuit of the present invention, and when a more accurate output is required, a circuit shown in FIG. 2 is used which is substantially similar to that shown in FIG. 1.
  • Eq. (5 l holds for the voltage E across the Zener diode ZD and the voltage E across the output resistor R in the circuit shown in FIG. 2.
  • Two differential amplifiers A, and A whose gain is very high are inserted in the circuit shown in FIG. 2 in order to feed back the outputs thereof to their negative terminals through Dar- Iington circuits Tr and Tr and Tr and Tr and Tr There fore the stability and accuracy of the constant current circuits may be further improved over the circuit shown in FIG. I.
  • FIGS. 3 shows an operational amplifier of the inverting configuration, and when the gain of the differential amplifier A is almost infinity, the input current thereof is almost zero so that the relation between the current l flowing through the resistor R and the current I flowing through the resistor R is given by This means that the circuit shown in FIG. 3 functions as a constant current circuit or source for the load re sistor R...
  • the circuit shown in FIG. 4 functions as a multiplier or divider depending upon the combination of the resistors R R R and R
  • the magnitudes of the resistors must be varied so as to represent the multiplicand, multiplier. dividend and divisor which are fed in the form of digital signals.
  • digital-to-analog converters of the types shown in FIGS. S-A to 5-D are used.
  • weighted resistors are connected in series or parallel as is well known in the art, and a contact or contacts across a resistor or resistors are closed or opened depending upon a given digital signal.
  • the resistors R R represent weights equal to successive powers of 2. That is, they represent weights r. 2r, 4r and Sr, respectively.
  • the switches S S S and S shunt the resistors R R respectively.
  • the decimal digit 6 which may be represented by ()1 H)" in the pure binary code be converted into the analog signal.
  • the switches S and 5 are opened so that the combined resistance Rs becomes Rx 2r 4r or which is the resistance representing the decimal digit
  • FIG. 6 illustrates a hydrid arithmetic device in accordance with the present invention comprising the circuit shown in FIG. 3 and the digital-to-analog converter shown in FIG. S-A.
  • the resistors R and R are shown as comprising a weighted resistor network of the type shown in FIG. S-A.
  • a dividend is represented by the magnitude of the resistor R
  • a divisor is represented by the magnitude of the resistor R to carry out the division based upon Eq.
  • a constant current source I0 may comprises the Zener diode ZD and the differential amplifier A, as shown in FIG. 2 or may be any conventional constant current source.
  • the internal resistance of the constant current source I0 corresponds to the resistor R, shown in FIG. 2.
  • a first arithmetic device comprising the constant current source 10, and the resistors R R and R, carries out the division of (the number of students who selected a first answer/ the total number of students).
  • the output of the differential amplifier A in the first hybrid arithmetic device is applied through a signal line 1 to the input of a second arithmetic device comprising the resistor R the con stant current source and the resistors R and R
  • a second arithmetic device comprising the resistor R the con stant current source and the resistors R and R
  • the resistors R R and so on are represented by the resistors R and so on, respectively.
  • the voltage across or current flowing through each of the resistors R,,., R and so on represents the number of students who selected a specific answer/the total number of memeples.
  • the output of the first arithmetic circuit may be derived through the operational amplifier A or instead of the resistor R an ammeter is inserted so that the teacher may directly read the ratio.
  • the digital-to-analog converter of the type shown in FIG. S-B is used.
  • the hybrid arithmetic device shown in FIG. 8 gives the result of a division or multiplication in the form of a digital output, and is based upon the circuit shown in FIG. 3. That is, the circuit comprising the differential amplifier A, and the resistors R, and R,, which are shown as comprising a weighted resistor network is substantially similar in construction to the divider shown in FIG. 3.
  • the hybrid arithmetic device shown in FIG. 8 comprises a register 13, a voltage comparator l4 and a generalpurpose analog-to-digital converter comprising the flipflop IS, the weighted resistor network R and the differential amplifier A
  • the registers I] and 13 also function as a counter, and the flip-flop 15 is set in response to the clear input and reset in response to the output of the comparator 14.
  • the flipflop 15 is set in response to the clear input before the arithematic device is actuated.
  • the digital signals rep resenting the digits A and B are stored in the registers 11 and 12, respectively and the analog voltage representing the quotient A/B is derived from the differential amplifier A,, and is applied to one input terminal of the comparator 14. Since the flip-flop 15 is set, the clock signals are transmitted through a gate G to the register I3 which functions as a counter in this case.
  • the transistors Trare turned on and off so that the analog voltage representing the Content in the register 13 is derived from the differential amplifier A and is applied to the other input terminal of the comparator 14.
  • the coincidence signal is derived from the comparator I4 and applied to the flipflop 15 so that the latter is reset.
  • the gate G is closed so that the clock signals are interrupted to be applied to the register 13.
  • the content in the register 13 represents the quotient A/B.
  • a multiplicand is set into the register 12 whereas a multiplier, into the register I3.
  • the output voltage of the amplifier A co incides with that of the amplifier A the clock pulses are interrupted to be applied to the register II. (The circuit for this purpose is now shown).
  • the content in the register 11 represents the product B-C.
  • a hybrid arithmetic, device comprising:
  • a first stage including a first resistor, a Zener diode connected to said first resistor, a first transistor am plifier having an output and an input, second and third resistors connected to the output of said first transistor amplifier, a first operational amplifier having a plurality of inputs and an output, the output thereof being connected to the input of said first transistor amplifier, one of said inputs of said first operational amplifier being connected to the point of interconnection between said Zener diode and said first resistor, the other input of said first operational amplifier being connected to a feedback path from the output of said first transistor amplifier;
  • a second stage including a second transistor amplifier having an input and an output, fourth and fifth resistors connected to the output of said second transistor amplifier, a second operational amplifier having a plurality of inputs and an output, the output of said second operational amplifier being connected to the input of said second transistor amplifier, one of the inputs of said second operational amplifier being connected to the output of said first transistor amplifier and the other input thereof being connected to a feedback path from the output of said second transistor amplifier;
  • a hybrid arithmetic device as defined in claim I in which the second and the fifth, output resistor are set to the values of a multiplicand and a multiplier, respectively, and the value of the output voltage is proportional to the product of said multiplicand and multiplier.
  • a hybrid arithmetic device as defined in claim I in which a plurality of additional stages, substantially identical to said second stage, are connected in parallel to the output of said second transistor amplifier, a resistor in each of said additional stages being representative of a particular dividend in relationship to a common divisor represented by said second resistor, another resistor in each of said additional stages being representative of a particular quotient resulting from the dividing operation.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Automation & Control Theory (AREA)
  • Evolutionary Computation (AREA)
  • Fuzzy Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Analogue/Digital Conversion (AREA)
US355061A 1972-05-01 1973-04-27 Hybrid arithmetic device Expired - Lifetime US3900719A (en)

Applications Claiming Priority (1)

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JP47043497A JPS5225217B2 (enrdf_load_stackoverflow) 1972-05-01 1972-05-01

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US3900719A true US3900719A (en) 1975-08-19

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US (1) US3900719A (enrdf_load_stackoverflow)
JP (1) JPS5225217B2 (enrdf_load_stackoverflow)
DE (1) DE2322156A1 (enrdf_load_stackoverflow)
FR (1) FR2183477A5 (enrdf_load_stackoverflow)
GB (1) GB1437981A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4334277A (en) * 1977-09-28 1982-06-08 The United States Of America As Represented By The Secretary Of The Navy High-accuracy multipliers using analog and digital components
US20150130438A1 (en) * 2013-11-14 2015-05-14 Littelfuse, Inc. Overcurrent detection of load circuits with temperature compensation

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5227266U (enrdf_load_stackoverflow) * 1975-08-18 1977-02-25

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3293424A (en) * 1963-05-28 1966-12-20 North American Aviation Inc Analog multiplier
US3309508A (en) * 1963-03-01 1967-03-14 Raytheon Co Hybrid multiplier
US3400257A (en) * 1964-10-05 1968-09-03 Schlumberger Technology Corp Arithmetic operations using two or more digital-to-analog converters
US3428790A (en) * 1965-10-14 1969-02-18 Honeywell Inc Analog-digital hybrid divider apparatus using fractional arithmetic
US3602707A (en) * 1969-05-23 1971-08-31 Howard E Jones Analogue multiplier-divider circuit including a pair of cross-coupled transistor circuits
US3634659A (en) * 1965-10-23 1972-01-11 Adage Inc Hybrid computer using a digitally controlled attenuator

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3309508A (en) * 1963-03-01 1967-03-14 Raytheon Co Hybrid multiplier
US3293424A (en) * 1963-05-28 1966-12-20 North American Aviation Inc Analog multiplier
US3400257A (en) * 1964-10-05 1968-09-03 Schlumberger Technology Corp Arithmetic operations using two or more digital-to-analog converters
US3428790A (en) * 1965-10-14 1969-02-18 Honeywell Inc Analog-digital hybrid divider apparatus using fractional arithmetic
US3634659A (en) * 1965-10-23 1972-01-11 Adage Inc Hybrid computer using a digitally controlled attenuator
US3602707A (en) * 1969-05-23 1971-08-31 Howard E Jones Analogue multiplier-divider circuit including a pair of cross-coupled transistor circuits

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4334277A (en) * 1977-09-28 1982-06-08 The United States Of America As Represented By The Secretary Of The Navy High-accuracy multipliers using analog and digital components
US20150130438A1 (en) * 2013-11-14 2015-05-14 Littelfuse, Inc. Overcurrent detection of load circuits with temperature compensation
US9411349B2 (en) * 2013-11-14 2016-08-09 Litelfuse, Inc. Overcurrent detection of load circuits with temperature compensation

Also Published As

Publication number Publication date
FR2183477A5 (enrdf_load_stackoverflow) 1973-12-14
GB1437981A (en) 1976-06-03
DE2322156A1 (de) 1973-11-08
JPS5225217B2 (enrdf_load_stackoverflow) 1977-07-06
JPS495236A (enrdf_load_stackoverflow) 1974-01-17

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