US3869854A

US3869854A - Solid state electronic control

Info

Publication number: US3869854A
Application number: US359188A
Authority: US
Inventors: James A Church
Original assignee: Individual
Current assignee: Individual
Priority date: 1973-05-10
Filing date: 1973-05-10
Publication date: 1975-03-11
Anticipated expiration: 1992-03-11

Abstract

A solid state timing and cycling device utilizing integrated circuits and other discrete solid state components to control the operation of electrically actuated remote control valves for the purpose of automatically programming the operation of all types of systems designed to distribute water for irrigation, spraying, and humidification of plant materials. The control comprises six sections including a digital readout clock circuit, a calendar circuit, an hours memory circuit, a station output board, an internal power supply and an external power output circuit. The internal power supply is common to all sections of the control except power output to the electrically controlled valves in the field and the external power output circuit actuates the electrically operated remote control valves.

Description

United States Patent [191 Church 9 1 SOLID STATE ELECTRONIC CONTROL [76] inventor: James A. Church, 3570 Cortez,

Dallas, Tex. 75220 [22] Filed: May 10, 1973 [21] -Appl. No.: 359,188

[52] US. Cl 58/33, 137/6242, 239/7 D [51] Int. Cl..... G04c 13/06, G04c 23/12, E03b 7/07 [58] Field of Search 58/23, 4, 4 A, 24 R, 25,

58/33, 152 R; l37/624.l8, 624.2; 239/6770;

[56] References Cited UNITED STATES PATENTS 3,120,652 2/1964 Weighton et a1 58/145 R 3,234,410 2/1966 Sherman 137/6242 X 3,440,434 4/1969 Yates et al..... 137/624.2 X 3.479.812 11/1969 Kramer 58/23 A X 3.664.116 5/1972 Emerson et al.... 58/23 A 3.669.352 6/1972 Zaphiris 239/70 3.681.914 8/1972 Loewengart 58/24 R 3.721.084 3/1973 Dargent 58/5 OR T 14 05 ELEMENT T T cfoa DIVIDE BY SIXTEEN COUNTER AM PM INDICATOR 9 BINARYCODED DECIMAL DECODER B4 Mar. 11, 1975 3,732,685 5/1973 Haydon 553/26 Primary Examiner-Edith Simmons Jackmon Attorney, Agent, or FirmArthur M. Sloan [5 7] ABSTRACT A solid state timing and cycling device utilizing integrated circuits and other discrete solid state components to control the operation of electrically'actuated remote control valves for the purpose of automatically programming the operation of all types of systems designed to distribute water for irrigation, spraying, and humidification of plant materials. The control comprises six sections including a digital readout clock circuit, a calendar circuit, an hours memory circuit, a station output board, an internal power supply and an external power output circuit. The internal power supply is common to all sections of the control except power output to the electrically controlled valves in the field and the external power output circuit actuates the electrically operated remote control valves.

36 Claims, 8 Drawing Figures B C G g E C U DE BY c DECADE COUNTER l SIX COUNTER R COUNTER cc V TE TRANSIST CC SCHMITT TRIGGER DIVIDE EY SIX DIVIDE BY TEN DlVlDE BY TEN DIVIDE BY 51X TRIPLE LINE RECEIVER {QQIENIEU MARI 1 1975 1 SOLID STATE ELECTRONIC CONTROL This invention relates to a solid state timing and cycling device to control operation of electrically actuated remote control valves for automatically programming the operation of all types of systems designed to distribute water for irrigation, spraying, and humidification of plant materials of all types.

The control device of the invention includes six sections as follows:

I. A digital readout clock circuit including wave shaping and frequency division to obtain 1 pulse per minute time base form the line frequency,

2. A calendar circuit which changes day indication each 24 hours,

3. An hours memory circuit which tracks the digital readout. No visual indicators are connected to this circuit,

4. A station output board which contains as many sections as needed to control the irrigation or water distribution system. In the embodiment herein described a five output board is shown for purposes of illustration. Each section can be set individually for the time desired for that station to operate a section of the entire system.

5. An internal power supply which in the embodiment of the invention described herein supplies volts, regulated plus or minus (1) 0.25 volt, at up to l ampere and is common to all sections of the control except power output to the electrically controlled valves in the field.

6. An external power output circuit for operation or actuation of the electrically operated remote control valves supplies power through relays controlled by the station output board and regulated through the primary power circuit which may include a suitable transformer and/or rectifier as required for operation of said valves.

Accordingly it is an object of the subject invention to provide an improved solid state electronic irrigation control.

Another object of the subject invention is to provide an improved solid state timing and cycling device.

Yet another object of the subject invention is to provide a solid state timing and cycling device which utilizes integrated circuits and other discrete solid state components.

A further object of the subject invention is to provide an improved solid state timing and cycling device to control the operation of electrically actuated remote control valves.

Still another object of the subject invention is to provide an improved solid state timing and cycling device to automatically program the operation of all types of water distribution systems.

An additional object of the subject invention is to provide an improved control system for automatically programming the operation of irrigation, spraying and humidification systems.

Yet a furter object of the subject invention is to provide an improved solid state timing and cycling device including six sections.

Another object of the subject invention is to provide an improved solid state timing and cycling device including a digital readout clock circuit, a calender circuit, an hours memory circuit, a station output board, an internal power supply, and an external power output circuit.

Additional objects, the features and nature of the invention and the advantages thereof will become apparent by reference to the detailed description of illustrated embodiments, the appended claims and the accompanying drawings, in which:

FIGS. 1, 1A, and IB are a schematic diagram showing an internal power supply, a digital readout clock circuit, a calendar circuit, and an hours memory circuit in accordance with the invention.

FIG. 2 is a schematic diagram of a data collection gate in accordance with the invention.

FIG. 3 is a schematic diagram of a five station output board in accordance with the invention.

FIG. 4 is a schematic diagram of one alternate output board in accordance with the invention.

FIG. 5 is a schematic diagram of a second alternate output board in accordance with the invention.

FIG. 6 is a schematic diagram of an external power supply circuit in accordance with the invention.

Turning to FIG. 1, digital readout clock circuit 1 is shown connected to l4

day calendar circuit

2, 12 hour memory circuit 3, and internal power supply 4. AM-PM indicator 5 is part of the digital readout clock circuit 1.

Sixty Hertz line frequency is fed into one-third of a triple line receiver 6 such as the triple line receiver numbered 8Tl4 sold by Signetics of 811 East Arques Avenue; Sunnyvale, California; and described on pages I 17 through 180 of Signetics Digital Manual 8000 Series TTL/MSI Copyrighted 1971 and showing Signetics code no. D253 DlG-0O2-l 1-50M as a triple line receiver designed for applications requiring digital information to be transmitted over long lengths of coaxial cable, strip line, or twisted pair transmission lines. The Receivers high impedance input structurepresents a minimal load to the driver circuit and allows the transmission line to be terminated in its characteristic impedance to minimize line reflections. The built-in hysteresis characteristic of the 8Tl4 also makes it ideal for such applications as Schmitt triggers, one-shots and oscillators. Other suitable devices than the Signetics device described may be used.

The 60 Hertz line frequency is shaped into a square wave by the Schmitt trigger action of the integrated circuit triple line receiver 6. The 60 Hertz square wave is then fed into a divide by six 7, through a divide by 10 8, a divide by 10 9, and a divide by six 10 to obtain a total of divide by 3600. A 1 pulse per minute output is obtained to be used as the time base for the clock 1.

Divide by six 7 and divide by six 10 may be the divide by six portion of a divide by 12 counter/storage element numbered 8288 sold by Signetics mentioned heretofore and described on pages l33-l38 of Signetics Digital Manual 8000 Series TTL/MSI referred to supra. Divide by 10 8 and divide by 10 9 may be the decade counter numbered 8292 sold by Signetics mentioned heretofore and described on pages -150 of Signetics Digital Manual 8000 Series TTL/MST referred to supra. Other suitable devices than the Signetics devices described above may be used.

The 1 pulse per minute output is fed into the first decade counter 11 and the binary coded decimal output is decoded by the binary coded decimal decoder 12 and drives the seven segment readout 13 for minutes indication.

First decade counter 11 may be Signetics decade counter numbered 8292 described supra. Binary coded decimalfdecoder 12 may be the seven segment decoder numbered 8 T 4.sold by Signetics mentioned heretofo're and-describedonpages 1'53through 156 of Signetics Digital Manual8000 Series TTL/MSI refe-rred to supra. Other suitable devices than the Signetics devices described may be used.

a A.signal generated by the fall of the D output ofthe decade. counter 11 is fed into a divide by six counter 14 to obtaintens of minutes indication on the digital readout 85.

The divide by six counter 14 may be Signetics divide by 12 counter/storage element numbered 8288, described supra.

The D output of the divide by six 14 generates the signal fed into the second decade counter 15 to obtain hours, indication on the readout 87.

The second decade counter 15 may be Signetics decade counter numbered 8292 described supra. To obtain tens of hours indication, and unused flipflop in the tens of minutes counter 15 and a discrete NPN transistor 16 are used to turn the B and C seg ments of the fourth readout 17 on and off.

A flip-flop in the second divide by six of the frequency divider chain and two

NPN transistors

18 and 19 are used to obtain AM and PM indications on the

pilot light indicators

134 and 133 respectively,

transistors

18 and 19 beingtriggered by the tens of hours indicator.

Resistor 20 is a base bias resistor for transistor 18 and resistor 21 is a base bias resistor for transistor 19.

When the PM indication changes to AM, a signal is fed to a divide by 16 counter 22, and its binary coded decimal output is decoded by a one of 16 decoder 23.

Divide by 16 counter 22 may be the binary counter numbered 8293 sold by Signetics mentioned heretofore and described on pages 145-150 of Signetics Digital Manual 8000 Series TTL/MSI referred to supra. One of sixteen decoder 23 may be the 4-line to l6-line decoder/demultiplexer numbered N74l54 sold by Signetics mentioned heretofore and described on pages 135 through 136 of Signetics Digital Manual 54/7400 TTL Copyrighted 1971 and showing Signetics code no. D288 DlG-007-8l 50M. Other suitable devices than the Signetics devices described above may be used.

The output of the one of 16 decoder 23 is inverted by one of the inverters 24 through 37 and fed through one of transistor base bias resistors 39 through 51 to the base of one of NPN transistors 52 through 65.

Inverters 24 through 37 may be the hex inverters numbered N7404 sold by Signetics mentioned heretofore and described on pages 17 and 18 of Signetics Digital Manual 54/7400 TTL referred to supra. Other suitable devices than the Signetics devices described above may be used.

The transistors 52 through 65 which are switching transistors provide power for indicator lights 66 through 79 corresponding to the days of the week for the required calendar which is illustrated here as a 2 week period, thus SMTWTF SS MTWTFS for Sunday, Monday, Tuesday, Wednesday, Thursday, Friday, Saturday, Sunday, Monday, Tuesday, Wednesday, Thursday, Friday, Saturday.

The emitter electrodes of transistors 52 through 65 are grounded at ground 80.

A signal generated by the fifteenth pulse causes the divide by 16 counter 22 to be reset to the first day of the 2 week period.

- The hours memory circuit 3 includes a divide by 12 counter 81 and a one of 16 decoder 82. The divide by 12 counter is shown grounded at 83.

The hours memory circuit 3 divide by 12 counter 81 may. be Signetics divide by 12 counter/storage element numbered 8288, described supra. The one of 16 decoder 82 may be Signetics 4-line to l6-line decoder/- demultiplexer numbered N74l54, described supra. Other suitable devices than the Signetics devices described above may be used.

A signal derived from the hours decade counter 15 is fed into the divide by 12 counter 81, and the count advances as indicated on the visual readout in the clock circuit. Since chip 81 is a divide by 12 counter, it is automatically reset after the count of 12, but to insure synchronism with the clock readout, the divide by 12 counter 81 receives the same data pulse that resets the clock read out to 1:00 oclock. This data signal is generated twice in 24 hours.

Binary coded

decimal decoders

84 and 86 are equivalent to binary coded decimal decoder 12 and perform in the same manner as binary coded decimal decoder 12. Signetics seven segment decoder 8T04 described supra in regards to binary coded decimal decoder 12' may also be used for binary coded

decimal decoders

84 and 86.

Seven segment readouts and 87 are equivalent to seven segment readout 13.

The binary coded decimal decoder 84 is grounded by ground 88.

Resistor 89 is a base bias resistor for the base of discrete transistor 16 which is grounded at ground 90.

Schmitt trigger 91 is a monostable multivibrator which acts as a data pulse generator to reset the divide by six counter integrated circuit 14, the second decade counter integrated circuit 15, and the divide by 12 counter 81 of the 12 hour memory circuit 3.

Schmitt trigger 91 may be the monostable multivibrator numbered N7412l sold by Signetics mentioned heretofore and described on pages 1 15 through 1 18 of Signetics Digital Manual 54/7400 TTL described supra. Other suitable devices than the Signetics device described above may be used.

Schmitt trigger 91 is grounded at 92. Resistor 94 and capacitor 93 comprise an RC circuit to determine pulse length.

The designation Vcc where it occurs, signifies the positive voltage, typically 5 volts plus or minus 0.25 volts as indicated above.

Diode 95 which is a rectifier to block current and resistor 96 together form a wave shaping circuit network.

Capacitor 97 is a high frequency bypass capacitor which is grounded at ground 98. Typically capacitor 97 may have a value of 0.01 micro farads; however, a suitable capacitor of any appropriate value may be utilized.

Resistor 99 brings the AC from the transformer sec ondary winding 124 to the triple line receiver 6 which is a wave shaping circuit.

Capacitor 100 is a bypass capacitor which is grounded at ground 101.

Triple line receiver 6 is connected to ground at 102 and 103. Divide by six counter 14 is grounded at 104. Second decade counter 15 is grounded at 105. Divide by six 7 is grounded at 106. Divide by 10 8 and divide by 10 9 are grounded at 107 and 108 respectively. Divide by six 10 is grounded at 109.

Divide by 16 counter 22 is grounded at 110.

The AM-PM indicator is grounded at 111.

Capacitor 112 is a bypass capacitor which is connected to ground 113.

First decade counter 11 is grounded at 114.

Wiper or switch arm 115 and switch

contacts

116, 117, 118, 119, and 120 together comprise a one pole five position make before break time setting switch in which as wiper arm 115 is advanced to the right it picks up faster pulses which allows for rapid time setting. Contact 116 gives 1 pulse per minute, contact 117 gives 6 pulses per minute, contact 118 gives 60 pulses per minute, contact 119 gives 600 pulses per minute, and contact 120 gives 3,600 pulses per minute.

Power source 121 typically may supply 120 volts AC at 50-60 Hertz. Switch 122 may be opened to disconnect the power source 121.

Coils

123 and 124 are the primary and secondary windings respectively of a transformer which has a core 125. The secondary winding 124 is grounded to ground 126.

Diodes

127 and 128 are rectifiers to convert AC current to pulsed DC current.

Capacitor 129 is a filter capacitor which is grounded at 130.

Voltage regulator 131 may be the linear integrated circuit manufactured under the number LM309 by Signetics mentioned heretofore and described on page 93 of Signetics Linear Data Book, Volume 1, Copyrighted 1971. Voltage regulator 131 is grounded at ground 132.

PM pilot light 133 and AM pilot light 134 were indicated above in discussion of the AM-PM indicator circuit 5.

Diodes

135 and 136 are rectifiers for current limitation.

Turning to FIG. 2

switches

146, 147, 148, and 149 are shown connected to

output pins

1, 2, 11, and 12 of the one of 16 decoder 82 of the 12 hour memory circuit 3.

Switches

146, 147, 148, and 149 make and break contact with the three input NOR gate 162 through

isolation diodes

155, 156, 157, and 158, respectively. Switches and diodes similar to

switches

146, 147, 148, and 149 and

diodes

155, 156, 157, and 158 connect and disconnect output pins 3 through of one of 16 decoder 82 to three input gate 162 as indicated by dashed lines in FIG. 2.

Isolation diode 159 is connected between the collector electrode of transistor 52 and pilot light 66 of the 14 day calendar circuit 2. Likewise isolation diode 160 is connected between the collector electrode of transistor 53 and pilot light 67; isolation diode 161 is connected between the collector electrode of transistor 64 and pilot light 78; and isolation diode 162 is connected between the collector electrode of transistor 65 and pilot light 79.

Switches

150, 151, 152, and 153 connect and disconnect the output from the 14 day calender circuit 2 to the three input NOR gate 162. Switches similar to

switches

150, 151, 152, and 153 connect transistor 54 through 63 to the three input NOR gate 162 through isolation diodes similar to

diodes

159, 160, 161, and 162 as indicated by dashed lines in FIG. 2.

Single pole double throw switch 145 connects the AM-PM indicator circuit 5 to the three input NOR gate 162. As noted above, the base bias resistor 21 is connected to the flip-flop in the second divide by six l0.

Three input NOR gate 162 may be the triple 3- input NOR gate manufactured by Signetics mentioned heretofore under the number 8875 and described on pages 2-24 and 2-25 of Signetics Digital Designers Choice Logic Specifications Handbook Vol. 1 Logic Elements SS1 8400/8800 TTL/DTL, Copyrighted 1971.

As noted, the three inputs A, B, and C to the three input NOR gate 162 come respectively from the 12 hour membory circuit 3, the 14 day calender circuit 2, and the AM-PM indicator circuit 5 which is part of the clock circuit 1.

The output from the three input NOR" gate 162 passes through the diode 364 which prevents reverse current flow to the Schmitt trigger 154 which is the trigger input on the output sequence board as shown in FIGS. 3, 4, and 5.

Schmitt trigger 154 may be the Signetics monostable multivibrator numbered N74l2l as indicated in regard to Schmitt trigger 91.

Turning to FIG. 3, one embodiment of the five station output or sequence board is shown.

As noted, by closing

appropriate switches

145, 146, 147, 148, 149, 150, 151, 152, and 153 in the AM-PM indicator circuit 5, the hours memory circuit 3, and the calender circuit 2, data is fed to the three input gate 162. When all 3 inputs to the gate 162 are low, an output signal is sent to the output board where a pulse is generated to start the first section of the output board on its timed output to the valves in the field.

The output board includes Schmitt trigger 154 and X numberof

individual timers

175, 176, 177, 178, and 179 which are connected sequentially. When the first section has timed out, it shuts down and automatically starts the next section 176 on time. This action continues through all sections at which time the last section shuts down until the next pulse from the clock circuit 1 is received.

Provision has been made to skip

alternate sections

175, 177, and 179 or 176 and 178 and shutdown or retrigger the alternate sections at once or after a timed delay. The output can be started manually if need be. A single section can be manually selected and timed or can be timed automatically. All automatic timing is adjustable from /2 second upward as required for the appropriate program.

Turning to the five station output board shown in FIG. 3 the sequential timers or

stations

175, 176, 177, 178, and 179 may be linear integrated circuit monolithic timing circuits such as Signetics timer number NE555V described on

pages

177 and 178 of Signetics Linear Data Book Volume I, Copyrighted 1972. Other suitable devices than Signetics NE555V may be used.

The three input data collection gate 162 is shown providing a signal through diode 364 and Schmitt trigger 154 to timer 175. The 12 hour data, 14 hour data, and AM-PM data inputs to the data collection gate 162 are shown in the data collection schematic of FIG. 2.

Trimmer resistors 180, 181, 182, 183, and 184 adjust the on time to compensate for tolerances in the resis tance and capacitance of their related RC circuits. Trimmer resistor is part of the RC circuit including timing resistor 185 and capacitor which is grounded at ground 195. Trimmer resistor 181 is part of the RC circuit including timing resistor 186 and capacitor 191 which is grounded at ground 196. Trimmer resistor 182 is part of the RC circuit including timing resistor [87 and capacitor 192 which. is grounded at ground 1'97. Trimmer'resistor 183 is part of the RCcircuit including timing resistor 188 and capacitor 193 whichis grounded. at ground 198. Trimmer resistor 184 is par-t of the RC circuit including timing resistor 189 and capacitor 194 which is grounded at ground 199.

Resistors 200,201, 202, and 203 are input bias resistors.

Capacitors

204, 205, 206, 207, and 208 are voltage level reference capacitors which are grounded respectively at

grounds

214, 216, 218, 220, and 222.

Capacitors

209, 210, 211, and 212 are isolation or coupling capacitors.

Timers

175, 176, 177, 178, and 179 are grounded respectively at

grounds

213, 215, 217, 219, and 221.

Resistor 223 and capacitor 224 comprise a RC circuit to determine the length of pulse the Schmitt trigger 154 generates. Schmitt trigger 154 is grounded at ground 225.

NPN transistors

226, 227, 228, 229, and 230 are relay switching transistors.

Resistors

231, 232, 233, 234, and 235 are transistor base bias resistors for

transistors

226, 227, 228, 229, and 230 respectively.

The base electrodes of transistors 23], 232, 233, 234, and 235 are connected respectively to switch

points

236, 237, 238, 239, and 240 of a single station select switch including swtich element or wiper 286.

Relay coils 241, 242, 243, 244, and 245 are connected to the emitter electrodes of transistors 231, 232,

233, 234, 235 respectively.

Relay contacts

246, 247, 248, 249, and 250 are activated by their associated relay coils 241, 242, 243, 244, and 245. Relay coil 241 is grounded at ground 251; relay coil 242 is grounded at ground 252; relay coil 243 is grounded at ground 253; relay coil 244 is grounded at ground 254, and relay coil 245 is grounded at ground 255.

Pilot light

266, 267, 268, 269, and 270 are connected in parallel with

relay coils

241, 242, 243, 244, and 245 respectively.

Switch 256 isan on-off-on single pole double throw switch to apply power directly to the base of

Transistors

226', 227, 228, 229 or 230 through switch 272 and resistor 257 or from Timer 258 for single station manual operation. The timer 258 may be a Signetics timer number NESSSV as described above.

Resistor 257 is a base bias resistor.

Timer 258 is grounded at ground 259.

Push button switch 260 is a timed on switch, i.e. pushing the button starts the timer 258 on time delay. Switch 260 is grounded at ground 261.

Capacitor 263 is a timing capacitor and variable resistor 264 is a timing resistor which together form an RC circuit.

Capacitor 262 is a voltage level reference capacitor.

Capacitors

262 and 263 are grounded at ground 265.

Timer 258 is a single station timer for picking out one station and having it timed.

Capacitor 271 is a coupling capacitor.

Turning to FIG. 6 the external power supply circuit is shown.

Valves

280, 281, 282, 283, and 284 are connected to relay

contacts

246, 247, 248, 249, and 250 as shown.

Valves

280, 281, 282, 283, and 284 are valves in the field.

External power supply 285 matches the valves in the

field

280, 281, 282, 283, and 284 and is connected to relay

coils

241, 242, 243, 244, and 245.

The positive voltage is indicated by Vcc as heretofore.

Turning to FIG. 4 one alternate five station out put board that may be used with the subject invention is shown.

The alternate output board of FIG. 4 includes a Schmitt trigger input 154 and X number of individual timers connected sequentially.

When a signal is transmitted from the three input gate 162 through the diode 364 and Schmitt trigger 154, the Schmitt trigger 154 is activated and generates an output pulse which starts the timer 300 for the first station. The first station 300 will time out according to the length of time set up in the program and shutdown simultaneously starting the second timer or section 301 on time according to the program. This action will continue through the stations or

timers

302, 303, and 304 at whichtime the system will shut down until the next signal is transmitted from the clock and calendar board of FIGS. 1, 1A, and 1B through the Schmitt trigger 154.

An alternate program can be set up whereby alternate stations or timers can be skipped if desired.

When switch 305 which is a double pole double throw center off switch is in the lower or odd number position for example,

NPN transistors

307 and 309 are turned on, bypassing timing

resistors

312 and 314. A pulse generated by the Schmitt trigger 154 will start the first station 300 on the programmed time. At the end of the time period, the first station 300 will shut down and trigger the second station 301. Since timing resistor 312 is bypassed by transistor 307, the second station 301 will shutdown and trigger the third station or timer 302 typically about /2 second after start.

The third staion 302 will time out according to the time setting for that station, triggering the fourth station or timer 303 on shutdown. NPN transistor 309 is turned on, bypassing timing resistor 314, causingthe fourth station 303 to skip to the fifth station or timer 304 which will time out according to the programmed time.

On shutdown of the fifth station 304, the pulse generated will cause flip-flop 316 to change state, reversing the on/off condition of NPN transistors 306,307, 308, 309, and 310. The next pulse generated by the Schmitt trigger 154 will start the first station 300 and transistor 306 is turned on, bypassing timing resistor 311 and causing the first station 300 to skip to the second station 301 which will time out according to the programmed time.

Shutdown of the second station 301 will trigger the third station'or timer 302 which will skip due to the on condition or transistor 308 and will start the fourth timer or station 303.

Upon shutdown of the fourth station 303, the fifth station 304 is triggered on and will shutdown typically about one-half second later, generating a pulse which will cause flip-flop 316 to change back to the original state, and the system will be shutdown until the next signal from the clock and calender board of FIGS. 1, 1A, and 18 through the Schmitt trigger 154.

When switch 305 is in the upper or even number position, the opposite or alternate transistors are turned on, i.e.

transistors

306, 308, and 310 instead of

transistors

307 and 309.

Timing

resistors

313 and 315 serve the same function as timing

resistors

311, 312, and 314 mentioned above.

If desired, retriggering of the output board of FIG. 4 can be accomplished by closing switch 317 which activates the retrigger timer 365. The transfer pulse generated by the shutdown of the first station 300 will start the retrigger time delay which will range ordinarily from /2 second to 50 minutes. Retriggering times longer than 60 minutes will be accomplished by the clock and calendar circuits of FIGS. 1, 1A and 1B which can trigger each hour.

Timers

300, 301, 302, 303, and 304 may be Signetics timers number NE555V described above in regards to

timers

175, 176, 177, 178, and 179.

Referring further to FIG. 4

resistors

318, 319, 320, 321, and 322 and transistor base bias resistors for

transistors

306, 307, 308, 309, and 310.

Resistors

323, 324, 325, 326, and 327 are trimmer resistors to adjust the on time to compensate for tolerance in the resistors and capacitors in their respective RC circuits. Resistor 323 forms an RC circuit with resistor 31 1 and capacitor 328. Resistor 324 forms an RC circuit with resistor 312 and capacitor 329. Resistor 325 forms an RC circuit with resistor 313 and capacitor 330. Resistor 326 forms an RC circuit with resistor 314 and capacitor 331. Resistor 327 forms a .RC circuit with resistor 315 and capacitor 332.

Capacitors

328, 329, 330, 331, and 332 are grounded at

grounds

333, 334, 335, 336, and 337 respectively.

Capacitors

338, 339, 340, and 342 are voltage level reference capacitors which are grounded respectively at

grounds

343, 344, 345, 346, and 347.

Resistors

348, 349, 350, and 351 are input bias resistors.

Capacitors

352, 353, 354, 355, 356, and 357 are iso' lation or coupling capacitors.

Resistors

358, 359, 360, 361, and 362 are transistor base bias resistors for

transistors

226, 227, 228, 229, and 230.

Switch 363 is a manual start push button switch. The operation of the alternate output board circuit of FIG. 4 can be commenced by pushing the button on switch 363 independently of the signal from the clock and calendar board circuit of FIGS. 1, 1A, andlB, and thus the clock and calendar board circuit of FIGS. 1, 1A, and 1B can be bypassed.

Capacitor 366 is a timing capacitor which forms a RC circuit with timing resistor 368.

Capacitor 367 is a voltage level reference capacitor.

Capacitors

369 and 370 are coupling capacitors.

Block 371 indicates external modular timing boards to increase the capacity of the system beyond five timers or stations such as

stations

300, 301, 302, 303, and 304.

Resistor 372 is a base bias resistor.

Switch 373 which is a manual on switch is activated to apply power to the base of

Transistors

226, 227, 228, 229, or 230 for picking out one station through

contacts

236, 237, 238, 239, or 240 of switch 272.

Diode 374 prevents reverse current flow.

Push button switch 375 when activated by pushing starts the timer 377 on time delay. Timer 377 may be Signetics timer number NESSSV described above. The switch 375 is connected to ground 376.

Timing capacitor 380 and timing resistor 378 together form an RC circuit.

Capacitor 379 is a voltage level reference capacitor.

Capacitors 379 and 380 are connected to ground 381.

F lip-flop 316 may be Signetics Dual J -K Master-Slave Flip-Flop Digital 54/74TTL Series number 7473 described on pages 77 and 78 of Signetics Digital Manual 54/7400 TTL. Flip-Flop 316 is grounded at ground 382.

The trigger pluse starts the first section of the modular board 371.

Vcc indicates the positive voltage.

Switch element or wiper 286 along with

switch contacts

236, 237, 238, 239, and 240 and circuit elements 372 through 381 constitutes an independent overriding circuit to operate one station and doesnt interfere with the program.

Turning to FIG. 5 a second five station alternate outboard circuit is shown. In so far as operation differs from FIGS. 3 and 4 it will be discussed.

Retrigger pulses are derived from and injected into first station or timer 300 in FIG. 4. However in the alternate output board of FIG. 5 pulses can be derived from any station and injected into any station, according to the program.

The start of the output board of. FIG. 5 at any station can be accomplished by selecting the starting station through switch 430 and pushing push button switch 436. The output will then be as programmed from that station, retriggering if desired.

Switch 430 is used to inject retrigger pulses into any station selected either at once or after a timed delay. First station or timer 425 is selected by switch position 431. Second station or timer 426 is selected by switch position 432. Third station or timer 427 is selected by switch position 433. Fourth station or timer 428 is selected by switch position 434. Fifth station or timer 429 is selected by switch position 435.

Timers

425, 426, 427, 428, and 429 may be Signetics timers number NESSSV described above in regards to

timers

175, 176, 177, 178, and 179 et seq.

Push button switch 436 which is used to start the output manually at the selected station is grounded at ground 437.

Capacitors

438, 439, 440, 441, 442, 443, and 271 are coupling capacitors.

The Schmitt trigger 154 provides the impulse or start pulse for normal operation.

Switch 444 is used to pick up the trigger pulse from any station by selecting desired

switch contact

445, 446, 447, 448, 449, or 450 by adjustment of switch wiper blade or element 451.

The retrigger timer 452 may be Signetics timer number NESSSV described above.

The other elements shown in FIG. 5 are described in the description of FIGS. 3 and 4.

In summary the solid state controller of the subject invention may be constructed with output voltage to match valves in the field or other devices as required. The number of stations is unlimited with auxiliary plug in modular output'sections. The auxiliary output sections-neednot be located at the main controller site.

A l.4,day calendar may beutilized with a 12 hour electronic clock and the AM-PM circuit may be bypassed to repeat cycle for both AM and PM hours.

Variable-timing typically from /2 second to one hour per station is provided at each station and one or more auxiliary output sections can be triggered simultaneously or allowed to run sequentially.

Alternate cycles are utilized to skip alternate stations. The repeat cycle feature will pick up skipped stations with predetermined time delay, typically up to one hour. The repeat feature need not be used as the next clock pulse will pick up skipped stations. The circuit will automatically return to the initial state.

The repeat cycle feature can be triggered from any station, and the repeat start pulse can be applied to any station, ahead of, or behind the triggering station.

Any one or all stations can be turned on manually simultaneously or by separate push button controlled timer, independent of the programmed setup.

Since the internal power supply includes a transformer, no high voltage is present past the power supply, and the power source is isolated from the internal circuitry. The indicator lamps and digital readouts indicate the circuits in operation.

The output, master valve, and pump circuits may be protected by circuit breakers.

It is thought that this invention and many of its attendant advantages will be understood from the foregoing description, and it will be apparent that various changes may be made in the form, construction and arrangement of the parts without departing from the spirit and scope of the invention or sacrificing all of its material advantages, the forms hereinbefore described being merely preferred embodiments thereof.

What I claim as my invention and desire to secure by letters patent of The United States ls:

l. A solid state electronic control for timing and cycling including integrated circuits for timing and frequency division, discrete transistors, solid state diodes, light emitting diode numeric indicators, resistors and capacitors, and an internal power supply including an alternating current source wherein the integrated circuits drive the discrete transistors to control the light emitting diode numeric indicators for time indication, the solid state diode rectify alternating current from the alternating current source to direct current, the resistors limit current, and the capacitors effect filtering and transient suppression to automatically, sequentially time and cycle the actuation of electrically operated remote control valves for distribution of water for the purpose of irrigation, spraying, and humidification of plant materials, said solid state electronic control comprising six sections including a digital readout clock circuit, a calendar circuit, an hours memory circuit, a station output board, the internal power supply, and an external power output circuit in which the digital readout clock circuit is connected to the calendar circuit, the hours memory circuit, and the internal power supply, the station output board is connected to the calendar circuit, the hours memory circuit, and the digital readout clock circuit, and the external power output circuit is connected to the station output board and adapted for connection to remote control valves so that the digital readout clock circuit indicates the hours of a time period and then repeats, the calendar circuit changes indication each 24 hours, indicating days of the week, the hours memory circuit tracks the digital readout, the internal power supply is common to all sections of the control except power output to remote control valves, startup of the station output board is dependent on coincidence of signals obtained from the digital readout clock circuit, the calendar circuit, and the hours memory circuit, and the external power output circuit supplies power to operate remote control valves. 7

2. A solid state electronic control as described in claim 1 in which the digital readout clockcircuit includes an AM-PM indicator circuit.

3. A solid state electronic control as described in claim 2 in which the internal power supply is common to all sections of the control except the power output to the electrically operated remote control valves and the external power output circuit actuates the electrically operated remote control valves.

4. A solid state electronic control as described in claim 3 in which the internal power supply includes a source of power, a transformer, and a voltage regulator in which the transformer isolates the source of power from the other sections of the control and the transformer secondary winding is connected to the voltage regulator.

5. A solid state control as described in claim 4 in which the internal power supply includes two diodes and a filter capacitor in which one diode is connected in each arm of the transformer secondary winding, the filter capacitor is connected between the diodes and the voltage regulator, and the transformer secondary winding and filter capacitor are grounded.

6. A solid state control as described in claim 4 in which the digital readout clock circuit includes wave shaping and frequency division means to obtain a pulse time base from the line frequency and digital readout means.

7. A solid state control as described in claim 6 in which the wave shaping means includes a triple line receiver connected to the secondary winding of the internal power supply transformer.

8. A solid state control as described in claim 7 in which the frequency division means includes first and second divide by six means, first and second divide by 10 means, first and second decade counter means, Schmitt trigger means, divide by six counter means, and multiple binary coded decimal decoder means in which the triple line receiver is' connected to the Schmitt trigger means, to the second decade counter means, to at least one of the binary coded decimal decoder means, to the first and the second divide by six means, and to the divide by six counter means, the

Schmitt trigger means is connected to the divide by six counter means and the second decade counter means, the first divide by six means is connected to the first divide by 10 means, the first divide by 10 means is connected to the second divide by 10 means, the second divide by 10 means is connected to the second divide by six means, the second decade counter is connected to the divide by six counter and to a binary coded decimal decoder means, and the divide by six counter is connected to the first decade counter means and to multiple binary coded decimal decoder means so that the line frequency is shaped into a square wave by the Schmitt trigger action of the triple line receiver and is fed through the first divide by six to the first divide by 13 v 10, to the second divide by 10, to the second divide by six for atotaldividc by 3600 to obtaina 1 pulse per minute output as a time base for the digital readout clock circuit which is fed to the first decade counter whose output is decoded by a binary codeddecimal decoder means,.a signal from the first decade counter being fed into-the divide by six counter means whose output is decodedby a binary coded decimal decoder means, a signal from the divide by six counter being fed into the second decade counter whose output is decoded by a binary coded decimal decoder means, the Schmitt trigger acting as a data pulse generator to reset the divide by six counter and second decade counter.

9. A solid state electronic control as described in claim 8 including four digital readout means, one for minutes indication, one for tens of minutes indication, one for hours indication, and one for tens of hours indication.

10. A solid state electronic control as described in claim 9 in which the digital readout means for tens of hours indication includes B and C segments including transistor and flip flop means to turn the B and C segments of the digital readout means for tens of hours indication on and off.

11. A solid state electronic control as described in claim 8 in which the AM-PM indicator circuit includes flip flop means in the frequency division means, two NPN transistors, and pilot light indicator means.

12. A solid state electronic control as described in claim 11 in which the hours memory circuit tracks the digital readout means and includes divide by 12 counter means and one of 16 decoder means in which the divide by 12 counter means receives a signal from the decade counter means of the digital readout clock circuit.

13. A solid state electronic control as described in claim 12 in which the calendar circuit changes day indication each 24 hours including divide by 16 counter means, one of 16 decoder means, multiple inverter means, multiple solid state switching means, and multiple pilot light indicator means in which the divide by 16 counter means is connected to the second divide by six means of the frequency division means, to the AM-PM indicator circuit flip flop means and to the base electrode of one of the two AM-PM indicator circuit transistors whose collector electrode is connected to one of the two pilot light indicator means whose function is to indicate PM, the one of 16 decoder means is connected to the divide by sixteen counter means and to the multiple inverter means, the multiple inverter means is connected to the multiple solid state switching means, and the multiple solid state switching means is connected to the multiple pilot light indicator means so that the divide by 16 counter means counts the passage of 24 hours, and the binary coded output of the divide by 16 counter means is decoded by the one of 16 decoder means and is inverted by the inverter means and fed to the solid state switching means which activate associated pilot light indicator means to indicate days of the week.

14. A solid state electronic control as described in claim 13 in which the calendar circuit divide by 16 counter is connected to the calendar circuit one of 16 decoder, the one of 16 decoder is connected between the divide by 16 counter and the inverter means, and the multiple solid state switching means are connected between the inverter means and the pilot light indicator means.

15. A solid state electronic control as described in claim 14 including switch means connected to the digital readout clock circuit frequency division means said switch means being adjustable to pick up faster pulses allowing for rapid time setting.

16. A solid state electronic control as described in claim 15 including data collection means for collecting data from the hours memory circuit, the calendar circuit, and the AM-PM indicator circuit and transmitting that data to the station output board.

17. A solid state electronic control as described in claim 16 in which the data collection means is a threeinput NOR gate.

18. A solid state electronic control as described in claim 17 including switching means between the threeinput NOR gate and each of its data inputs.

19. A solid state electronic control as described in claim 17 in which the station output board includes trigger input means connected to the output of the three-input NOR gate and a number of solid state sequential timers connected to the trigger input means.

20. A solid state electronic control as described in claim 19 in which the trigger input means is a Schmitt trigger.

21. A solid state electronic control as described in claim 20 including rectifier means connected between the output from the three-input NOR gateand the Schmitt trigger to prevent reverse flow of current.

22. A solid state electronic control as described in claim 21 including RC circuit means connected to each sequential timer and trimmer resistor means connected between each sequential timer and its related RC circuit to adjust the on time to compensate for tolerances in the resistance and capacitance of their related RC circuits.

23. A solid state electronic control as described in claim 22 including multiple relay switching transistor means and multiple relay means in which the relay switching transistor means are connected between the sequential timers and the coils of the relay means.

24. A solid state electronic control as described in claim 23 in which the external power output circuit includes an external power supply and in which the external power supply is connected to one set of the relay contacts.

25. A solid state electronic control as described in claim 24 including external field valves connected be-- tween the external power supply and other relay contacts.

26. A solid state electronic control as described in claim 25 including switching means and solid state timer means in which the switching means is adjustable to connect the solid state timer with a selected one of the solid state sequential timers to have said sequential timer timed.

27. A solid state electronic control as described in claim 26 including a second switching means to apply power to the timer and a third switching means to start the timer on time delay.

28. A solid state electronic control as described in claim 27 including means for bypassing the output of the three-input NOR gate and triggering the Schmitt trigger directly.

29. A solid state electronic control as described in claim 28 including retriggering means connected to the first sequential timer and switch means connected between the retriggering means and the positive voltage whereby closing the switch means activates the retrigger means and the transfer pulse generated by the shutdown of the first sequential timer will start the retriggering time delay.

30. A solid state electronic control as described in claim 29 in which the retriggering means is a solid state electronic timer.

31. A solid state electronic control as described in claim 29 including means for skipping selected alternate sequential timers.

32. A solid state electronic control as described in claim 31 in which the means for skipping selected alternate sequential timers includes a solid state flip flop, a number of NPN transistors, one connected to each sequential timer, and switching means connected between the flip flop and NPN transistors.

33. A solid state electronic control as described in claim 32 including external modular timing boards to increase the capacity of the station output board by adding additional sequential timer stations, said external modular timing boards being connected to the means for skipping selected alternate sequential timers.

34. A solid state electronic control as described in claim 25 including first switching means, second switching means, and retrigger means in which the first switching means is adjustable to connect the retrigger means with a selected one of the solid state sequential timers to pick up trigger pulses from the selected sequential timer, the retrigger means is connected between the first and the second switching means and the second switching means injects retrigger pulses into the selected sequential timer.

35. A solid state electronic control as described in claim 34 including manual switch means connected to the second switching means to start the output manually at any sequential timer station.

36. A solid state electronic control as described in claim 34 in which the retrigger means is a solid state

Claims

1. A solid state electronic control for timing and cycling including integrated circuits for timing and frequency division, discrete transistors, solid state diodes, light emitting diode numeric indicators, resistors and capacitors, and an internal power supply including an alternating current source wherein the integrated circuits drive the discrete transistors to control the light emitting diode numeric indicators for time indication, the solid state diode rectify alternating current from the alternating current source to direct current, the resistors limit current, and the capacitors effect filtering and transient suppression to automatically, sequentially time and cycle the actuation of electrically operated remote control valves for distribution of water for the purpose of irrigation, spraying, and humidification of plant materials, said solid state electronic control comprising six sections including a digital readout clock circuit, a calendar circuit, an hours memory circuit, a station output board, the internal power supply, and an external power output circuit in which the digital readout clock circuit is connected to the calendar circuit, the hours memory circuit, and the internal power supply, the station output board is connected to the calendar circuit, the hours memory circuit, and the digital readout clock circuit, and the external power output circuit is connected to the station output board and adapted for connection to remote control valves so that the digital readout clock circuit indicates the hours of a time period and then repeats, the calendar circuit changes indication each 24 hours, indicating days of the week, the hours memory circuit tracks the digital readout, the internal power supply is common to all sections of the control except power output to remote control valves, startup of the station output board is dependent on coincidence of signals obtained from the digital readout clock circuit, the calendar circuit, and the hours memory circuit, and the external power output circuit supplies power to operate remote control valves.

8. A solid state control as described in claim 7 in which the frequency division means includes first and second divide by six means, first and second divide by 10 means, first and second decade counter means, Schmitt trigger means, divide by six counter means, and multiple binary coded decimal decoder means in which the triple line receiver is connected to the Schmitt trigger means, to the second decade counter means, to at least one of the binary coded decimal decoder means, to the first and the second divide by six means, and to the divide by six counter means, the Schmitt trigger means is connected to the divide by six counter means and the second decade counter means, the first divide by six means is connected to the first divide by 10 means, the first divide by 10 means is connected to the second divide by 10 means, the second divide by 10 means is connected to the second divide by six means, the second decade counter is connected to the divide by six counter and to a binary coded decimal decoder means, and the divide by six counter is connected to the first decade counter means and to multiple binary coded decimal decoder means so that the line frequency is shaped into a square wave by the Schmitt trigger action of the triple line receiver and is fed through the first divide by six to the first divide by 10, to the second divide by 10, to the second divide by six for a total divide by 3600 to obtain a 1 pulse per minute output as a time base for the digital readout clock circuit which is fed to the first decade counter whose output is decoded by a binary coded decimal decoder means, a signal from the first decade counter being fed into the divide by six counter means whose output is decoded by a binary coded decimal decoder means, a signal from the divide by six counter being fed into the second decade counter whose output is decoded by a binary coded decimal decoder means, the Schmitt trigger acting as a data pulse generator to reset the divide by six counter and second decade counter.

17. A solid state electronic control as described in claim 16 in which the data collection means is a three-input NOR gate.

18. A solid state electronic control as described in claim 17 including switching means between the three-input NOR gate and each of its data inputs.

21. A solid state electronic control as described in claim 20 including rectifier means connected between the output from the three-input NOR gate and the Schmitt trigger to prevent reverse flow of current.

25. A solid state electronic control as described in claim 24 including external field valves connected between the external power supply and other relay contacts.

29. A solid state electronic control as described in claim 28 including retriggering means connected to the first sequential timer and switch means connected between the retriggering means and the positive voltage whereby closing the switch means activates the retrigger means and the transfer pulse generated by the shutdown of the first sequential timer will start the retrigger time delay.