US3832639A - Tone generator for generating selected frequencies - Google Patents

Abstract

A tone generator comprising a pulse oscillator, a divider having an adjustable integer dividend which is connected thereto and which comprises a sub-divider having an adjustable fractional dividend, and a sub-divider which is connected thereto and which has a fixed integer dividend, the latter sub-divider also constituting a binary-to-digitial converter.

Description

United States Patent Janssen 1 1 Aug. 27, 1974 1 TONE GENERATOR FOR GENERATING [56] References Cited SELECTED EREQUENCIES UNITED STATES PATENTS [75] Inventor: Daniel Johannes Gerardus .lanssen, 3,215,860 11/1965 Neumann 328/27 X Emmasingel, Eindhoven, 3,500,213 3/1970 Ameau 328/27 X Netherlands 3,551,826 12/1970 Sepe 328/25 X 3,657,657 4/1972 Jefferson 328/14 1 Asslgneel PhlllpscorporalwmNew 3,752.97; 8/1973 Thorn et a1. 32s/14x York, NY. 22 Filed; May 29, 1973 Primary ExaminerJ0hn Zazworsky Attorney, Agent, or Firm-Frank R. Trifari [21] Appl. No.: 364,969

1 1 ABSTRACT [30] Foreign Apphcatmn Pnomy Data A tone generator comprising a pulse oscillator, a di- June 10, 1972 Netherlands 727933 Vider having an adjustable integer dividend is connected thereto and which comprises a sub-divider U-S. i. having an adjustable fractional dividend and a ub- 328/27- 307/261 divider which is connected thereto and which has a [5 Cl. fixed integer dividend the latter ub divider also con- Fleld of Search l8, a binary to digitial onverter 6 Claims, 13 Drawing Figures PULSE GENERATOR 'NTEGER V R [f' m i 1 i 7 10 SELECTION SWITCHING UNIT INTEGER DIVIDER PATENTED 2 7 I974 3 832 6 39 SHEET 1 7 PULSE GENERATOR I INTEGER DIVIDER f 1 5 In M l a SUB-DIVIDERS 1 K) I E i I 1 1 l ln l 12 H9 [INTEGER DIVIDER L ECTIQN SWITCHING Fig.1

1 UNIT CURRENT /5SOURCE 18 A 25 K H U I6 wEf INJECTION LOGIC T ELEMENT ELEMENT Fl .2 a F '9 b K OR-GATE AND-GATE H 3-5 7 19 I A B A. B Q" B7D B 21 PAIENIEDmczmn SHEET b 0? 7 Fig.5a

TONE GENERATOR FOR GENERATING SELECTED FREQUENCIES The invention relates to a tone generator for generating a number of selected frequencies, comprising a pulse oscillator, a frequency divider which is connected to the pulse oscillator and which has an adjustable integer dividend for deriving the selected frequencies from the pulse oscillator frequency, and a binary-to-digital converter for forming approximately sinusoidal digital signals.

Tone generators of this kind are advantageously used in practice for generating frequencies of crystal stability.

Netherlands Patent Application 7.013,78O describes a tone generator which is used in a data modulator and which comprises a pulse source having a pulse repetition frequency which is equal to a multiple of the selected frequencies to be generated, and from which a pulse sequence is derived, by means of a frequency distribution network, which is applied to a binary-todigital converter.

Due to the frequency dividing capacity of the binaryto-digital converter, the pulse repetition frequency of the pulse source is chosen to be higher by a multiplication factor which is equal to the frequency dividing capacity than the smallest common denominator of the frequencies to be generated. If a very closely approximated sine wave is to be generated, a digital converter having a high frequency dividing capacity is required.

This has the drawback that an oscillator having a very high oscillation frequency is to be used. This implies, on the one hand, that the number of logic elements to be used is large and, on the other hand, that the logic elements used must be suitable for operation at these very high frequencies; logic elements are then required which have a comparatively large dissipation.

The invention has for its object to realize a tone generator of the kind set forth by means of a comparatively small number of logic elements, in which the operating speed of the logic elements can be comparatively low, and in which the selected frequencies are generated with a closely approximated sine wave by means of few additional logic elements.

The device according to the invention is characterized in that the divider having an integer dividend comprises an adjustable sub-divider having a fractional dividend, a sub-divider having a fixed integer dividend being connected thereto, the latter sub-divider also constituting the binary-to-digital converter.

According to a further characteristic, the integer divider comprises a programming network, to which the sub-divider having the adjustable fractional dividend is connected for generating reset signals at given counting positions of this sub-divider, to which a frequency selection switching unit is connected for the selection of some of the generated reset signals for each selected frequency, and to which the sub-divider having the fixed integer dividend is connected for causing the appearance of the selected reset signals according to a fixed sequence and for a number of times per cycle of the integer divider which corresponds to the dividend of the sub-divider having the fixed integer dividend, the programming network being connected to the subdivider having the adjustable fractional dividend forresetting the sub-divider having the adjustable fractional dividend to a starting position by any relevant reset signal appearing.

The invention and its advantages will be described with reference to the embodiments shown in the Figures.

FIG. 1 shows an embodiment of a tone generator according to the invention.

FIGS. 2a to 2d show some injection-logic elements by means of which the tone generator shown in FIG. 1 is realized.

FIG. 3 shows the diagram of a divider which is used in the tone generator shown in FIG. 1..

FIGS. 4, a to k, show signals which can occur in the divider shown in FIG. 3.

FIGS. 5a and 51) show parts of a binary-to-digital converter which is used in the tone generator shown in FIG. 1.

FIGS. 6, a to i, and FIG. 7 show signals which can occur in the parts of a binary-to-digital converter shown in FIGS. 5a and 5b.

FIG. 8 shows the diagram of another divider which is used in the tone generator shown in FIG. 1.

FIG. 9 shows an embodiment of a tone pushbutton selection switching device used in the tone generator shown in FIG. 1.

The embodiment shown in FIG. 1 illustrates an application of the tone generator according to the invention in a push-button telephone set, the setbeing adapted to be used in a special tonefrequency signalling system. In this signalling system use is made of two different frequency bands which are situated within the frequency band of a speech channel, four selected frequencies which are used as signalling frequencies being situated in each frequency" band. For the transfer of information, a signalling frequency of one frequency band is combined with a signalling frequency of the other frequency band.

In Document No. 10l,C.C.I.T.T. Com. XI recommends 697 Hz, 770 Hz, 852 Hz and 941 Hz successively for the signalling frequencies situated in the lowest of the two frequency bands, and 1,204 Hz, 1,336 Hz, 1,477 Hz and 1633 Hz successively for the signalling frequencies situated in the highest of the two frequency bands.

These frequencies may not deviate more than 1.5 percent, and the level of the sum of all higher harmonics must be at least 20 dB lower than the level of the fundamental wave.

So as to satisfy the i 1.5 percent frequency tolerance requirement, while taking into account ageing phenomena and the effects of variations of temperature, relative humidity and voltage, the signalling frequencies are preferably derived from crystal-stabilized oscillators. It is economical to use one crystal-controlled oscillator and to derive all signalling frequencies from the oscillation frequencies supplied by this oscillator so that it is at the same time ensured that the signalling frequencies cannot be shifted with respect to each other. Digital techniques are used to comply with the frequency tolerance requirement and to enable realization of the tone generator in integrated form.

Use is made of a pulse oscillator l which is known per se, and the signalling frequencies are derived from the oscillator frequency supplied by the pulse oscillator by means of integer dividers.

So as to keep the number of dividers small, dividers are used which have an adjustable integer dividend,

two integer dividers 2 and 3 having an adjustable dividend being used because of the fact that two signal frequencies must be simultaneously generated in the special signalling system. These dividers comprise control terminals 8 and 9 whereto a frequency selection switch- 5 ing unit 12 is connected by means of which the dividends can be adjusted. The oscillator frequency must then be equal to the smallest common denominator of the signalling frequencies to be generated, the said smallest common denominator being very large for the signalling frequencies recommended by the C.C.I.T.T. Commission. The pulse frequencies supplied by the dividers 2 and 3 generally contain a high percentage of higher harminics. So as to satisfy the requirement that the level of the sum of all harmonics must be at least 1 dB lower than the level of the generated signalling frequency, filters must be used; in view of the fact that it must readily possible to integrate these filters, they must be realized in digital form. These digital filters have a frequency dividing capacity which is proportional to the quality of these filters. When use is made of such filters, the oscillator frequency would normally have to be chosen to be higher by a factor which is equal to the frequency dividing capacity than the smallest common denominator of the signalling frequencies. This implies that many logic elements must be used; these elements must have an operating speed which is adapted to this high oscillator frequency. Elements of this kind are uneconomical and have a high dissipation. In that case it is not possible to use a tone generator of this kind in a push-button telephone set.

The invention enables the use of a lower oscillator frequency in that each of the integer dividers 2 and 3 comprises a sub-divider 4, 6 having an adjustable fractional dividend, and a sub-divider 5, 7 having a fixed integer dividend which is connected thereto, the latter sub-divider also constituting the binary-to-digital converter.

A further reduction of the oscillator frequency is obtained by utilizing the permissible 1.5 percent frequency tolerance by selecting signalling frequencies which have a comparatively small smallest common denominator, but which deviate only slightly (less than 1.3/00) from the frequencies recommended by C.C.I.T.T. Com. XI in Document No. 101.

Consequently, the frequency of the oscillator amounts to 221.8 kHz in this embodiment. The dividends of the integer dividers 2 and 3 which are required so as to derive the desired signalling frequencies therefrom are stated, together with these frequencies, in columns 2 and 1, respectively, of table A.

tone generator must be suitable for operation at a supply of 2.7 volts and a supply current of 10 mA. To this end, all logic circuits are realized by means of injection logic. This kind of logic is described in the U.S. Pat. application Ser. No. 253,348, filed on May 15, 1972 and assigned to the same assignee.

The basic element of all injection logic circuits is shown in FIG. 2a, and consists of a multicollector transistor 14 without resistors, for which it holds good approximately that the base is connected to a unit current source 15. When input terminal 16 is conductively connected to earth, referred to hereinafter as that a low signal is applied to input terminal 16, the current of current source 15 will be applied to earth, and the transistor 14 will not be conductive. Any currents applied to the output terminals 17 and 18 which are connected to the collectors cannot be carried off, which will be referred to hereinafter as that the output terminals 17 and 18 supply a high signal. If a high signal is applied to input terminal 16, the current of current source 15 will flow to earth via the base-emitter junction of transistor 14, and currents applied to the output terminals 17 and 18 will flow to earth via the collector-emitter junction. The output terminals 17 and 18 then supply a low signal. This basic element, operating as an inverter, is denoted by the symbol shown in FIG. 2b. The direct interconnection of a plurality of inputs is prohibited in injection logic.

According to this logic system, an AND-gate is realized by interconnecting two conductors as shown in FIG. 2c. The output terminal supplies a high signal (cannot take off current) only if A and B are high (i.e., no current is derived from A or B). This means that the signal on the output terminal satisfies the logic relation A. B of the logic signals A and B applied to the inputs.

FIG. 2d shows an OR-gate which is constructed according to this logic system. The logic signals A and B applied to the input terminals are inverted to form A and B by the inverters l9 and 20. Subsequently, these signals are combined to form A'B by the AND-gate which is realized by the interconnected outputs of the inverters l9 and 20, and this signal is converted to the output signal A B by way of inverter 21.

By means of the inverter, the AND-gate and the OR- gate shown in the FIGS. 2b to 2d, all more complex logic elements such as bistable elements, can be realized in known manner. Each of the bistable elements used in the circuit comprises a set input S, a trigger The logic used will be considered before a detailed description is given of the tone generator.

The use of the tone generator in a push-button telephone set in the present embodiment implies that the input T, a condition input D, a signal output Q, and an inverted signal output 6. A high signal which is applied to the set input S sets the element to the set state which is characterized in that the signal output 0 supplies a high signal. A high or a low signal applied to the condition input D can set or reset. respectively, the bistable element at the instant at which a signal applied to the trigger input T changes'from high to low. A two-divider is obtained in known manner by connecting the inverted signal output 6 of a bistable element to the condition input D.

FIG. 3 is a detailed representation of the divider 2 having an adjustable integer dividend according to the invention. The sub-divider 4 comprises four cascadeconnected bistable elements 22 to 25 which are constructed as two dividers. The trigger input T of element 22 is connected to the output terminal 13 of the pulse oscillator 1 which is not shown in this Figure, and the trigger inputs T of the elements 23 to 25 are connected to the signal outputs Q of the preceding elements 22 to 24. The pulse sequence which is applied to terminal 13 by the oscillator is shown in FIG. 4a. The signals which are successively derived therefrom by two-division by the elements 22 to 25 are shown in the FIG. 4, b to e.

The sub-divider 5, having a fixed dividend, is connected to the sub-divider 4 having an adjustable dividend. The fixed dividend of this sub-divider 5 is chosen to be equal to twelve in this embodiment. So as to realize this dividend, sub-divider 5 comprises four bistable elements 26, 27, 28 and 29 which are interconnected as described hereinafter, the elements 26 and 29 thereof being connected as two-dividers. Because the inputs of elements which are constructed according to injection logic may not be directly interconnected, the inverters 30 to 34 are used so as to obtain a plurality of identical outputs to which inputs can be individually connected, these inverters being connected to the signal output Q or the inverted signal output 6 of the bistable elements 25, 26 and 27 supplying the inverted signals with respect to the desired signals. For example, the inverter 30 is connected to the inverted signal output 6 of element 25 so as to supply the trigger inputs T of the elements 26, 27 and 28, connected to the outputs of the inverter 30, with a signal which is identical to the signal supplied by the signal output Q of element 25.

Furthermore, so as to obtain a signal for the condition input D of element 27 such that the elements 26, 27 and 28 constitute a six-divider, the inverters 35, 36 and 37 are provided. Inverter 35 is connected to the inverters 32 and 33 so as to supply on its output the logic OR-function of the logic signal values applied to the inverters 32 and 33. Similarly, inverter 36 is connected to the inverters 31 and 34 so as to supply on its output the logic OR-function of the logic signal values applied to the inverters 31 and 34. The inverter 37 is connected to the output of the inverter 35 and to the inverted signal output 6 of bistable element 28 so as to supply on its output the logic NAND-function of the logic signals applied to its input, the outputs of the inverters 36 and 37 being connected to the condition input D of element 27 so as to apply thereto the logic AND-function of the signals supplied by the inverters 36 and 37. Furthermore, the signal output of element 27 is connected, via inverter 34, to the condition input D of element 28.

The operation of the sub-divider will be described with reference to the FIG. 4, f to j, assuming that the bistable elements 26 to 29 are in the set state; the output signal of sub-divider 4 which is shown in FIG. 4e is shown again at a reduced time scale in FIG. 4f.

Because the elements 26 to 28 are in the set state, the inverter 35 causes inverter 36 and the inverter 37 to supply a high signal, with the result that a high signal is also applied to the condition input D of element 27.

As a result of the negative edge appearing at the instant t (FIG. 4f), element 26 is reset, element 27 remains set and element 28 is reset as is shown in the FIG. 4, g, h and i. The resetting of the element 26 causes the output signal of inverter 35 to change from high to low, with the result that for the time being the resetting of element 28 does not influence the high output signal supplied by the inverter 37. The negative edge which appears at the instant t sets element 26 to the set state, with the result that the output signal of inverter 35 becomes high again. In conjunction with the high signal supplied by the inverted signal output 6 of element 28, this high output signal causes the output signal of inverter 37 to change from high to low with the result that a low signal is applied to the condition input D of element 27. Consequently, the negative edge occurring at the instant t will reset both the element 26 and the element 27. Because elements 26 and 27 are simultaneously reset, the value of the signals supplied by the inverters 35 and 36 is not changed. Only the signal applied to the condition input D of element 28 changes from low to high. The negative edge appearing at the instant t will consequently, set elements 26 and 28. Because element 26 is set, the output signal of inverter 36 changes from high to low, with the result that the signal applied to the condition input D of element 27 remains low, even though the output signal of inverter 37 has become high due to the setting of element 28. The negative edge appearing at the instant t resets element 26, with the result that the signal supplied by inverter 36 becomes high and a high signal is applied to condition input D of element 27. The negative edge which appears at the instant t sets element 26 and element 27. All three elements 26, 27 and 28 are then set, so that as from the instant t the cycle of the successive states of the said elements is repeated. The pulse sequence supplied by element 28, consequently, has a pulse repetition frequency which is six times smaller than the pulse repetition frequency of the pulse sequence supplied by the sub-divider 4. Because the trigger input T of the bistable element 29 which is connected as a twodivider is connected to the signal output Q of element 28, the pulse repetition frequency of the pulse sequence supplied by element 29 is twelve times smaller than the pulse repetition frequency of the pulse sequences supplied by the sub-divider 4 as shown in FIG. 4j.

So as to obtain a digital signal which is approximately sinusoidal, the sub-divider 5 comprises a weighting network 38 to which the inverters 32 and 34 and the inverted signal output Q of element 29 are connected. The weighting network 38 comprises a gate circuit as shown in FIG. 5a in order to form signals which determine the phases of the approximated sine wave, and a current source circuit as shown in FIG. 5b which is connected thereto and by means of which the amplitudes of the approximated sine wave are determined.

The signals supplied by the inverters 32, 34 and the inverted signal output Q of element 29 are applied to the input terminals 40, 41 and 42 of the gate circuit shown in FIG. a, the said signals being shown in FIGS. 6a, 6b and 66.

Connected to these input terminals are the inverters 43, 44 and 45 so as to have a plurality of identical signal outputs available for each input terminal in order to prevent inputs ofinverters which are connected thereto from being directly connected to each other. The signals applied to the input terminals 40, 41 and 42 are recovered from the signals supplied by the inverters 43, 44 and 45 by means of the inverters 46, 47 and 48.

Because the outputs of the inverters 43, 4'7 and 48 are interconnected, the logic AND-function of the inverted signal of the input signal shown in FIG. 6a and the input signals shown in the FIGS. 6a and 6c are ob' tained on inverter 50, the said signal being shown in FIG. 6d. After successive inversion by the inverters 50 and 53, this signal is applied to output terminal 53-1 in unmodified form.

Because the outputs of the inverters 47 and 48 are interconnected, the logic AND-function of the input signals shown in the FIGS. 6!; and 6c is applied to inverter 51, the said signal being shown in FIG. 6e and being applied in unmodified form to the output terminals 54-3 after successive inversion by the inverters 51 and 54.

The inverter 49 constitutes an OR-gate, in conjunction with the inverters 44 and 46 which are connected to the input of this inverter, with the result that this inverter forms on both its outputs the logic ORfunction of the input signal shown in FIG. 6a and a signal which is obtained by inversion of the input signal shown in FIG. 6b. A first output of inverter 49 is connected, together with an output of inverter 48, to the input of inverter 52 in order to supply this inverter with the logic AND-function of the signal supplied by inverter 49 and the input signal shown in FIG. 60. This signal, shown in FIG. 6f, is applied in unmodified form to the output terminal 55-4 after successive inversion by the inverters 52 and 55.

A second input of inverter 49 is connected, together with an output of inverter 45, to inverter 56 in order to supply the output terminals 56-4 with the inverted logic AND-function of the signal supplied by inverter 49 and a signal which is derived from the input signal shown in FIG. 6c by inversion. The signal applied to the output terminals 56-4 is shown in FIG. 6g.

The output of inverter 47 is connected, together with the output of inverter 45, to an inverter 57 in order to supply the output terminals 57-3 with the inverted logic AND-function of the input signal 6b and a signal which is obtained from the input signal shown in FIG. 60 by inversion. This signal is shown in FIG. 6h. Furthermore, the outputs of the inverters 43, 45 and 47 are connected to an inverter 58 in order to cause the inverter 58 to supply the inverted logic AND-function of signals which are derived from the input signals shown in FIGS. 6a and 60 by inversion and the input signal shown in FIG. 6b, the said signal being shown in FIG. 6i.

As appears from the FIGS. 6d and 6i, the inverters 53 to 58 supply pulses which are symmetrically arranged with respect to each other, which have the same pulse repetition frequencies, and which have a different pulse duration, with respect to each other, the duration of the pulses being odd multiples of approximately one twelfth of the pulse period of the pulse sequence supplied by subdivider 5. Consequently, in each period of the pulse sequence supplied by the sub-divider 5 twelve phases are characterized which are approximately regularly distributed over 360C.

In order to obtain an approximately sinusoidal amplitude which changes at these phase instants, the inverters 53, 54, 55, 56, 57 and 58 are provided with one output terminal 53-1, three output terminals 54-3, four output terminals 55-4, four output terminals 56-4, three output terminals 57-3, and one output terminal 58-1, respectively, which are connected to the current source circuit shown in FIG. 5b. This circuit comprises 16 parallel-connected current sources, divided in six groups of one, three, four, four, three and one current source, respectively, which are denoted by 59; 68-62; 63-66; 67-71; 72-75 and 76, respectively. Only one current source is shown of each group. Each current source comprises a first transistor 59-1, 60-1, 76-1, and a second transistor 59-2, 60-2, 76-2, which is connected in series therewith. All current sources are connected between the terminals 78 and 79 of a supply voltage source not shown, in series with a resistor 77. Also provided between these terminals is a voltage divider which is composed of the resistors 80 and 81, the centre tapping of the said voltage divider being connected to the bases of all transistors 59-1, 59-2, 76-1, 76-2. The voltage of the centre tapping of the voltage divider 80, 81 is selected such that all transistors 59-1 to 76-1 carry an identical, constant current. The output terminals 53-1 to 58-1 of the gate circuit are connected, via input terminals 59-3 to 76-3, to connections which are provided between the collectors of the transistors 59-1, 60-1, 76-1 and the emitters of the transistors 59-2, 60-2, 76-2. If the signal applied to an input terminal, for example, 59-3, is high, the current flows from the main current path of transistor 59-1 to earth via the main current path of the transistor 59-2 and resistor 77. This current then causes a voltage drop across resistor 77. If the signal applied to the input terminal 59-3 is low, the current flows from the main current path of transistor 59-1, via input terminal 59-1 and the inverter 59 which is connected thereto, to earth with the result that this current cannot contribute to the voltage across resistor 77. Because the inverters 53 to 58 control one, three, four, four, three, and one current source, respectively, by means of the signals shown in the FIGS. 6d to 6i, the sinusoidal voltage signal shown in FIG. 7 is formed across resistor 77, the said sinusoidal voltage signal comprising only the (n-12) +first harmonics (n l, 2, 3,

By connecting a capacitor 83 parallel to resistor 77, a low-pass filter is obtained which suppresses the har monies, with the result that the C.C.I.T.T. requirement as regards the level of these harmonics is satisfied. The sinusoidal voltage signal is available between the terminals 82 and 79 which constitute the output terminal 10 shown in the FIGS. 1 and 3.

For generating the four signal frequencies which are situated in the high frequency band, it must be possible to adjust the dividends of divider 2 which are shown at these frequencies in Table A, column 2, under the control of the signals which are applied to the control input 8 by the frequency selection switching unit 12. Because the dividend of sub-divider 5 is equal to twelve, the dividend of sub-divider 4 must be adjusted to the first four values shown in column 3 of Table A for the signalling frequencies which are situated in the high frequency band. To this end. sub-divider 4 is provided with the programming network 84 which is shown in FIG. 3. This programming network comprises the conductors 85 to 91 which are connected, via the OR-gate 100 which is formed by the inverters 92/98 which are connected to these conductors and the inverter 99 which is connected thereto, to an inverter 101, together with the input terminal 13. This inverter 101 is connected, via an inverter 102, to the set inputs S of the bistable elements 22, 23 and 24. By means of this programming network 84 a reset signal can be derived at the instants at which the sub-divider 4 is in one of the counting positions 11 to 16, the said reset signal being used to reset the sub-divider 4 to a starting position which is defined by the set state of the elements 22 to 25.

To this end, the inverted signal outputs of the elements 22, 23 and 24 are connected to inputs of inverters 103, 104 and 105, the outputs of the inverter 103 being connected to the conductors 86, 87 and 90, the outputs of the inverter 104 being connected to the conductors 85, 86, 87 and 91, the outputs of inverter 105 being connected to the conductors 88, 89, 90 and 91, and the signal output Q of element 25 being connected to the output of OR-gate 100, each connection point constituting an AND-gate. When the signal on input 13 is high, the reset signal is obtained if one of the conductors 85 to 91 supplies a high signal via OR-gate 100 and the signal output Q of element 25 also supplies a high signal. If it is assumed that sub-divider 4 is in its starting position, the signal output Q of element 25 becomes high (FIG. 4e) after nine pulses have been applied to the input terminal; the way in which the sub-divider 4 is connected to the programming network then causes, as shown in FIG. 4, b and c, all signals applied by subdivider 4 to the conductor 85 to be high for the eleventh pulse applied to sub-divider 4, the signals applied to conductors 86 and 87 to be high for the twelfth pulse applied to sub-divider 4, the signals applied to the conductors 88 and 89 to be high for the thirteenth pulse applied to sub-divider 4, the signals applied to conductor 90 to be high for the fourteenth pulse applied to sub-divider 4, and the signals applied to conductor 91 to be high for the fifteenth pulse applied to the sub-divider 4, all elements 22 to 25 of sub-divider 4 being set by the sixteenth pulse because the subdivider 4 has the completed one counting cycle.

So as to obtain the fractional dividend of the subdivider 4 which is required for a given signal frequency, control signals are generated under the control of the frequency selection switching unit 12 in a manner which will yet be described, the said control signals serving to select two of the eight reset signals which are generated at given counting position of the sub-divider 4, these selected reset signals being arranged, under the control of signals supplied by sub-divider 5, such that they alternately occur in a given time sequence.

To this end, the programming network 84 is provided with input terminals 8-1 and 8-2 to which inverters 106 and 107 are connected. The frequency selection switching unit 12 is connected to these input terminals 8-1 and 8-2 which constitute the control terminal 8 shown in FIG. 1. This device 12 supplies two logic signals to the input terminals 106 and 107 when a button is depressed in a manner which will yet be described. By means of these two logic signals, four signal states can be distinguished, each signal state being used to select two of the eight-reset signals. This is achieved in that the conductors and 86 connected to outputs of inverter 106 as well as to outputs of inverter 107, the conductors 87 and 88 being connected to outputs of the inverter 106, and the conductors 89 and 90 being connected to the outputs of the inverter 107.

If the signals applied to the input terminals 8-1 and 8-2 are both low. the inverters 106 and 107 supply high signals. The conductor which receives only high signals from sub-divider 4 at a given counting position then applies a high signal via OR-gate which, in conjunction with the high state of the signal output Q of element 25, is capable of resetting sub-divider 4. This occurs first for the conductor 85 at the counting position eleven. By keeping the signal which appears in counting position 11 on conductor 85 low in the manner yet to be described, the signal on conductor 86 becomes high at counting position twelve of the sub-divider 4, the said signal then being capable of resetting the subdivider 4. When a low signal is applied to both input terminals 8-1 and 8-2, the reset signals which are generated at the counting positions 11 and 12 are thus selected.

If the signal which is applied to input terminal 8-1 is low and the signal which is applied to input terminal 82 is high, a high signal is applied only to the conductors 87 and 88. The low signal which is applied to the conductors 85 and 86 keeps the signals appearing on these conductors low due to the connection points of the outputs of the inverters 103, 104 and 105 which act as AND-gates. As a result, the reset signals which are derived at the counting positions twelve and thirteen are selected.

If the signal applied to input terminal 8-1 is high and the signal applied to input terminal 8-2 is low, the inverter 107 applies a high signal only to the conductors 89 and 90. The reset signals which are derived at the counting positions thirteen and fourteen are then selected.

If the signals applied to both input terminals 8-1 and 8-2 are high, a low signal is applied to the conductors 85 to 90. Only the reset signal derived from the counting position 15 and the signal which causes the resetting to the starting position in the counting position 16 of sub-divider 4 are then selected.

The sequence in which the two reset signals which are selected under the control of the frequency selection switching unit 12 succeed each other is determined by subdivider 5. The outputs of the inverters 31 and 33 of this sub-divider are connected to an inverter 108, the outputs of which are connected to the conductors 85 and 91, an output of inverter 31 being connected to conductor 87, and a further output being connected to conductor 89, an output for inverter 34 also being connected to the latter conductor. The operation will be described in detail with reference to the signals shown in the FIG. 4, a to k.

As already described, each pulse supplied by subdivider 4 (FIG. 4f) changes the state of the elements 26 and 27 in accordance with the signals shown in FIG. 4, g and h. These figures show that the signals applied to inverter 108 are both high during the time intervals situated between the instants t t t t t t and r r,,. The signal supplied by inverter 108 is low during these intervals. If the signals applied to both input terminals 8-1 and 8.2 are low for the time intervals during which inverter 108 applies a high signal to conductor 85, this conductor 85 will carry a high signal at the counting position 11, and during the time intervals in which invcrtcr 108 supplies a low signal to conductor 85, the conductor 86 will carry a high signal at the counting position 12. The counting positions of the sub-divider 4 change at the instants at which the trailing edges of the pulses applied to input terminal 13 appear, so that a signal supplied via OR-gate 100 by the conductor 85 or 86, changes from high to low at the instants of appearance of the eleventh or the twelfth counting position. respectively. The signal applied from input terminal 13 to inverter 101, however, is then low. The signal applied to input terminal 13 becomes high after one half pulse repetition time of the pulse sequence applied to input terminal 13, with the result that via the inverters 101 and 102 a high signal (shown in FIG. 4k) is applied to the set inputs S of the elements 22, 23 and 24. This signal resets the sub-divider 4 to its starting positron.

As appears from FIG. 4, g, h, k and a, assuming that sub-divider 4 is in the starting position, this sub-divider is reset only after 11 pulses have been received on input terminal 13, subsequently after 12 and after that, as appears from FIG. 4, g and h, successively after 11, ll, 11,12,11, 12,11, 11, 11 and 12 pulses have been received on input terminal 13 in each cycle of the subdivider 5. Because the cycle of subdivider 5 is equal to the cycle of divider 2, the dividend of this divider is 136, the said dividend deriving, according to Table A, the signal frequency 1,633 Hz from a generator frequency of 221.8 kHz. The mean dividend of subdivider over a cycle of divider 2 is 34/3, as is indicated in Table A, column 3. Because the sub-divider 4 is not always reset at the same counting position, the instants I, to I as shown in FIG. 4 are not regularly distributed. These instants are also shown in FIG. 6 and FIG. 7. The sequence of appearance of the instants, however, is chosen such that the approximated sine wave is mirrorsymmetrical, with the result that no even harmonics are generated. The increase of the number and the intensity of the odd higher harmonics caused by the irregular time distribution is so small that the requirements imposed by C.C.I.T.T. are readily satisfied.

The signal which is applied by inverter 31 to the conductor 87 corresponds to the signal shown in FIG. 4g. This means that, if a low signal is applied to input terminal 8-1 and a high signal is applied to input terminal 8-2, the conductors 88 and 87 alternately carry a high signal at the counting positions 13 and 12, respectively, of the sub-divider 4, thus resetting the sub-divider. The mean dividend of sub-divider 4 is then equal to 25/2, with the result that the dividend of divider 2 is equal to 150. According to Table A, a signal having a frequency of 1,477 Hz is then generated.

The signals applied by the inverters 31 and 34 to conductor 89 correspond to the signal shown in FIG. 4g, and to a signal which is obtained by inversion of the signal shown in FIG. 4/1. This means that a high signal is applied to conductor 88 only during the intervals situated between the instants t t and I t,,. If a high signal is applied to input terminal 8-1 and a low signal is applied to input terminal 8-2, the sub-divider 4 is reset, because the conductors 90 and 91 carry high signals in the described manner, successively after 14, 14, 14, l3, 14, 14; 14, 14, 14, 13, 14 and 14 pulses have been received on input terminal 13 in each cycle of divider 2. The mean dividend of subdivider 4 is then equal to 83/6, so that the dividend of divider 2 is equal to 166.

According to Table A, a signal having a frequency of 1.336 H7. is then generated.

The signal which is applied by inverter 108 to conductor is also applied to conductor 91. If high signals are applied to both input terminals 8-1 and 8-2, the conductor will carry a high signal, if inverter 108 supplies a high signal, after 15 pulses have been applied to input terminal 13, the said signal resetting the subdivider 4 and, if inverter 108 supplies a low signal, the sub-divider 4 will have returned to its starting position after 16 pulses have been received on input terminal 13. It is thus achieved that in each cycle of the divider 2 the sub-divider 4 is successively reset after 15, 16, 15, 15, 15, 16; 15, 16, 15, 15, 15 and 16 pulses have been applied to input terminal 13. The mean dividend of sub-divider 4 is then equal to 46/3, and the dividend of divider 2 is then equal to 184. In accordance with Table A, a signal having a frequency of 1,204 Hz is then supplied.

The sequence of the counting positions at which the sub-divider 4 is successively reset is also chosen for the generated signalling frequencies of 1,477 Hz, 1,336 Hz and 1,204 Hz such that the approximated sine wave is mirror-symmetrical so that no even harmonics are generated.

The frequencies which are situated in the low frequency band of the special signalling system are derived from the oscillator frequency by means of the integer divider 3 which is composed, in accordance with the invention, of a sub-divider 6 having a fractional, adjustable dividend, and a sub-divider 7 having a fixed, integer dividend. This divider 3 is shown in detail in FIG. 8. As appears from Table A, the dividends which have to be realized by means of this divider are larger than those of divider 2. Consequently, the divider 3 shown in FIG. 8 differs from the divider 2 shown in FIG. 3, on the one hand, in that between the bistable elements 24 and 25 a bistable element 109 is provided whose set input S is connected to an output of inverter 102, the trigger input T being connected to signal output Q of element 24, the signal output 0 being connected to the trigger input T of element 25, and the inverted signal output 6 being connected to an additionally provided inverter 110 and, on the other hand, in that the sub-dividers 6 and 7 are connected to the conductors 85 to 91 in a manner other than the subdividers 4 and 5, conductor not being connected to an output of inverter 107. Disregarding the fact that the input terminals are denoted by 9-1 and 9-2 in accordance with the control terminal 9 shown in FIG. 1 and the fact that the output terminal as shown in FIG. 1 is denoted by 1 1, the other parts are denoted by the same references as used for the divider 2.

Besides the fact that the signal output Q of element 25 supplies a high signal in the counting positions 16 to 32, inverter 104 supplies a high signal to conductor 85 only if sub-divider 6 is in counting position 19, high signals being applied by the inverters 103 and 104 to conductor 86 when the sub-divider 6 is in counting position 20, high signals being applied to conductor 87 by inverters 103 and when sub-divider 6 is in counting position 21, a high signal being applied to conductor 88 by the inverter 105 when subdivider 6 is in counting position 22, high signals being applied to conductor 89 by the inverters 103, 104 and 105 when sub-divider 6 is in counting position 24, high signals being applied to conductor 90 by the inverters 103 and when subscribed, i.e., if the signals applied to both input terminals are low, the conductors 85 and 86 are selected, the conductors 87 and 88 being selected if the signal applied to input terminal 9-1 is low and the signal applied to input terminal 9-2 is high, the conductor 89 being selected if the signal applied to input terminal 9-1 is high and the signal applied to input terminal 9-2 is low, and the conductors 90 and 91 being selected if the signals applied to the two input terminals 9-1 and 9-2 are high. The sequence in which the conductors 85, 86; 87, 88 and 90, 91, which are selected per pair, supply reset signals is determined in that the conductors 85 and 87 are connected to the outputs of the inverters 31 and 33, and in that conductor 90 is connected to an output of inverter 31. As appears from the FIG. 4, g and h, the inverters 31 and 33 supply high signals only during the time intervals which are situated between the instants r r 2 i t t t and t so that when conductor pair 85, 86 is selected, the subdivider 6 is reset after 20, 19, 20,20, 20, 19; 20, 19, 20, 20, 20 and 19 pulses have been successively received on output terminal 13 in each cycle of divider 3. The mean dividend of subdivider 6 then amounts to 59/3, and the dividend of divider 3 is 236. In accordance with Table A, a frequency of 941 Hz is then supplied to output 11.

Similarly, when the conductor pair 87 and 88 is selected, the sub-divider 6 is reset after 22, 21, 22, 22, 22, 21; 22, 21, 22, 22, 22 and 21 pulses have been successively received on input terminal 13 in each cycle of divider 3. The mean dividend of sub-divider 6 is then 68/3, and the dividend of divider 3 is equal to 260, the said dividend corresponding according to Table A to a signal frequency of 852 HZ which is applied to output terminal 11.

When conductor 89 is selected sub-divider 6 is reset after every 24 pulses received on input terminal 13. The dividend of divider 3 is then 288, which corresponds according to Table A to a signal frequency of 770 Hz for the signal applied to input terminal 11.

The inverter 31 applies the signal shown in FIG. 4g to conductor 90, with the result that upon selection of the conductor pair 90, 91 the sub-divider 6 is reset after 27 and 26 pulses have alternately been received on input terminal 13. The dividend of sub-divider 6 is then equal to 53/2, and the dividend of divider 3 then amounts to 318, which according to Table A makes the signalling frequency of the signal appearing on output terminal 11 equal to 691 Hz.

The stated sequence of the counting positions at which the sub-divider 6 is successively reset in again chosen such that the approximated sine wave is mirrorsymmetrical.

The frequency selection switching unit 12 which supplies the required logic signals to the input terminals 8-1, 8-2 and 9-1, 9-2 is shown in FIG. 9. This device comprises a counter 138 which is composed of four cascade-connected bistable elements 111, 112, 113 and 114. The output terminal 13 of the pulse oscillator 1 applies, via the inverter 137, pulses to the trigger inputs T of the bistable elements 111 to 114. As a result, the counter 138 continuously passes through all successivc counting positions. Also provided is a push-button switch 127 which is composed of two pairs of four conductors 127-1 to 127-4 and 127-5 to 127-8 which cross each other at right angles. Above each crosspoint (16 in total) of the conductor a push-button (not shown) is provided, the said push-button pressing, when depressed, the conductors, which normally cross each other at the crosspoint against each other, with the result that they are conductively connected to each other. The inverted signal outputs 6 of the elements 111 and 112 are coupled, via an OR-gate which is formed by the inverters 115, 117 and 123, to the conductor 127-5, which the result that only this conductor receives a low signal when the elements 111 and 112 are in the set state. The signal output Q of element 111 and the inverted signal output 6 of element 112 are coupled, via the OR-gate formed by the inverters 116, 117 and 124, to conductor 127-6 with the result that this conductor receives a low signal only when element 111 is in the reset state and element 112 is in the set state. i

The inverted signal output 6 of element 111 and the signal output Q of element 112 are coupled, via the OR-gate formed by the inverters 115, 118 and 125, to conductor 127-7 so that only this conductor receives a low signal when the element 11 1 is in the set state and element 112 is in the reset state. Furthermore, the signal outputs Q of the elements 111 and 112 are coupled, via an ORgate which is formed by the inverters 116, 1 18 and 126, to conductor 127-8 so that only this conductor receives a low signal when the elements 111 and 112 are both in the reset state. During the counting of counter 138, low signals are successively applied to the conductors 127-5 to 127-8, the said low signals corresponding to the four possible set/reset state combinations of the elements 111 and 112.

The conductors 127-1 to 127-4 are connected to inverters 128 to 131. Because these conductors are normally not connected to earth, high signals are applied to the inverters 128 to 131, with the result that the latter supply low signals. When a button is depressed, one of the conductors 127-5 to 127-8 is connected to one of the conductors 127-1 to 127-4. The inverter (128 to 131) which is connected to this one conductor (127-1 to 127-4) supplies a high signal at the instant at which the conductor which is connected to the said one conductor supplies a low signal.

The output of inverter 131 is connected to an inverter 132, together with outputs of the inverters 119 and 1 21 which are connected to the inverted signal outputs Q of the elements 113 and 114. The inverter 132 supplies a low signal only if inverter 131 supplies a high signal and the elements 113 and 114 are both in the set state. The output of inverter 130 is connected to the input of an inverter 133, together with the output of inverter 121 and the output of an inverter which is connected to the signal output Q of element 113. The inverter 133 supplies a low signal only if inverter supplies a high signal, the element 113 is in the reset state, and the element 114 is in the set state. The inverter 129 is connected to an inverter 134, together with the output of inverter 119 and an output of an inverter 122 which is connected to the signal output Q of element 114. This inverter 134 supplies a low signal only if inverter 129 supplies a high signal and the element 113 is in the set state and the element 114 is in the reset state. The inverter 128 is connected to an inverter 135, together with outputs of the inverters 120 and 122, the said inverter 135 supplying a low signal only if inverter 128 supplies a high signal and the elements 113 and 114 are both in the reset state. During the counting, the elements 113 and 114 apply high signals to the inputs of the inverters 132 to 135, the said signals corresponding to the four possible set/reset state combinations of these elements. The inverters 132 to 135 are connected, via an AND-gate by the junction 136, to the input of inverter 137. It is thus achieved that when a button is depressed, the AND- gate 136 supplies a low signal for only one counting position of counter 138 which is characteristic for the button. This low signal is applied to inverter 137, with the result that the pulses which are supplied via the oscillator output terminal 13 are blocked. The counter 138 remains in the selected counting position as long as the button is depressed. The output terminals 141-1 and 141-2, connected to the outputs of the inverters 120 and 122, supply the signals which are required for the input terminals 8-1 and 8-2 of divider 2. Similarly, the output terminals 142-1 and 142-2, connected tothe outputs of the inverters 116 and 118, supply the signals required for the input terminals 9-1 and 9-2. When the button is released, the signal supplied by AND-gate 136 becomes high again and the counter 138 continuously counts the pulses again supplied by the pulse oscillator 1. It will be obvious from the foregoing that, when a button is depressed, two signal frequencies of the special signalling system are generated, one signalling frequency being situated in each of the two frequency bands. The frequencies which are selected by depression of a push-button switch 127 are shown on the ends of the conductors in FIG. 9 which are interconnected by the button.

What is claimed is:

1. A tone generator for generating a number of selected frequencies, comprising a pulse oscillator, a frequency divider which is connected to the pulse oscillator and which has an adjustable integer dividend for deriving the selected frequencies from the pulse oscillator frequency, and a binary-to-digital converter for forming approximately sinusoidal digital signals, characterized in that the divider having an integer dividend comprises a sub-divider having an adjustable fractional dividend and a sub-divider having a fixed integer dividend which is connected thereto, the latter sub-divider also constituting the binary-to-digital converter.

2. A tone generator as claimed in claim 1, characterized in that the integer divider is provided with a programming network to which the sub-divider having the adjustable fractional dividend is connected in order to generate reset signals at given counting positions of this sub-divider, to which a frequency selection switching unit is connected for the selection of some of the genrated reset signals for each selected frequency, and to which the sub-divider having the fixed integer dividend is connected for causing the appearance of the selected reset signals according to a fixed sequence and for a number of times per cycle of the integer divider which corresponds to the dividend of the sub-divider having the fixed integer dividend, the programming network being connected to the sub-divider having the adjustable fractional dividend in order to reset the subdivider having the adjustable fractional dividend to its starting position by any relevant reset signal appearing.

3. A tone generator as claimed in claim 2, characterized in that the reset signals which are selected by the switching unit are derived from directly successive counting positions of the adjustable sub-divider, the sequence in which the selected reset signals appear being selected such that the approximated sine wave is mirror-symmetrical.

4. A tone generator as claimed in claim 1, characterized in that the binary-to-digital converter comprises a weighting device including a plurality of parallelconnected current sources which are connected in series with a resistor, and means for successively switching on under the control of signals derived from the counting positions of the fixed sub-divider, a varying number of said current sources in such a manner as to produce an approximated sine wave across the resistor.

5. A tone generator as claimed in claim 1, characterized in that two adjustable dividers having an integer dividend are connected to the pulse oscillator, the said dividers being provided with control terminals to which a frequency selection switching unit is connected.

6. A tone generator as claimed in claim 5, wherein the dividend of one of the adjustable integer dividers is adjustable under the control of the frequency selection switching unit to produce a set of values which are below the frequency value of the pulse oscillator, the dividend of the other adjustable integer divider being adjustable under the control of the frequency selection switching unit to produce a set of values which are above the value of the oscillator frequency.

$3 33 I UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent Mi. 3 832 ,639 Dated ugust 27, 1974 Invented DANIEL J. G. JANSSEN It is certified that error appears in the above-identified patent and that: said Letters Patent are hereby corrected as shown below:

On the title page, Section [30] change 727933" Signed and sealed this 7th day ofjanuary I975.

(SEAL) Attest;

McCOY N. GIBSON JR. '0. MARSHALL DANN Attesting Officer Commissioner of Patents

Claims (6)

1. A tone generator for generating a number of selected frequencies, comprising a pulse oscillator, a frequency divider which is connected to the pulse oscillator and which has an adjustable integer dividend for deriving the selected frequencies from the pulse oscillator frequency, and a binary-to-digital converter for forming approximately sinusoidal digital signals, characterized in that the divider having an integer dividend comprises a sub-divider having an adjustable fractional dividend and a sub-divider having a fixed integer dividend which is connected thereto, the latter sub-divider also constituting the binary-to-digital converter.

2. A tone generator as claimed in claim 1, characterized in that the integer divider is provided with a programming network to which the sub-divider having the adjustable fractional dividend is connected in order to generate reset signals at given counting positions of this sub-divider, to which a frequency selection switching unit is connected for the selection of some of the genrated reset signals for each selected frequency, and to which the sub-divider having the fixed integer dividend is connected for causing the appearance of the selected reset signals according to a fixed sequence and for a number of times per cycle of the integer divider which corresponds to the dividend of the sub-divider having the fixed integer dividend, the programming network being connected to the sub-divider having the adjustable fractional dividend in order to reset the sub-divider having the adjustable fractional dividend to its starting position by any relevant reset signal appearing.

3. A tone generator as claimed in claim 2, characterized in that the reset signals which are selected by the switching unit are derived from directly successive counting positions of the adjustable sub-divider, the sequence in which the selected reset signals appear being selected such that the approximated sine wave is mirror-symmetrical.

4. A tone generator as claimed in claim 1, characterized in that the binary-to-digital converter comprises a weighting device including a plurality of parallel-connected current sources which are connected in series with a resistor, and means for successively switching on under the control of signals derived from the counting positions of the fixed sub-divider, a varying number of said current sources in such a manner as to produce an approximated sine wave across the resistor.

5. A tone generator as claimed in claim 1, characterized in that two adjustable dividers having an integer dividend are connected to the pulse oscillator, the said dividers being provided with control terminals to which a frequency selection switching unit is connected.

6. A tone generator as claimed in claim 5, wherein the dividend of one of the adjustable integer dividers is adjustable under the control of the frequency selection switching unit to produce a set of values which are below the frequency value of the pulse oscillator, the dividend of the other adjustable integer divider being adjustable under the control of the frequency selection switching unit to produce a set of values which are above the value of the oscillator frequency.

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