GB1399200A - Tone generator for generating selected frequencies - Google Patents

Abstract

1399200 Tone generators; keysets PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 7 June 1973 [10 June 1972] 27174/73 Headings G4D D7X D6Y D6C1 and D6C2 A tone generator comprises a pulse oscillator feeding an integer frequency divider formed from a non-integer adjustable subdivider and an integer subdivider the latter serving as part of a digital-toanalogue converter to produce a representation of the tone. The embodiment is for generating two tones, one selected from each of two sets of four tones, in a push-button telephone set and accordingly has two dividers connected to a common crystal controlled pulse oscillator, Fig. 1 (not shown). By selecting tone frequencies different from the design centre values but within the tolerance range, smaller dividers and a lower oscillator frequency may be used in the two divider circuits, Figs. 3 and 4 (not shown). The embodiment is formed from current injection logic units in which a multi-collector transistor has a current supply at its base so that a low input signal which diverts current from the base prevents the collector from diverting current from an output circuit thus producing a high output signal, the unit thus operating as an inverter. AND gates are formed by wired connections of the outputs of the inverters, OR gates are formed by feeding the inputs to respective inverters having their outputs connected to the inputs of a common inverter, Figs. 2a-2d (not shown). Bi-stable circuits are formed from these inverters and, as described, have a "set" input S, a trigger input T and a control input D which sets the circuit to correspond to the input at the high to low transition of the trigger input. One of the dividers is shown in Fig. 3, and comprises an adjustable non-integer sub-divider 4 and an integer sub-divider 5 associated with a digitalto-analogue converter 38. The sub-divider 5 comprises a divide-by-six section 26, 27, 28 and a divide-by-two section 29 to provide overall division by twelve. Inverters 30-34 are provided to provide multiple outputs. Feedback to cause the three stages 26, 27, 28 to divide by six is provided by an OR gate formed from inverters 35, 32 and 33, a further OR gate comprises inverters 36, 31 and 34, the outputs of these gates being connected to form a wired AND gate. The adjustable non-integer sub-divider 4 comprises stages 22-25 having the input connected to pulse source 13 which also feeds the "set" inputs under the control of a programming network connected to Q output of 25. The basic circuit is adjustable to divide by 11-16 but is controlled by the outputs from sub-divider 5 such that the dividend may change from counting cycle to counting cycle so as to provide a non-integer mean dividend. Thus, if the dividend in successive cycles is 12, 13, 12, 13 &c. a mean dividend is 12À5 and the overall dividend of the two sub-dividers is 150. The reset point of the counting cycle is controlled by a logic OR gate 100 the output of which is associated with the Q output of divider stage 25. The dividend is selected to have one of four possible values by binary signals applied at terminals 9-1 and 9-2. Selection of the dividend and thus of the control signals for 8-1 and 8-2 and the corresponding control terminals of the divider for the other set of four tones is effected as shown in Fig. 9, by a matrix switching arrangement 127. A counter 138 is continually circulated by input pulses 13 until a button at one of the matrix intersections is pressed whereupon the counter is stopped at the position which gives the right coding at the output terminals 141 and 142, these terminals being connected to the terminals 8-1, 8-2 of the respective dividers. The conversion of the output of the sub-divider 5 of Fig. 3, to sinewave form is effected by a unit 38 comprising a digital-to-digital converter, Fig. 5a and a digitial-to-analogue converter, Fig. 5b. In Fig. 5a, the three outputs from the divider are received at 40, 41 and 42 and provide, at outputs 53-58, pulses having the same centre point in time but of varying width, Fig. 6 (not shown). The outputs have one, three and four parallel connections as indicated and these are connected to corresponding transistors in the switching groups 59, 60, 63, 67, 72 and 76 of Fig. 5b, where although one transistor only is shown in each group, there are parallel transistors according to the number of inputs. Thus, for example, when the input signal at 60-3 is "up" a unit value current from each of three transistors 60-1 passes through corresponding transistors 60-2 to provide three units of current in the output load 77. A stepped sinewave, Fig. 7 (not shown), is built up and is passed through a filter to the output terminal.