US3832609A - Slip detection system - Google Patents

Abstract

A system for detecting excessive slip between the speed of an ac. motor and the speed of an a-c. generator supplying power to the motor at a variable frequency. Transducers associated with the motor and the generator produce pulses at frequencies proportional to the speeds of the motor and the generator, respectively. The periods Tm and Tg of these two series of pulses are measured by applying clock pulses to a counter during each period, so that the number of clock pulses counted during each period is proportional to the duration thereof. The pulses applied to the counter during the period Tm are counted up, and the pulses applied during the period Tg are counted down, so that the resulting output of the counter represents the difference (Tm - Tg). The count representing the period Tm is stored in a separate register, and the number representing Tm is then repetitively subtracted from the number representing (Tm - Tg) until the remainder is reduced to zero. The number of subtraction steps required to reduce the remainder to zero is counted to provide a number representing the quotient (Tm -Tg)/Tm. This quotient represents the per cent slip of the motor, and is compared with a preselected per cent slip limit determined by the setting of a series of thumbwheel switches. If the measured per cent slip value exceeds the preselected limit, an output signal is generated for actuating an alarm or other suitable utilization device so that the excessive slip condition can be corrected. Computation of the actual per cent slip is carried out by digital signal processing on a rapidly iterating basis so that the system provides a substantially instantaneous indication of any change in the percent slip. The system includes a number of auxiliary features for detecting various malfunctions and for resetting the system in response to both internal and external command signals.

Description

United States Patent 1191 Barrett et al SLIP DETECTION SYSTEM 751 Inventors: William J. 3 Barrett, Rockford, 111.;

Harold Green, Middleton, Wis.

[73] Assignee: Woodward Governor Company, Rockford, Ill.

22 Filed: Feb. 5, 1973 21 Appl. No.: 329,697

Primary Examiner-T. E. Lynch Attorney, Agent, or Firm-Wolfe, Hubbard, Leydig,

Voit & Osann, Ltd.

57 ABSTRACT- A system for detecting excessive slip between the speed of an a-c. motor and the speed of an a-c. generator supplying power to the motor at a variable fre- 1111 3,832,609 5] Aug. 27, 1974 quency. Transducers associated with the motor and the generator produce pulses at frequencies proportional to the speeds of the motor and the generator, respectively. The periods T, and T,, of these two series of pulses are measured by applying clock pulses to a counter during each period, so that the number of clock pulses counted during each period is proportional to the duration thereof. The pulses applied to the counter during the period T,, are counted up, and the pulses applied during the period T, are counted down, so that the resulting output of the counter represents the difference (T T,,). The count representing the period T,,, is stored in a separate register, and the number representing T is then repetitively subtracted from the number representing (T T until the remainder is reduced to zero. The number of subtraction steps required to reduce the remainder to zero is counted to provide a number representing the quotient (T ,,)/T,,,. This quotient represents the per cent slip of the motor, and is compared with a preselected per cent slip limit determined by the setting of a series of thumbwheel switches. If the measured per cent slip value exceeds the preselected limit, an output signal is generated for actuating an alarm or other suitable utilization device so that the excessive slip condition can be corrected. Computation of the actual per cent slip is carried out by digital signal processing on a rapidly iterating basis so that the system provides a substantially instantaneous indication of any change in the percent slip. The system includes a number of auxiliary features for detecting various malfunctions and for resetting the system in response to both internal and external command signals.

31 Claims, 11 Drawing Figures mama, 10271314 3.832.609

MET 2 U 8 [war war Pmmanmmm 3.832509 Q MET-7N 8 [N0 0/- I; Jar/v; I flm zwzi\ Y (42 H H II I] II I] H II. I] II II II [I II ,II [I H II [I [I II II H w WW 4624 j I f] arr zzrr J 477* 4 f 7 J77 H m7 Q w m 7? i s, m m 1% E zkaz/r i w H g" me E -jj fi iL m F1 F1 SLIP DETECTION SYSTEM DESCRIPTION OF THE INVENTION The present invention relates generally to systems for signaling the percentage difference between the frequencies of two recurring signals of variable frequency and, more particularly, to a system for signaling the percentage difference between the speed of an a-c. motor and the speed of an alternator or generator supplying power to the motor at a variable frequency.

In the case of an a-c. motor energized with alternating current from an alternator or generator of variable speed, slip" is defined as the difference between the alternator or generator speed (N,,) and the motor speed (N,,,) divided by the alternator or generator speed. This quotient multiplied by 100 gives the per cent slip, or

In certain applications of such systems, it is important to detect when the slip exceeds a certain limit. For example, in a hydroelectric system, excess generator capacity may be used during periods of low demand to drive one of the alternators as a synchronous motor to pump water back uphill for use in periods of high demand. Excessive slipping, especially likely during startup, in such a system produces abnormally high currents and correspondingly high temperatures. Consequently, if an excess slip condition occurs, the equipment must be allowed to cool for a relatively long period, e.g., to 12 hours, before starting up again. Thus, it is extremely desirable to detect when the slip exceeds a predetermined limit so that the generator can be controlled in speed and frequency to limit slip of the motor.

It is a primary object of the present invention to provide a slip detection system which continuously monitors the magnitude of slip in a motor-generator combination, and actuates a utilization device such as an alarm or automatic shut-down device whenever the slip exceeds a predetermined limit.

i It is another object of the invention to provide a slip detection system of the foregoing type which has ahigh degree of accuracy and reliability over a relatively wide speed range.

A further object of the invention is to provide a sli detection system of the type described above which permits convenient manual adjustment of the predetermined limit of slip detected by the system.

Still another object of the invention is to provide such a slip detection system which continually computes the per cent slip and provides a substantially instantaneous indication of whether the per cent slip is above or below a predetermined limit. A related object is to provide such a system which is characterized by high reliability and immunity from aging or drift by virtue of digital signal processing on a rapidly iterating basis.

A still further object of the invention is to provide such a slip detectionsystem which immediately senses a failure of the motor to start and provides an indication of such failure.

Yet another object of the invention is to providesuch a slip detection system which continuously monitors the primary inputs to the system and provides a substantially instantaneous indication of any malfunction that results in an interruption of such inputs.

Other objects and advantages of the invention will be I apparent from the following detailed description taken in connection with the accompanying drawings, in which:

FIG. 1 is a block diagram of a slip detection system embodying the invention;

FIG. 2, constituted by FIGS. 2a and 2b when joined, is a more detailed block and circuit diagram of the system illustrated in FIG. 1;

FIG. 3 is a moredetailed block diagram of the computing portion of the system illustrated in FIG. 2;

FIG. 4 is a timing diagram illustrating the signals in that portion of the system of FIG. 2 which measures the period T,,,;

FIG.'5 is a-timing diagram illustrating the signals in that portion of the system of FIG. 2 which controls the signals applied to the count up'input of the up-down counter;

FIG. 6 is a timing diagram illustrating the signals in that portion of the system of FIG. 2 which controls the signals applied to the count down input of the updown counter;

FIG. 7 is a timing diagram illustrating the signals in that portion of the system of FIG. 2 which controls the timing of the computing operations;

FIG. 8 is a timing diagram illustrating the signals in the output and reset portions of the system of. FIG. 2;

FIG. 9 is a timing diagram illustrating the signals-in the start-up check portion of the system of FIG. 2; and

FIG. 10 is a timing diagram illustrating the signals in the input signal monitoring portion of the system of FIG.'2.

While the invention will be described in connection with a preferred embodiment, it will be understood that it is not intended to limit the invention to that embodiment. On the contrary, it is intended to cover all alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.

Before considering the slip detection system illustrated in the drawings, it will be helpful to note the symbols and conventions which have been employed in those figures to diagrammatically represent different logic devices and signals. In this connection, the system shown in the drawings operates on a binary logic basis, i.e., each signal which is produced and responded to may have either a binary l or 0 value. These might be, for example, voltage levels of 12 volts and zero volts, respectively, which is positive logic since the most positive logic voltage levelis defined to be the logical I state, while the most negative logic voltage level is defined to be the logical 0 state. The system illustrated generally responds affirmatively to binary l signals, but when any given signal has a binary 0 value, that will normally produce no response (although a response to a binary 0 signal may be produced in certain instances.)

The term flip-flop is used herein to designate a device that exhibits two different stable states. The illustrative system utilizes two different types of flip-flops, namely the D-type and the JK-type. The D-type flipflop is characterized by a single data (D) input and a clock (C) input, and it may have either or both Q and Q outputs available. The data input is a synchronous input, i.e., it does not cause an immediate change in the output, but rather requires the presence or occurrence of a clock pulse at the clock input to generate a change of state in the outputs. When the flip-flop is clocked by the occurrence of a clock pulse at the clock input, the binary signal present at the data input is transferred to the Q output, and the Q output is always the complement of the Q output. For example, if the signal at the data input is a binary 1 when the flip-flop is clocked, the Q output is a binary 1 signal and the Q output is a binary signal after clocking. This type of flip-flop may also have asynchronous preset (P) and/or clear (Cr) inputs which are overriding controls that inhibit normal operation and cause the Q output to go to either a binary 1 or 0 level, depending on which input is present.

The JK-type flip-flop has two data inputs, J and K, and only a single clock input. When the signals present at the J and K inputs are. at different binary levels when the flip-flop is clocked, the signal present at the J input is transferred to the Q output, and the 0 output is always the complement of the Q output. When the binary 0 signals are present at both the J and K inputs when the flip-flop is clocked, the outputs remain unchanged at the. levels existing prior to clocking. When binary 1 signals are present at both the J and K inputs when the flip-flop is clocked, the outputs always change state in response to the clocking signal. As in the case of the D- type flip-flop, the JK-type flip-flop may also have asynchronous preset (P) and/or clear (Cr) inputs which override the other inputs and cause the Q output to go to either a binary I or 0 level, depending on which input is present.

NAND gates and NOR gates have been illustrated by the conventional symbols exemplified by the gates 55 and 38, respectively, in FIGS. 2a and 2b. As is well known, the output of the NAND gate is always a binary 1 signal except when all inputs are binary I signals, in which case the output becomes a binary 0 signal. Cons versely, the output of the NOR gate is always a binary 0 signal except when all inputs are binary 0 signals, in

which case the output becomes a binary 1 signal.

In FIGS. 2 through 9, certain logic signals appearing on various conductor lines are designated by alphabetical symbols. The letters chosen for these symbols sometimes represent words or phrases which loosely define the significance or function of the designated signal. Because the relationships between these symbols and the functions of the signals the designate may aid in understanding the description which follows, these relationships will be listed here:

Alphabetical Symbol Function AST Indicates that no computation has been completed within n phase A signals. Used to generate a reset and prevent inadvertent lock up of the unit.

Borrow from most significant bit of counter 52.

Used to clear both motor input flip- .flops 36 and 40 on GO or with RST. CLI First clock signal CL2 Second clock signal, out of phase with first clock signal.

Carry output from adder 75. Used to indicate completion of each adding step and when sum goes to zero Used to transfer output of adder 75 to up-down counter 52 during calculate phase of measurement cycle. Occurs before RTR.

Output of gate 80 used to increment counter 81 by one in response to each CRY indicating completion of an adding step.

BOR

CLEARX CRY CTR

DEC

Function 5 FFB FFR GCLK OVF PHA

PHAD

PHAX

PHB

PHBD PHBX PST.

RST

RTR

SMC

SOK

SRT STRT SUC SWD

SWU

Down count provides CLI input to count-down input of up-down counter 52 during measurement of interval between generator pulses Output of flip-flop I25 used to indicate loss of P,, or P,,.

A selective reset pulse applied only to flip-flops 92, III, H2 and I25. FFR is activated by power on or remote pushbutton but not by GCLK.

The clock generated by the lack-of CRY from adder 75. Applied to the output flip-flop 92, and is used to clock the output to the. state demanded by the output of the comparator. GCLK is gated with CL2.

ls used to start the measurement cycle if a motor pulse is received before the initial counter 74 reaches the preset number of generator pulses. Power on signal used to generate resets RST and RST.

Generates GCLK when CRY indicates zero sum in adder 75.

Indicates too many generator pulses have been received without a motor pulse. ls used to generate an error signal toactivate alarm.

Generates SRT on end of computation cycle or on hand-up,

Output of single shot I20 used to monitor P,,,.

Output of single shot I21 used to monitor Signal from the motor after being passed through the Schmitt trigger 34. Prestart signal used to generate a complete reset of the detector. Generates both RST and FFR.

A universal reset signal generated by power on, GCLK or a remote push button. All control flip flops except 92, l l I, 112 and I25 are cleared by RST.

Used to transfer information into register 73 during computation of phase of operation.

Is 0 when both PHAD and PHBD are I. Indicates detector is in computation phase. Enables the register and counter transfers RTR and CTR.

Sets flip-flop l I l to enable start of detector if Pm is received before LKOUT indicates error.

Trigger signal for reset.

A signal which, when 0, begins counting generator pulses. During start up, the rise of STRT indicates a measurement cycle is under way. STRT goes to 0 on reset and I if initial counter 74 contains too many generator pulses before receiving a motor pulse. The combination of CM and the phase B measurement cycle. Indicates a countdown operation.

The gated count-down signal. ls active after PHB and before PHBD. Is applied to the count-up input of counter 52 if underflow occurs during count-down. Enables application of SUC to countdown input of counter 52 in response to when neither PHBD nor SWU is I.

A signal indicating that a borrow has been generated by the counter.

TPE Detects coincidence of CS1 and CS2.

Goes to 1 when P or P, lost.

UCT Up count. Provides CLl input to count up input of counter 52 during measurement of time between motor pulses.

UP Up count provides CLl input to count-up input of counter 32 during measurement of interval between motor pulses.

UPF The clock applied to the counter 74 during start-up check.

UPS The up signal generated by CLl and PHA.

UPT The controlled count-up signal which is gated by the completion of the motor measurement operation.

The complement-of any signal designated by a given alphabetical symbol is conventionally designated by the same symbol with a superimposed bar added. For example, when the signal PHA is a binary l or 0, the signal PI-IA is a binary or 1 respectively.

Turning now to the block diagram of FIG. 1, the invention is illustrated in one exemplary application for detecting the percentage slip between a synchronous motor 5 energized by. a three-phase alternator 6 (referred to hereinafter as the generator). Although the invention has a wide variety of different applications, in the particular systemillustrated the alternator 6 is driven by a prime mover 7 powered by an energy medium source 8 via a governor 9. For example, the illustrative system may represent a hydroelectric system in which the prime mover 7 is a hydraulic turbine powered by water pressure as the energy medium, with the water control valve representing the governor 9. In such a system, a human operator normally adjusts a set point control 9a to adjust the governor 9 to control the speed of the prime mover 7 and thus the alternator 6. During start-up of the motor 5, it is particularly important that the operator adjust the set point control 9a to bring the alternator 6 up to speed at a rate which does not produce excessive slip between the motor 5 and the alternator 6, so as to avoid the difficulties described previously.

In accordance with one important aspect of the present invention, the slip detection system includes .means for generating signals representing the speeds of the motor and the generator, and computing means responsive to such signals for producing an output signal representing K( T,,, T,,)/T where K is a predetermined constant, T, is the period of rotation of the motor, and T is the period of rotation of the generator. Thus, in the system of FIG. 1, a pair of pulse generators 10 and 11 produce two'series of pulses P,, and P (see, e.g.,

To solve this equation, the output of the detector 14 enables a gate 16 to pass clock pulses from a source 17 to the count-up input of an up-down counter 18 during the period T,,,; at the end of the period T,,,, the output of detector 14 disables the gate 16 so that the number of clock pulses counted by the counter 18 represents the deviation of the period T,,,. This count is FIGS. 9 and 10) at frequencies proportional to the. I

speeds of the motor 5 and the generator 6, respectively. Thus, the frequency of pulses P,, represents the motor speed N,,,, while the frequency of pulses P represents the generator speed N,,. The two series of pulses P,, and P from the generators 10 and 11 are applied to a pair of detectors l4 and 15 which produce output signals representing the periods between successive pulses in each of the two series P and P respectively. Thus, the outputs of the detectors l4 and 15 represent the periods T, and T which are inversely proportional to the corresponding speeds N,,, and N Consequently, the percent slip equation described previously can be expressed as follows:

stored in a T register 19. When the gate 16 is disabled,

it also conditions a gate 20 to be enabled by the next T signal from the detector 15. As a result, clock pulses from the source 17 are passed through the gate 20 and applied to the count-down input of the counter 18 during the period T,,, at the end of which the gate 20 is disabled.

Since the clock pulses transmitted to the counter 18 are counted up during the period T and down during the period T,,, the net count accumulated in the counter 18 at the end of both counting operations is the difference (T T which is the numerator or dividend in the percent slip tenn (T,, T,)/T,,,. This number (T,,, T is stored in a register 21 for use in a subsequent division operation to obtain the quotient (T,, Tn)/T,,,. To carry out the desired division, the T count in the register 19 is successively subtracted from the (T,, T count in the register 21 until the remainder reaches zero (or goes negative), and the number of subtraction steps required to reduce the remainder to less than T is the desired quotient.

Thus, in the system illustrated in FIG. 1, the dividend (T T is passed through a multiplier to produce an output signal representing 100 (T T and this product is fed to a subtracting unit 23 which successively subtracts T,, from 100(T T Each time a subtraction step is carried out, the subtracting unit 23 increments a counter 24 by one. When the repetitive subtraction process results in a remainder of less than T,,,, using binary numbers, the subtraction unit 23 produces a borrow" output which stops the counter 24, and the count accumulated in the counter 24 at this point represents the desired quotient 100( T,,, ,,)/T,,,.

In accordance with another important aspect of the invention, means are provided for generating a signal representing a preselected maximum limit for the percentage of slip between the generator and motor, and for producing an excess slip signal whenever the measured percentage slip value exceeds the value of the preselected maximum limit. Thus, the illustrative system of FIG. 1 includes a set of thumbwheel switches 26 that can be set to different positions to preselect a desired maximum slip value. In order to determine whether the computed slip exceeds the preselected maximum value determined by the settings of the switches 26, the output of the counter 24 is applied to a comparator 25 which receives its other input from the switches 26. Whenever the measured slip number from the counter 24 exceeds the preselected maximum number from the thumbwheel switches 26, the comparator output actuates a utilization device 27. The utilization device 27 may be any suitable means for utilizing the output signal from the comparator 25, such as an alarm device for alerting the operator to the fact that an excess slip condition exists so that he can shut down the system or perhaps adjust the governor set point control 911 accordingly, or an automatic control system for adjusting the governor set point automatically in response to the comparator output signal.

' Each time the counter 24 is stopped at the end of a dividing operation, a reset signal generator 28 is actuated to produce a reset signal which resets the two detectors l4 and 15 and the counter 18 to condition the system for another operating cycle. Thus, the counter 18'counts another pair of periods T and T and the computing operation is repeated to determine a new quotient lO(T,,, g)/T,,,.

In accordance with one particular aspect of the invention, the motor and generator signals P, and P are both continuously monitored to'insure that the signals remain present during operation of the slip detection system. Without such monitoring, the termination of one of these input signals due to a malfunction, for example, could result in a calculation of zero slip or some other error which could mislead the operator. Thus, the signals P and P, are both applied to a monitor circuit 29 which is connected to the utilization device 27 for automatically actuating the alarm in response to termination of either one of the input signals P, and P Turning next to FIGS. 2a and 2b, there is shown in more detail an exemplary system of the type illustrated generally in FIG. '1. The primary input signals representing the generator speed N and the motor speed N,, are in digital. form, comprising series of pulses P, and P (FIGS. 4, 9 and generated at frequencies proportional to the speeds of the generator and'the motor, respectively. Transducers for generating such pulses are well known and may comprise Hall effect devices having toothed wheels 30 and 31 carried by the generator and motor shafts for inducing signals, such as signal f,,, in FIG. 4, in stationary pick-up devices 32 and 33 at frequencies proportional to the speeds of the respective shafts. In the illustrative system, the pick-up devices 32 and 33 are connected to Schmitt triggers 34 and 35 for converting the sinusoidal signals induced in the pick-up devices to square pulses P and P as illustrated in FIGS. 4, 9 and 10. A Schmitt trigger is a conventional regenerative bistable circuit whose state depends on the amplitude of the inputvoltage so that it can be used for squaring a sinusoidal input. Simple single pole filters formed by the RC networks RlCl and R2C2 on the inputs of the Schmitt triggers 34 and 35, respectively, remove induced noise from the output signals of the pick-up devices 32 and 33.

In order to convert the two series of pulses P and P to signals representing the periods T, and T,,, between pulses, which are proportional to the periods of rotation of the generator and motor, the output pulses P and P,,, from the Schmitt triggers 34 and 35 are applied to the clock inputs of a pair of conventional .IK-type flip- flops 36 and 37, respectively, operated in the toggle mode. Thus,- a binary 1 signal is applied to both the J and K inputs of each flip-flop so that the outputs Q and Q change state whenever the flip-flop is clocked; in the illustrative system the Q and Q outputs of the flip- flops 36 and 37 change state in response to each negative transition at the clock input, i.e., at the trailing edge of each positive-going pulse P or P,,, so that the outputs of the flip- flops 36 and 37 represent the periods T and T between successive pairs of pulses P, and P respectively. The resulting Q output of the flip-flop 36 is illustrated in FIG. 4 as signal PHAX; though not illustrated, the Q output of flip-flop36 is designated PHAX, the Q output of flip-flop 37 is designated PHBX, and the Q output of flip-flop 37 is designated PI-IBX. Prior to application of the pulses P and P,,, the two flip- flops 36 and 37 are cleared by the respective output signals from NOR gates 38 and 39, which will be described in more detail below. I

For the purpose of synchronizing the signals representing T, and T, with an internal clock signal, the Q and Q outputs of the flip- flops 36 and 37 are connected to theJ and K inputs, respectively, of'a second pair of JK-type flip-flops 40 and 41. The internal clock signal,

designated signal CL2 and illustrated in FIG. 4, is applied to the clock input of both the flip-flops 40 and 41. Each time one of the flip-flops 40 or 41 is clocked, the state of the J input thereof is transferred to the Q output, and the state of the K output is transferred to the Q output; thus the Q and Q outputs of the flip-flops 40 and 41 are identical to those of the flip- flops 36 and 37, respectively, except that they are synchronized with the clock signal CL2. The Q output of flip-flop 20 is designated PI-IA (FIG. 4), the Q output of flip-flop 40 is designated PHA (FIG. 5), and the Q output of flip-flop 41 is designated'PHB (FIG. 6).

' Assuming the flip-flop 40 has been cleared by the signal CLEARX (FIG. 4) from the gate 38 and a binary 1 signal is present at the J input of the flip-flop 40, the Q output (PHA) from the flip-flop 40 rises from a binary 0 to a binary 1, and the Q output (PI-IA) drops from 1 to 0, in response to the next negative transition in the clock signal CL2. The outputs of the flip-flop 40 then remain at these levels until the Q output from flipflop 36 returns to the 0 level, after which the Q and Q outputs of flip-flop 40 return to the 0 and 1 levels, respectively, in response to thenext negative transition in the clock signal CL2.

To measure the widths of the periods T,,, and T represented by the output signals from the flip-flops 40 and 41, the Q output signals from these flip-flops are used to control the gating of a second clock signal CLl to the count-up and count-down input terminals 50 and 51, respectively, of a 20-bit up-down binary counter 52. The pulses of the clock signal CLl are counted only during the intervals T, and T, represented by the signals PI-IA and PHB, respectively, so that the resulting counts are numerically proportional to the durations of the intervals'T and T Furthermore, the pulses gated into the counter 52 by the signal PHA representing T, are counted up, and the pulses gated into the counter by the signal PHB representing T, are counted down so that the resulting net count is numerically proportional to the difference T T which is the numerator or dividend in the per cent slip equation described previously.

Turning now to a more detailed description of the gating arrangement between the Q outputs of the flipflops 40 and 41 and the counter 52, the Q output from the flip-flop 40 and the inverted clock signal CLl are applied to a NOR gate 53 connected to the count-up input of the counter 52, while the 0 output from the flip-flop 41 and the inverted clock signal CLl are applied to a NOR gate 54 connected to the count-downinput. When the Q output from either flip-flop 40 or 41 is a binary 1 signal, the clock signal CLl does not pass the corresponding NOR gate 53 or 54, i.e., the output of the gate 33 or 34 is maintained at the binary 0 level. However, when the Q output of one of the flip-flops 40 or 41 is changed to a binary 0 signal, the clock signal CLl passes through the corresponding NOR gate 53 or 54 to produce the complement thereof (CLl) at the gate output, i.e., the output of the gate 53 (signal UPS in FIG. 5) or 54 (signal SUC in FIG. 6) switches between the binary 0 and 1 levels in synchronism with the clock signal CLl.

For the purpose of controlling application of the output signal UPS from the gate 53 to the counter 52, this signal UPS is applied to a NAND gate 55 which also receives the Q output from D-type flip-flop 57. Although the signal UPS is generated repetitively in response to the toggling of the flip-flop 36, it is necessary to block the application of the signal to the counter 52 while the width of the period T, is beingmeasured and while the computing portion of each cycle of operation is carried 5 out to determine the value of the percent slip ratio (T T,,)/T,,,. For this purpose, a binary 1 signal GO (FIG. 4), from a source to be described below, .is normally applied to the data input of the flip-flop 57, while the Q output (PHA) of the flip-flop 40 is applied to the clock input. The D-type flip-flop 57 is clocked by a positive transition at its clock input, so the binary l at the data input is transferred to the Q output in response to the trailing edge of signal PHA at the end of the period T,,,. The Q output of the flip-flop 57 is always the inverse of the Q output, so the Q output becomes a binary signal when the Q output goes to the binary 1 level. These Q and Q outputs are designated signals PHAD and PHAD, respectively, and are illustrated in FIGS. 4 and 5. 1

Since the data input to the D-type flip-flop37 is a continuous binary 1 signal during steady state operation, the Q and Q outputs thereof remain at the binary l and 0 levels until the flip-flop 57 is cleared by a reset signal (designated RST in FIG. 4) applied to its clear input at the end of each complete operating cycle. Thus, the signal PHAD applied to the NAND gate 55 is a binary 1 signal during one period T,,,, thereby en-- abling transmission of the clock signal CLl to the count-up input 50 during that period, and then is switched to a binary 0 signal at the end of the period T, to prevent thetransmission of any further signals to the count-up input 50 until the flip-flop 57 is cleared at the end of a complete operating cycle.

During the period T,,, whenthe gate 55 is enabled by the coincidence of binary l signals from both the gate 53 and the Q output of flip-flop 57, it produces an output signal UPT (FIG. 5) which is the complement of signal UPS during one period T,,,. This output signal is applied to a NAND gate 58 which receives its other 40 input signal SWC (FIG. 5) from a NAND gate 59. The purpose of the gate 59 is to apply the normal countdown input signal SUC to the count-up input 50 wheneverthe counter 52 counts down to zero before the end of the period T,,, which occurs only when the 45 period T, is greater than T Of course, this result can be obtained only when the motor speed is greater than the generator speed, which may happen in a transient condition. Such an event is detected by applying the borrow output signal BOR (FIG. 6) of the most significant position in the counter 52 to the clock input of a J K-type flip-flop 60 having a continuous binary 1 signal applied to its J and K inputs, so that the 0 output signal SWU (FIGS. 5 and 6) of the flip-flop 60 becomes a binary 1 whenever the flip-flop 60 is clocked by a negative transition in the signal BOR. The resulting binary 1 signal SWU enables the. gate 59 to pass the remainder of the count-down pulses (illustrated by signal SWC in FIG. 6) through the gate 58 to the count-up input 50, while blocking the transmission of any further pulses to the count-down input 51. Consequently, the counter 52 determines the absolute value of the term T T regardless of whether T, or T, is greater.

Whenever the gate 58 receives an operative count-up 65 signal UPT or SWC, it produces a corresponding output signal UP (FIG. 6) which is passed through an inverter 61 to provide the final signal UP (FIG. 6) that is applied to the fcounvup input 50. The counter 10 has a capacity of 20 bits, which means that it can count from zero through 1,048,575.

Turning next to the count-down phase of the counting operation that determines the, value of (T T the output of the gate 54 when the Q output of the flip-' flop 41 is a binary 0 signal is illustrated as signal SUC in FIG. 6. This output signal SUC is applied to a NAND gate 62 which also receives the output signal (FIG. 6')

from a NOR gate 63. The inputs to the NOR gate 63 are the signal SWU described previously, and the Q output signal PHBD from a D-type flip-flop 64. As described previously, the purpose of the signal SWU is to transfer the signal SUC from the count-down input to the count-up input of the counter 52 in the event that the counter reaches zero before the end of the period T,,. For this purpose, the binary 1 output signal SWU produced by the flip-flop in response to a BOR signal causes the output of the gate 63 to go to the binary 0 level, thereby disabling the gate 62 to interrupt transmission of the signal SUC to the count-down input 31.

The purpose of the flip-flop 64 is to control application of the signal SUC to the counter 52 when the BOR signal is 0. Although the signal SUC is generated repetitively in response to toggling of the flip-flop 37, this sig nal is to be applied to the counter 52 only during a single period T, following each period T in which the signal UP is applied to the counter. For this purpose, the signal GO normally applies a binary 1 signal to the data input of the flip-flop 64, while the Q output (PI-IB) of the flip-flop 41 is applied to the clock input. The D- type flip-flop 64 is clocked by a positive transition at its clock input, so the binary l at the data input is transvferred to the Q output in response to the trailing edge of signal PHB at the end of the period T The Q output of the flip-flop 64 is always the inverse of the Q output, so theQ output becomes a binary 0 signal when the Q output goes to the binary 1 level. These Q and Q out- .puts are designated signals PHBD and PHBD, respectively, and PHBD is illustrated in FIGS. 6 and 7.

Since the data input to the D-type flip-flop 64 is a continuous binary 1 signal during steady state operation, the Q and Q outputs thereof remain at the binary l and 0 levels, after being clocked by signal Pl-IB, until the flip-flop 64 is cleared by the reset signal RST applied to its clear input at the end of each complete operating cycle. Thus, the signal PHBD applied to the NOR gate 63 is a binary 0 signal during one period T,,, thereby producing a binary 1 output signal SWD for enabling the gate 62 to transmit the clock signal CLl to the count-down input 51 during that period, and then is switched to a binary 1 signal at the end of the period T, to prevent the transmission of any further signals to the count-down input 51 until the flip-flop 64 is cleared at the end of a complete operating cycle. The final output of the gate 62 is designated signal DN and is illustrated in FIG. 6.

In order to delay the generation of the first signal representing a period T, until after generation of the first signal representing a period T in each operating cycle, the two flip-flops 37 and 41 which generate the signals PI-IBX and PHB representing T, are disabled by the application of steady signals to their clear inputs. This is done so long as the signal PHAD exists and until the first signal. PI-IA representing T,,, has been generated.

flip-flops 37 and 41 to inhibit operation thereof. At the end of the first period T measured by the signal PHA, however, the signal PI-IAD is switched to the binary level, thereby producing a binary 1 output signal from the gate 39 to enable the flip-flops 37 and 41 so that these flip-flopsinitiate the measurement of the period T the next time the-signal P, is switched to the binary 1 level. As a result of this delay in the enabling of the flip-flops 37 and 41, the transition in the output PI-IBD of flip-flop 64 indicating the end of the first period T, does not occur until after the transition in the output of flip-flop 57 indicating the end of the first period T Moreover, the first transition in the signal PHB does not occur until after the first period T has been measured, even though the signal P,, is generated previously, so that application of the clock signal CLl to the count-down input 51 via gate 54 (controlled by signal PHB) is delayed until after measurement of the first period T,,,. I

In addition to terminating the application of clock pulses to the count-up input 50 at the end of the period T and initiating measurement of the period T the signal PI-IAD is used to cause storage of the number representing the width of the period T in al 6-bit register 65 (FIG. 2b). Thus, the signal Pl-IAD strobes the most significant 16 bits in the counter 52 into the register 65 after clock pulses have been counted upwardly for one period T,,,, and the register 65 then holds a number proportional to the duration of T,,,. Since the four least significant bits in the counter 52 are not transferred to the register 65, the number stored in the register 65 is actually the number representing T,, shifted four binary places to the left, which is equivalent to dividing the number by 16. The purpose of this division by 16 will be explained below.

When measurement of both periods T,,, and 7}, is completed, there is coincidence of the Q outputs of both the flip-flops 57 and 64 (signals PI-IAD and PI-IBD) at the binary 1 level for the first time. These outputs are both connected to a NAND gate 70 so that the coincidence of the binary l signals at the inputs to the gate 70 produces a binary 0 signal SMC (FIG. 8) at the gate output. This binary 0 signal SMC is applied to a pair of NOR gates 71 and 72 to enable these gates to pass clock signals CL2 and CLl, respectively. The output signal RTR (FIG. 7) from gate 72 leads the output signal CTR (FIG. 7) from the gate 71 and is applied to a 24-bit register 73 to strobe the 20 data bits from the counter 52 and the 4 data bits from a supplemental counter 74 into the register 73.

Referring to FIG. 3 for a more detailed description of the connections between the counters 53 and 74 and the registers 73 and 65, it can be seen that the counter 52 comprises five units 52a-52e having a capacity of four bits each, the register 65 comprises two eight bit units 65a and 65b, and the register 73 comprises three eight bit units 73a-73c. In response to the signal CTR, the four bits in the counter 74 and the four least significant bits in the counter 52, i.e., the four bits in unit 52a, are transferred to the first register unit 73a, the eight next most significant bits from counter units 52b and 520 are transferred to the second register unit 73b, and the six next most significant bits in counter units52d and 52e are transferred'to the third register unit 730. For reasons to be explained below, the two most significant bit locations in the counter unit 52e and the regis ter unit 730 are not utilized. The effect of introducing the four bits from the supplemental counter 74 into the four least significant positions in the register 73 is to shift the number from the counter 52 four places to the left, which is the same as multiplying the number representing (T by 16. As will be seen from the ensuing discussion, this is the first step of a three-step multiplication process which ends up multiplying the number representing (T,,, T,,) by 1,024. This is an approximation of the desired multiplier of 1,000, 100 of which is the multiplier included in the percent slip equation, and the other 10 of which converts the detected slip range of 0.1. to 9.9 percent to integers of l to 99. The use of 1,024 rather than 1,000 as a multiplier introduces a computational error of 2.4 percent, which for practical purposes is negligible in the illustrated system.

The next step in the computing process is to divide the number representing (T,, T by the number representing T,,, to obtain the quotient of (T,,, T,,)/T,,,. To

carry out the desired division, the T,,, count stored in v the two units 65a and 65b of the 16 bit register 65 is repetitively subtracted from the T,,, T, count in the reg ister 73 until the latter count reaches zero (or goes negative), and the number of subtraction steps required to reach zero is the quotient (T )/T,,,. In the illustrative system, the repetitive subtractions are performed by successively adding the twos complement of the divisor (T from register 65) to the dividend ((T,,' T,,) from register 53) until the sum goes to zero; the number of addition steps is then the desired quotient. The twos complement of the divisor is the complement of the binary number representing T with one added to it. For example, if the count representing the value of T, in register 65 is 7, or 001 l l in binary form, its complement is 11000, and adding one. to this complement gives 1100], which is the twos complement. It is an axiom of binary arithmetic that the addition of the twos complement of a first binary number to a second binary number gives the same result as subtracting the first number from the second number, if the carry resulting from the addition process is ignored.

To perform the desired addition, the illustrative system includes a conventional binary adder having two parallel entry terminals X and -Y for receiving signals digitally representing the two binary numbers to be added, a carry input terminal for adding a signal representing an extra one to the sum of the X and Y inputs, parallel exit-sum output terminals carrying signals digitally representing the sum of the numbers represented by the X, Yand carry inputs, and a carry output terminal 77 carrying a signal representing any carries resulting from the addition process. As shown in more detail in FIG. 3, the adder 75 comprises six four bit units 75a-75f with adjacent units having their carry inputs and outputs interconnected; each four bit unit has a four bit X input, a four bit Y input, and a four bit sum output.

Returning to a detailed description of the computation process, the twos complement of the binary number stored in the register 65 is formed by passing the 16 bits stored in the register 65 through two multibit inverters 74a and 74b to the X inputs of the first four four bit units 75a-75d of the 24 bit adder 75; applying binary l signals to the X inputs of the last two four bit units 752 and 75f of the adder 75 to complete the entire ones complement of the binary number from register 65; and then adding a one to the ones complement by applying a binary 1 signal to the carry input 76 of the adder 75 to form the two s complement. This formation of the twos complement in the adder 75 occurs automatically when the number representing T is transferred into the register 65 upon the appearance of the signal PHAD, since the register 65 is Connected directly to the adder 75 via the inverters 74a and 74b without any intermediate gates, and the binary l signals are continuously applied to the X inputs of the last two adder units 74eand 74f and the carry input 76.

Addition of the twos complement of the T',,, number to the number representing (T T,) X 16 is effected automatically when the latter number is strobed into the register 73 in response to the signal RTR. That is, the output of the register 74 is connected directly to the Y inputs of the adder 75, so that any number fed into the register 73 is immediately transferred'to the adder 75. In the process of transferring the number-representing (T T X 16 into the adder75, the number is shifted two more binary places to the left, which has the effect of multiplying the number by 4, so that the number actually-entered into the adder represents (T T X64. This is the second step of the three-step multiplication process described previously. The third step is effected by dividing the number representing (T,',, T X 64 by the number representing T,,,/ 16, which yields a quotient representing T T /T X 1,024; it will be recalled that 1,024 isthe desired product of the threestep multiplication.

Referring to FIG. 3 for a more detailed description of how the number representing (T T X 16 is shifted two binary places to the left in the process of being fed into the adder 75, it will be recalled that the last two most significant bit locations in the bit counter were not utilized. Similarly, the last two most significant bit locations in the register 73 are also not utilized. How ever, when the 18 bits of the binary number in the register 73 are transferred to the adder 75, they are transferred to the 18 most significant Y inputs to the adder, so that in effect the two empty spaces are transferred to the right end of the adder 75, thereby transferring the binary number two binary places to the left.

Each time a number is fed into the register 73, the adder 75 immediately sums the X and Y inputs to produce a binary output signal representing the sum of (i) the binary number representing (T T,-,) X 1,024 and (ii) the twos complement of the binary number representing T, (without the carry). This multi-bit numberrepresenting output signal is applied directlyto, parallel entry input terminals of the counter 52 which is used as a holding register to store each new minuend temporarily during the repetitive subtraction (division) process. As long as the output of the adder 75 does not go to zero, the carry output 77 thereof is a binary l signal CRY (FIG. 8) which enables a NAND gate 80 to apply the clock signal CL2 to an eight bit binary codeddecimal (BCD) counter 81. The output of the gate 80 is designated signal DEC and is illustrated in FIG. 8. As will be apparent from the ensuing description, the timing of the repetitive subtraction steps effected by the adder 75 is controlled by the clock signals CLl and CL2, both of which have the same frequency. Thus, the clock pulses comprising the signal DEC are applied to the counter 81 at the same rate at which the successive subtraction steps are carried out, so that the counter 81 p is incremented once for each subtraction step, as long as the signal CRY remains at the binary 1 level.

When the output of adder 75 is reduced to zero,' the carry" output CRY becomes a binary 0 signal, indicating that the division process is complete and that the number stored in the counter 81 at that time is the final quotient. "The switching of signal CRY to the binary 0 level disables the gate 80 to terminate the application of clock pulses to the counter 81, thereby preventing any further incrementing of the counter 81.

In order to prevent the counter 81 from responding to any clock pulses applied thereto prior to the first subtraction step, the signal SMC is applied to the clear input of the counter 81 todisable the counter until the beginning of the computation period of each operating cycle. It will be recalled that the signal SMC is the output of the gate 70, which switches from the binary l to the binary 0 level in response to completion of the measurement of both periods T, and T, in each operating cycle. As long as the signal SMC is at the binary 1 level, the counter 81 is disabled, but as soon as the signal SMC drops to the binary 0 level, the counter 81 is enabled to begin counting the clock pulses in signal DEC. As can be seen in FIG. 8, signal SMC drops to the binary 0 level just prior to initiation of the first subtraction step by signal RTR, which is synchronized with the clock signal CLl.

To cyclically repeat the binary subtraction process until the remainder is reduced to zero, at which time the carry output CRY of the adder 75 becomes a binary 0 signal, the sum" output of the adder 75 is repetitively strobed into the counters 52 and 74 by a signal CRT synchronized with the clock signal CL2. More specifically, the SMC signal from the gate enables the gate 71 to transmit the clock signal CL2 through an inverter 78 to the clock input of the counters 52 and 74 to transfer the data from the adder 75 to the counters 52 and 74. As can be seen in FIG. 7, synchronization of the signal CTR with the clock signal CL2 causes it to trail the Ciel-synchronized signal RTR by a brief interval corresponding to the phase difference between the two clock signals CLl and I CL2. Consequently, each time the signal RTR transfers data into the adder 75 to initiate a subtraction step, a brief interval is allowed for the data to settle, in the adder 75 before the adder output is fed back into the counters 52 and 74. This process is repeated cyclically until the adder output is reduced to zero, indicating that the division process is complete.

It should be noted at this point that one of the purposes of the supplemental counter 74 is to compensate for the difference in the capacities of the 20 bit counter 52 and the'24 bit adder 75. Since the adder output includes 22 bits, and only 18 bits of the 20 bit capacity of the counter 52 are utilized, the supplemental four bit counter 74 is used to hold the four least significant bits of the adder output before they are transferred to the register 73.

To briefly recapitulate the computing process that is carried out during the computation period indicated in FIG. 7, the up-down counter 52 first determines the difference (T T by counting up clock pulses during the period T, and then counting down clock pulses during the period T At the end of the up count, the number representing T is divided by 16 and stored in the register 65. At the end of the down count, the number representing (T T,,) is multiplied by 16 and stored in the register 73. Then to multiply (T T by a constant K 1,024 and divide the resulting product by T,,,: number T,,,/ l 6 stored in the register 65 is passed through the inverters 74a and 74b to form the ones complement thereof; this one's complement is applied to the X input of the adder 75 where it is added to the one applied to the carry input to form the two's complement of the number representing T,,,/l6;

and the number ,I6(T,,, T is multiplied by 4 and applied to the Y input of the adder 75. The adder 75 instantaneously adds the binarynumbers representing 64 (T,,, T and the twos complement of T,,,/ 16, which is the same as subtracting T,,,/l6, from 64(T o), and the resulting sum is stored in the counter 52 (used as a holding register) until arrival of the next signal CTR. This subtraction process is repeated until the remainder is reduced to zero, so that the number-of subtraction steps carried out represents the quotient 64(T T,,)/T,,,/ 16 or 1,024(T,, g)/ m which is proportional to the per cent slip.

It will be understood that the computation process A recapitulated above is cyclically repeated at a fast rate, thereby providing a rapidly iterating output representing the per cent slip. Although the duration of the computation period varies with changes in the magnitude of the per cent slip being computed, even the longest computation period requires only a fractionof a second in the high-speed digital signal processing system illustrated. Thus,'the system provides a highly reliable and substantially instantaneous indication of any change in the per cent slip.

In keeping with the invention, the control system includes means for continually comparing the measured slip value with the pre-selected maximumvalue, and means for indicating when the measured slip value exceeds the selected maximum value. Thus, in the illustrative system of FIGS. 2a and 2b signals representing a binary number proportional to a selected maximum value for the per cent slip being measured by the system are generated by any suitable source such as a series of thumbwheel-operated switches 90. The binary signals generated by the setting of these switches 90 are applied to one set of inputs to a comparator 91. The other set of inputs to the comparator 91 receives the binary signals digitally representing the number stored in the counter 81, which is the measured per cent slip value. The output of the comparator 91 is applied continuously to the data input of a D-type flip-flop 92 via an inverter 93 and a NAND gate 94. At the end of each operating cycle, the flip-flop 92 is clocked to sample the comparator output and thereby determine whether the measured percent slip value is above or below the preselected maximumvalue. If the measured value is above the preselected maximum value, the output of the flip-flop 92 renders a transistor T1 conductive to energize a suitable alarm device, such as by energizing a relay coil, for example, to inform the operator that an excessive slip condition has been detected.

The signal for clocking the flip-flop 92 is designated GCLK (FIG. 8) and is generated at the end of each computation period. More specifically, the carry output signal CRY from the adder 75 is passed through an inverter 100 to a NAND gate 101 so that when the signal CRY drops to the binary 0 level at the end of the division process, a binary l signal CRY is applied to the gate 101 so that it passes the clock signal CL2 to apply a signal GX (FIG. 8) to a NOR gate 102. The other input to the gate 102 is the signal SMC from gate 70, which is a binary 0 signal during the computation period. Thus as can be most clearly seen from FIG. 8, the output GCLK of the gate 102 goes to the binary 1 level when the signal GX drops to the binary 0 level, but after the signal SMC returns to the binary I level at the end of the computation period the output signal GCLK from the gate 102 is held atthe binary 0 level and is no longer affected by transitions in the signal GX. Consequently, the output of the gate 102 forms a single positive-going pulse at the end of each computation period, and it is this output signal that is designated signal GCLK and used to clock the flip-flop 9-2. When the signalGCLK clocks the flip-flop 92, the complement of the binary signal present at the data input is transferred to the Q output, which is applied to'a NAND gate so that the complement of the Q output is applied to the base of the transistor T1.

If the output of the counter 81 does not exceed the number represented by the settings of the thumbwheel switches 90, the comparator output is a binary 0 signal so that a binary 0 signal is applied to the data input of the flip-flop 92; consequently, a binary Q signal is applied to the base of the transistor T1 to maintain the transistor T1 in a nonconductive state. On the other hand, when the comparator output is a binary 1 signal, indicating that the output of the. counter 81 has exceeded the limit set by the thumbwheel switches 90, the flip-flop 92 causes a binary 1 signal to be applied to the base of the transistor T1, thereby rendering the transistor T1 conductive to actuatean alarm or other utilization device to indicate an excessive slip condition.

As still another feature of the invention, a counter overflow detector is provided to turn on the transistor T1 in response to an overflow of the BCD counter 81. Without this feature the counter 81 could pass the excessive slip value, reach its full capacity, and then reset itself and start counting from zero so that the apparent count at the end of the computation period would be below the preselected maximum. Thus, if the counter 81 overflows, a binary 1 signal is produced on an output line 103 and passed through an inverter 104 to the clock input of a D-type flip-flop 105, thereby producing a binary 0 signal at the Q output of the flip-flop 105. This binary 0 signal is applied to the NAND gate 94, thereby changing the output of the gate 94 from a binary 0 toabinary 1. Consequently, when the flip-flop 92 is closed by the GCLK signal going to the binary 1 level at the end of the computation period, a binary 1 signal is produced at the Q'output of the flip-flop 92 even though the apparent slip value represented by the count in counter 81 is below the preselected maximum slip value represented by the settings of the thumbwheel switches 90. Thus, the transistor T1 isvrendered conductive to actuate the excess slip alarm or other suitable utilization device.

In accordance with another specific aspect of the invention, a start-up check system is provided for detecting whether a predetermined number of generator pulses P, are generated before the first motor pulse P,,,. If they are, the motor is either not'starting or there is a malfunction in the motor pulse generating system, so the system immediately activates the excess slip indicator or other utilization device so that appropriate remedial action can be taken by the operator. Thus, the generator pulses P, are applied to a NOR gate whose other input is the Q output of a D-type flip-flop l l 1. The motor pulses P, are applied to the clock input of another D-type flip-flop 112 whose data input is the 0 output of the flip-flop 111.

When the system is started up, the generator pulses P, are passed through the gate 110 (signal UPF in FIG. 9) and an inverter 113 to the auxiliary counter unit 74 which counts the pulses and produces a corresponding output on a series of output lines indicated at 74a. A

selected combination of these output lines 74a are connected to a NAND gate 114 so that the gate 114 produces a binary signal LKOUT in response to the counting of a predetermined number of generator 'puisem, riiisnaaryibmpm signal from the gate m clockinput to flip-flop 111. The Q output signal STRT of the flip-flop 111 is applied to the gate 110to prevent the application of any further generator pulses P, to the counter 74, while the Q output signal STRTis applied to the data input of the flip-flop 112 to hold the Q output signal GO (FIGS. 4 and 9) of the flip-flop 1 12 at the binary 0 level. This binary 0 signal G0 is passed through a NOR gate 115 to apply a binary 1 signal SOK (FIG. 9) to the preset input of the flip-flop 111.

In order to actuate the alarm when no motor pulses P, have been received within the predetermined startup check interval, the Q output (GO) of the flip-flop 112 and the Q output (STRT) of the flip-flop 111 are applied to a NAND gate 115 connected to the preset input of the flip-flop 92. Both the inputs to the gate 115 are thus binary 1 signals, producing a binary 0 output which overrides the synchronous inputs to the flip-flop 92 to produce a binary 0 signal at the Q output and thereby turn on the transistor Tl. When a motor pulse P,, is received at the clock inpu of the flip-flop 112 before the predetermined number of generator pulses has been counted, the output of the gate 114 (signal LKOUT) is a binary 1 signal, producing a binary l at the data input to the flip-flop 112 so that the arrival of P produces a binary 1 signal G0 at the Q output of flip-flop 1 12. Thus, the Q output (GO) of the flip-flop 112 is a binary 0 signal which holds the output of the gate 115 at the binary 1 level so that the flip-flop 92 is not preset. This prevents actuation of the alarm or other utilization device controlled by the transistor T1. At the same time, the switching of signal GO to the binaryIO level enables the flip-flops 36 and 40 so that the system is free tobegin measuring the period T,,,. The signal .60 also furnishes the required binary 1 signal at the data inputs of the flipeflops 57 and 64.

Yet another feature of the invention is the provision of monitoring means to ensure that both the motor and generator signals P and P, are present and remain present throughout operation of the system. Without such a check, the termination of one of these input signals due to a malfunction could result in a calculation of zero slip or some other error which could mislead the operator. Thus, the two input signals P and P, are applied-to a pair of monostable (single-shot) multivibrators 120 and 121 through a pair of inverters 122 and 123, respectively. Whenthe multivibrators 120 and 121 are triggered bythe input signals, the respective outputs OS1 and 082 are switched from the binary 0 level to the binary 1 level for predetermined intervals which are longer than the interval between a pair of successive pulses P 'and P,. Consequently, as long as both signals P,, and P, are pr'esent,'the output of a NAND gate 124 is a continuous binary 0 signal. This signal TPE (FIG. 10) is applied to the clock input of a D-type flip-flop 125 which has a continuous binary 1 signal applied to its data input. In the event'that either signal P, or P is not received within the interval of the binary 1 output of the multivibrator 121 or 120, respectively, signal TPE goes to the binary 1 level,

thereby clocking the flip-flop to produce a binary 1 signal FFB (FIG. 10) at the Q output. This output is passed through an inverter 126, producing a binary 0 signal that is applied to the gate 95 to render the transistor Tl conductive. That is, the gate 95 responds to the binary 0 from inverter 126 to produce a binary l which is applied to the base of the transistor T1 to energize the alarm controlled thereby.

To reset the entire slip detection system after each operating cycle, i.e., at the end of each computation period, the signalGCL'K triggers a monostable (single shot) multivibrator 130 to generate reset signals RST and RST (FIGS. 4 and 8). Thus signal GCLK is passed through an inverter 131 to form'si'gnal GCLK, which is passed through a NAND gate 132 to form a signal LPST (FIG. 8). Signal LPST, in turn, is passed through an inverter 134 to fomi a signal SRT (FIG. 8) to trigger the multivibrator 130. More specifically, when signal GCLK goes to the binary 1 level at the end of the computation period, GCLK goes to the binary 0 level to switch the output of gate 132 (signal LPST) to the binary 1 level, thereby switching signal SRT to the binary 0 level and signal SRT to the binary I level which triggers the multivibrator 130. This causes the Q and Q output signals (RST and RST) of the multivibrator 130 to switch to the binary l and 0 levels, respectively, for a predetermined interval, after which they automatically return to their normal binary 0 and 1 levels.

The binary 1 signal RST is used to clear the JK-type flip- flops 36, 37, 40 and 41 and the counters 52 and 74, while the binary 0 signal RST is used to clear the D- type flip- flops 57, 64 and 105. Thus, the binary 1 signal RST is applied to the two NOR gates 38 and 39, thereby producing binary 0 outputs (e.g., output signal CLEARX from gate 38, illustrated in FIG. 4) which are applied to the clear inputs of flip- flops 36, 37, 40 and 41 tohold the Q outputs of these flip-flops at the binary 0 level at least until signal RST returns to the binary 0 level. To clear the counters 52 and 74, the signal RST is applied directly to the clear inputs thereof. Similarly, the binary 0 signal RST is applied directly to the clear inputs of the Dv-type flip- flops 57, 64 and 105 to reset these three units.

The reset signals RST and RST are also generated in response to two other signals, AST or GST. The first of these signals, namely AST, is an anti-hang up signal produced to reset the system in case the register 65 contains-a zero, so that the signal GCLK would never be generated. Thus, signal AST is generated whenever more than six transitions occur at the Q output (Pl-IA) of the flip-flop 37 before a transition occurs at the Q output PHAD of flip-flop 57'. To this end, a counter is incremented by one in response to each transition in signal PI-IA, and is reset each time signal PI-IAD goes from the binary 1 level to the binary 0 level. The 2 and4 output lines of the counter 140 are connected to a NAND gate 141, indicating the occurrence of six transitions insignal PI-IA. If a binary 1 signal appears on both of these counter output lines before the occurrence of a negative transition in signal PI-IAD, the output of the gate 141 goes from the binary 1 level to the binary 0 level. This binary 0 signal is applied to the NAND gate 132 which normally receives a binary l signal GCLK so that the gate output LPST becomes a binary 1 signal. This binary 1 signal LPST is passed on through the NOR gate 133 and the inverter 134 to apply a binary 1 signal to the multivibrator 130,

. 1 9 thereby triggering the multivibrator to generate the reset signals RST and RST.

Signal GST generates the reset signals whenever the power is turned on to the system. Thus, the power is turned on by closing a switch S1,.thereby charging a capacitor C3 through a resistor R3 from a voltage source V1. When the capacitor C3 is charged to a predetermined level, a zener diode D1 becomes conductive to render a transistor T2 conductive. This generates a 1 signal GST at one of theinputs to the NOR gate 123 to trigger the multivibrator 120 and thereby reset the system in the manner already described above.

To ensure actuation of the alarm in response to an excess slip condition or any of the malfunctions described above, the reset signals RST and RST do not reset any of the alarm-actuating components; a separate system is provided for resetting these components in response to the power on signal GST or an external reset command signal. More specifically, the reset signals RST and RST do-not' reset any of the flip- flops 92, 111, or 125 which control actuation of the alarm via transistor T1. To reset these flip-flops whenever the power supply to the system is'turned on by closing the switch S1, the binary 1 signal (GST) from the transistor T2 triggers a monostable single-shot multivibrator 150 to generate a binary 1 signal for a predetermined interval at the Q output (signal FFR) and a binary signal for a predetermined interval at the Q output (signal FFR, FIG. 9). The signal FFR clears the flip- flops 92, 112 and 125 (the latter via inverter 151), while the signal FFR clears the flip-flop 111 via NOR gate 115.

To permit resetting of the entire system while the power is on, the reset signals FFR and FFR may also be generated in response to an external reset command signal. For example, it may be desired to generate such signals when the slip detector is switched from one alternator to another. In the system of FIGS. 2a and 2b,

' the means for initiating a reset command signal is exemplified by a switch S2 connected between a voltage source V2 and the base of a transistor T3. When closed, the switch S2 renders a transistor T3 conductive via diode D2, and the resulting signal PST (FIG. 10) at the collector of the transistor T3 triggers the single shot 150 to generate the reset signals FFR and FFR and thereby reset the flip flops 92, 111, 112 and 125.

As can be seen from the foregoing detailed descrip- .tion, this invention provides a step detection system which continuously monitors the per cent slip between the motor and the generator, and actuates a utilization device such as an alarm or automatic shut-down device whenever the slip exceeds a predetermined limit. The

system has a high degree of accuracy and reliability over a wide speed range, and the thumbwheel switches permit convenient manual adjustment of the predetermined slip limit. The system continually computes the per cent slip and provides a substantially instantaneous indication of whether the per cent slip is above or below the predetermined limit, and is characterized by high reliability and immunity from aging or drift by virtue of the digital signal processing on-a rapidly iterating basis. In addition, thesystem immediately senses a failure of the motor to start and provides an indication of suchv failure, and also continuously monitors the primary inputs to the system and provides a substantially instantaneous indication of any malfunction that results in an interruption of such inputs.

What is claimed is: 1. A system for detecting excessive slip between the speed of an a-c. motor and the speed of an a-c. generator supplying power to said motor at a variable fre- 5 quency, said system comprising the combination of a. means for generating a first electrical signal representing the speed of the generator,

b. means for generating a second electrical signal representing the speed of the motor,

0. means for generating a third electrical signal representing a preselected maximum limit for thepercentage of slip between said generator and said motor,

d. computing means responsive to said first and second signals for producing an electrical output signal representing K(N m)/N,, where K is a predetermined constant, N, is the generator speed, and N is the motor speed,

e. and means responsive to said third signal and said output signal for producing an excess slip output signal whenever the value represented by said output signal exceeds the preselected limit represented by said third signal. 2. A system for detecting excessive slip as set forth in claim 1 wherein said means for generating said first electrical signal comprises means for generating pulses at a frequency proportional to the generator speed, and said means for generating said second electrical signal comprises means for generating pulses at a frequency proportional to the motor speed.

3. A system for detecting excessive slip as set forth in claim 2 wherein said computing means includes 1. means responsive to said first signal for producing an electrical signal digitally representing a number proportional to the duration of the period T be tween pulses in said first signal,

2. means responsive to said second signal for producing an electrical signal digitally representing a number proportional to the duration of the period T,, between pulses in said second signal,

3. and means responsive to said T and T,,, signals for producing an electrical signal digitally representing a number proportional to K( T T,,)'/T,,,.

4. A system for detecting excessive slip as set forth in claim 3 wherein said means for producing said signal representing a number proportional to K( T ,,)/T,,,=

includes a source of clock pulses, an up-down counter having count-up and count-down input terminals and an output terminal, means for applying said clock pulses to the count-up input terminal of said counter during the period m, and means for applying said clock pulses to the count-down input terminal of said counter during the period T, for producing an electrical signal at the counter output terminal digitally representing a number proportional to the difference (T,, T

5. A system for detecting excessive slip as set forth in claim 3 wherein said means for producing said signal digitally representing a number proportional to K( T, T,,)/T comprises 1. means for generating an electrical signal digitally representing a number proportional to the difference (T T i 2. means responsive to said signals digitally'representing numbers proportional to (T and T,,,

' for repetitively subtracting the number proportional to T from the number proportional to (T,,, until the remainder is reduced to zero,

said output signal.

3. and means for counting the number of subtraction steps required to reduce said remainder to zero.

6. A system for detecting excessive slip asset forth in claim wherein said means for producing said signal representing a number proportional to (7",, T includes anup-down counter, and means for recycling an electrical signal digitally representing the remainder from each of the repetitive subtraction steps to said counter for use as the minuend in the next subtraction step.

7. A system for detecting excessive slip as set forthin claim 5 wherein said means for repetitively subtracting the number'proportional to T, from thenumber proportionalto (T,, T comprises means for producing an electrical signal digitally representing the twos complement of a binary number proportional to T and adding means for producing an electrical signal digitally representing the sum of said twos complement and a binary number proportional to (T,,, T

8. Asystem for detecting excessive slip as set forth in claim 7 wherein said adding means is a binary adder having a carry output, and including an electronic counter connected to saidcarry output for counting the number of addition steps which yield a carry to produce an electrical signal digitally representing a number proportional 'to. the quotient (T g)/T,,,.

. 9. A system for detecting excessive slip as set forth in claim 1 wherein said means for generating said third signal includes a set of manually operable switch means for selecting said maximum limit.

10. A system for detecting excessive slip as set forth in claim 1 wherein said means for producing an excess slip signal comprises a comparator for comparing said third signal and said output signal.

11. A system for detecting excessive slip as set forth in claim 2 which includes means for producing a start signal in response to generation of the first pulse in said second signal within a'predetermined interval following generation of the first pulse in said first signal, and means for activating a utilization device in response to the absence of said start signal after said predetermined interval. 3

12. A slip detection system as set forth in claim 5 which includes overflow detection means for activating a utilizationdevice in response to an overflow of said counter.

13. A slip detection system as set forth in claim 1 which includes means for monitoring said signals representing the speeds of the motor and generator, means for producing an output signal in responseto termination of either of said speed-representing signals, and means for activating a utilization device in response to 14. A slip detection system as set forth in claim 1 which includes internal reset means for automatically resetting said system at the end of each cycle of operation of said computing means, and means responsive to production of said excess slip signal prior to the resetting operation for maintaining said excess slip signal during and subsequent to the resetting operation.

15. A slip detection system as set forth in claim 1 which includes external reset means responsive to a command signal for resetting the entire slip detection. system including the means for producing said excess slip signal.

16. A slip detection system as set forth in claim which includes means responsive to the absence of either of said speed-representing signals at startup of the system for activating a utilization device. I

17. A system for signaling the percentage difference between'tworecurring signals having variable periods,

said system comprising the combination of a. an up-down counter having a count-up input terminal, a count-down input terminal, and output terminals carrying electrical signals digitally representing the number contained in the counter,

b. a source of clock pulses,

c. means responsive'to a first one of said recurring signals for applying said'clock pulses to said countup input terminal during one period of said first signal to produce counter output signals digitally representing a number T,, proportional to the duration of said one period of said first signal,

d. means'responsive to the second recurring signal for applying said clock pulses to said count-down input terminal during one period of said second signal to produce counter output signals digitally representing a number K( 7",, T,,) proportional to the difference between the durations of the periods of said first and second signals,

e. subtracting means responsive to said output signals digitally representing said numbers T and K( T,,

I T for producing output signals digitally representing thedifference K( T T,,,,

f. means for repetitively applying said difference output signals from said subtracting means and said signals representing said number T, to said subtracting means until the output signals therefrom represent a zero difference,

g. a source of clock pulses generated at the same frequency at which said differenceoutput signals are repetitively applied to said subtracting means,

h. and an electronic counter for counting the clock pulses from source (g) and producing output signals digitally representing the number of subtraction operations required to reduce the difference represented by the output signals from said subtracting means to zero, whereby the output signals from said counter digitally represent the quotient of nz a)/ m- 18. A system as set'forth in claim 17 wherein said subtracting means comprises means for producing'electrical signals digitally representing the twos complement of a binary number T,,,, and adding means for producing an electrical signaldigitally representing the sum of said twos complement and a binary number K( m u)- I 19. A system as set forth in claim 18 wherein said adding means is a binary adder having a carry output for producing a carry output signal as long as said sum is greater than zero, and including means responsive to said carry output signal for applying the clock pulses from source (g) to said counter only until said sum is reduced to zero. A

20. A method for detecting excessive slip between resenting the speed of the motor,

Claims (35)

1. A system for detecting excessive slip between the speed of an a-c. motor and the speed of an a-c. generator supplying power to said motor at a variable frequency, said system comprising the combination of a. means for generating a first electrical signal representing the speed of the generator, b. means for generating a second electrical signal representing the speed of the motor, c. means for generating a third electrical signal representing a preselected maximum limit for the percentage of slip between said generator and said motor, d. computing means responsive to said first and second signals for producing an electrical output signal representing K(Ng Nm)/Ng where K is a predetermined constant, Ng is the generator speed, and Nm is the motor speed, e. and means responsive to said third signal and said output signal for producing an excess slip output signal whenever the value represented by said output signal exceeds the preselected limit represented by said third signal.

2. A system for detecting excessive slip as set forth in claim 1 wherein said means for generating said first electrical signal comprises means for generating pulses at a frequency proportional to the generator speed, and said means for generating said second electrical signal comprises means for generating pulses at a frequency proportional to the motor speed.

2. means responsive to said second signal for producing an electrical signal digitally representing a number proportional to the duration of the period Tm between pulses in said second signal,

2. means responsive to said signals digitally representing numbers proportional to (Tm - Tg) and Tm for repetitively subtracting the number proportional tO Tm from the number proportional to (Tm - Tg) until the remainder is reduced to zero,

3. and means for counting the number of subtraction steps required to reduce said remainder to zero.

3. and means responsive to said Tg and Tm signals for producing an electrical signal digitally representing a number proportional to K(Tm - Tg)/Tm.

3. A system for detecting excessive slip as set forth in claim 2 wherein said computing means includes

4. A system for detecting excessive slip as set forth in claim 3 wherein said means for producing said signal representing a number proportional to K(Tm - Tg)/Tm includes a source of clock pulses, an up-down counter having count-up and count-down input terminals and an output terminal, means for applying said clock pulses to the count-up input terminal of said counter during the period Tm, and means for applying said clock pulses to the count-down input terminal of said counter during the period Tg for producing an electrical signal at the counter output terminal digitally representing a number proportional to the difference (Tm - Tg).

5. A system for detecting excessive slip as set forth in claim 3 wherein said means for producing said signal digitally representing a number proportional to K(Tm - Tg)/Tm comprises

6. A system for detecting excessive slip as set forth in claim 5 wherein said means for producing said signal representing a number proportional to (Tm - Tg) includes an up-down counter, and means for recycling an electrical signal digitally representing the remainder from each of the repetitive subtraction steps to said counter for use as the minuend in the next subtraction step.

7. A system for detecting excessive slip as set forth in claim 5 wherein said means for repetitively subtracting the number proportional to Tm from the number proportional to (Tm - Tg) comprises means for producing an electrical signal digitally representing the two''s complement of a binary number proportional to Tm, and adding means for producing an electrical signal digitally representing the sum of said two''s complement and a binary number proportional to (Tm - Tg).

8. A system for detecting excessive slip as set forth in claim 7 wherein said adding means is a binary adder having a carry output, and including an electronic counter connected to said carry output for counting the number of addition steps which yield a carry to produce an electrical signal digitally representing a number proportional to the quotient (Tm - Tg)/Tm.

9. A system for detecting excessive slip as set forth in claim 1 wherein said means for generating said third signal includes a set of manually operable switch means for selecting said maximum limit.

10. A system for detecting excessive slip as set forth in claim 1 wherein said means for producing an excess slip signal comprises a comparator for comparing said third signal and said output signal.

11. A system for detecting excessive slip as set forth in claim 2 which includes means for producing a start signal in response to generation of the first pulse in said second signal within a predetermined interval following generation of the first pulse in said first signal, and means for activating a utilization device in response to the absence of said start signal after said predetermined interval.

12. A slip detection system as set forth in claim 5 which includes overflow detection means for activating a utilization device in response to an overflow of said counter.

13. A slip detection system as set forth in claim 1 which includes means for monitoring said signals representing the speeds of the motor and generator, means for producing an output signal in response to termination of either of said speed-representing signals, and means for activating a utilization device in response to said output signal.

14. A slip detection system as set forth in claim 1 which includes internal reset means for automatically resetting said system at the end of each cycle of operation of said computing means, and means responsive to production of said excess slip signal prior to the resetting operation for maintaining said excess slip signal during and subsequent to the resetting operation.

15. A slip detection system as set forth in claim 1 which includes external reset means responsive to a command signal for resetting the entire slip detection system including the means for producing said excess slip signal.

16. A slip detection system as set forth in claim 1 which includes means responsive to the absence of either of said speed-representing signals at start-up of the system for activating a utilization device.

17. A system for signaling the percentage difference between two recurring signals having variable periods, said system comprising the combination of a. an up-down counter having a count-up input terminal, a count-down input terminal, and output terminals carrying electrIcal signals digitally representing the number contained in the counter, b. a source of clock pulses, c. means responsive to a first one of said recurring signals for applying said clock pulses to said count-up input terminal during one period of said first signal to produce counter output signals digitally representing a number Tm proportional to the duration of said one period of said first signal, d. means responsive to the second recurring signal for applying said clock pulses to said count-down input terminal during one period of said second signal to produce counter output signals digitally representing a number K(Tm - Tg) proportional to the difference between the durations of the periods of said first and second signals, e. subtracting means responsive to said output signals digitally representing said numbers Tm and K(Tm - Tg) for producing output signals digitally representing the difference K(Tm - Tg) - Tm, f. means for repetitively applying said difference output signals from said subtracting means and said signals representing said number Tm to said subtracting means until the output signals therefrom represent a zero difference, g. a source of clock pulses generated at the same frequency at which said difference output signals are repetitively applied to said subtracting means, h. and an electronic counter for counting the clock pulses from source (g) and producing output signals digitally representing the number of subtraction operations required to reduce the difference represented by the output signals from said subtracting means to zero, whereby the output signals from said counter digitally represent the quotient of K(Tm - Tg)/Tm.

18. A system as set forth in claim 17 wherein said subtracting means comprises means for producing electrical signals digitally representing the two''s complement of a binary number Tm, and adding means for producing an electrical signal digitally representing the sum of said two''s complement and a binary number K(Tm - Tg).

19. A system as set forth in claim 18 wherein said adding means is a binary adder having a carry output for producing a carry output signal as long as said sum is greater than zero, and including means responsive to said carry output signal for applying the clock pulses from source (g) to said counter only until said sum is reduced to zero.

20. A method for detecting excessive slip between the speed of an a-c. motor and the speed of an a-c. generator supplying power to said motor at a variable frequency, said method comprising the steps of a. generating a first electrical signal representing the speed of the generator, b. generating a second electrical signal representing the speed of the motor, c. generating a third electrical signal representing a preselected maximum limit for the percentage of slip between said generator and said motor, d. producing an electrical signal in response to said first and second signals and representing K(Ng - Nm)/Ng where K is a predetermined constant, Ng is the generator speed, and Nm is the motor speed, e. rapidly iterating steps (a) through (d), f. and producing an excess slip signal in response to said third signal and said output signal whenever the value represented by said output signal exceeds the preselected limit represented by said third signal.

21. A method for detecting excessive slip as set forth in claim 20 wherein said first signal comprises pulses generated at a frequency proportional to the generator speed, and said second signal comprises pulses generated at a frequency proportional to the motor speed.

22. A method for detecting excessive slip as set forth in claim 21 including the steps of producing an electrical signal digitally representing a number proportional to the period Tg between pulses in said first signal, producing an electrical signal digitally representing a number proportional to the period Tm between pulses in said second signal, and producing an electrical signal digitally representing a number proportional to K(Tm - Tg)/Tm in response to said Tg and Tm signals.

23. A method for detecting excessive slip as set forth in claim 22 wherein said signal representing a number proportional to K(Tm - Tg)/Tm is produced by generating a series of clock pulses, applying said clock pulses to the count-up input terminal of an up-down counter during the period Tm, and applying said clock pulses to the count-down input terminal of said counter during the period Tg for producing an electrical signal digitally representing a number proportional to the difference (Tm - Tg).

24. A method for detecting excessive slip as set forth in claim 22 wherein said signal representing a number proportional to K(Tm - Tg)/Tm is produced by generating an electrical signal digitally representing a number proportional to the difference (Tm - Tg), repetitively subtracting the number proportional to Tm from the number proportional to (Tm - Tg) until the remainder is reduced to zero, and counting the number of subtraction steps required to reduce said remainder to zero.

25. A method for detecting excessive slip as set forth in claim 24 wherein the repetitive subtraction is carried out by producing an electrical signal digitally representing the two''s complement of a binary number proportional to Tm, and producing an electrical signal digitally representing the sum of said two''s complement and a binary number proportional to (Tm - Tg).

26. A method for detecting excessive slip as set forth in claim 24 wherein the remainder from each of the repetitive subtraction steps is used as the minuend in the next subtraction step.

27. A method for detecting excessive slip as set forth in claim 24 which includes the step of activating a utilization device in response to the counting of a number of subtraction steps above a predetermined limit.

28. A method for detecting excessive slip as set forth in claim 25 wherein the signal representing a number proportional to the quotient (Tm - Tg)/Tm is generated by counting the number of binary addition steps which yield a carry.

29. A method for detecting excessive slip as set forth in claim 21 which includes the steps of producing a start signal in response to generation of the first pulse in said second signal within a predetermined interval following generation of the first pulse in said first signal, and activating a utilization device in response to the absence of said start signal after said predetermined interval.

30. A method for detecting excessive slip as set forth in claim 20 which includes the steps of monitoring said signals representing the speeds of the motor and generator, producing an output signal in response to termination of either of said speed-representing signals, and activating a utilization device in response to said output signal.

31. A method for detecting excessive slip as set forth in claim 20 which includes the step of activating a utilization device in response to the absence of either of said speed-representing signals at start-up.

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