US3817023A - Clock devices - Google Patents

Clock devices Download PDF

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Publication number
US3817023A
US3817023A US00350201A US35020173A US3817023A US 3817023 A US3817023 A US 3817023A US 00350201 A US00350201 A US 00350201A US 35020173 A US35020173 A US 35020173A US 3817023 A US3817023 A US 3817023A
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United States
Prior art keywords
counter
signal
signals
minute
generating
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Expired - Lifetime
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US00350201A
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English (en)
Inventor
T Kashio
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G5/00—Setting, i.e. correcting or changing, the time-indication
    • G04G5/04—Setting, i.e. correcting or changing, the time-indication by setting each of the displayed values, e.g. date, hour, independently
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G5/00—Setting, i.e. correcting or changing, the time-indication
    • G04G5/02—Setting, i.e. correcting or changing, the time-indication by temporarily changing the number of pulses per unit time, e.g. quick-feed method

Definitions

  • the time is displayed by means of a short hand which indicates hours and a long hand which indicates minutes.
  • the time is analogously displayed by the rotation of the short and long hands on a dial plate, and the time adjustment is made by manually rotating the long hand.
  • it is possible to adjust the time in a unit of seconds, for example 30 seconds or seconds by rotating the long hand to any desired positions on the dial plate.
  • an object of this invention to provide an improved clock device including simple means for accurately adjusting or correcting the time in a unit of seconds.
  • Another object of this invention is to provide a clock device including an improved electronic driving circuit of compact construction capable of providing digital or analogue display of hours and minutes even in clocks of small size and can accurately adjust or correct the displayed time in a unit of seconds.
  • a clock device comprising a source of signals having a stable frequency, a second" counter to count signals from said signal source and for generating 1 minute stepping signals at a rate of one per 60 seconds, a minute counter to count the one minute stepping signals for generating one hour stepping signals at a rate of one per 60 minutes, an .hour" counter for counting the 1 hour stepping signals, and means to generate a first signal for stopping the counting operation and clearing the content of the second counter and for stepping by one step the content of the min- 'ute" counter and a second signal for causing the cleared second counter to commence the counting operation of seconds from the initial count thereof.
  • a pulse signal for stepping by one the contents of a counting circuit is hereinafter referred to as a stepping signal.”
  • a clock device comprising a source of signals having a stable frequency a second counter to count signals from said signal source and for generating l minute stepping signals at a rate of one per 60 seconds, a minute counter to count the 1 minute stepping signals for generating 1 hour stepping signals at I a rate of one per 60 minutes, an hour counter for counting 1 hour" stepping signals, and means to generate a first signal for stopping the counting operation and clearing the content of the second counter and to generate a second signal for causing the cleared second counter to commence the counting operation of signals from the initial count thereof and advancing by one step the content of the minute counter.
  • FIG. I is a plan view of a digital wrist watch embodying the invention.
  • FIG. 2 is a block diagram showing the driving and control circuit for the watch shown in FIG. 1;
  • FIG. 3 shows one example of a circuit which generates a minute stepping signal when the correction key shown in FIG. 2 is operated;
  • FIG. 4 shows one example of a circuit which generates a minute stepping signal when the correction key shown in FIG. 2 is released.
  • FIG. 5 is a block diagram showing another example of time correcting controller.
  • a display plate 11a of a body 11 of a digital wrist watch shown in FIG. 1 is provided with an hour display section 12 and a minute display section 13, each consisting of two digits. These hour" and minute display sections 12 and 13 are made up of a plurality of liquid crystal display elements or digit display tubes so as to display any time, for example 10 oclock and 29 minutes.
  • a time adjusting or correction key 14 is provided on the display plate 11a and the body 11 is secured to a wrist of a user by means of a band 15.
  • clock signals utilized as the reference for counting the time are generated by a clock pulse generator 16 and are sent to an n-step counter 18 through one input of an AND gate circuit 17. Since the output of key 14 (which is coupled, for example, to a voltage source V) is applied to the other input of AND gate circuit 17 through an inverter 19, when the key 14 is not operated or released the clock pulses are continuously supplied to the counter 18. When the number of the steps n of the counter 18 and the frequency F of the clock pulse are set to satisfy a relation 1/n F 1, then the counter 18 will produce one carry signal at each second. The counter 18 is reset by the output of key 14.
  • the carry signal or second signal generated by counter 18 is applied to the inputs of an AND gate circuit 20 together with the output from inverter 19 and the output from AND gate circuit 20 is applied as the second signal to a second counting circuit in the form of a 60-step counter 21.
  • the counter 21 is constructed to be reset by the output from key 14 and the carry signal generated by this counter is applied to a 60-step minute counter 23 through an OR gate circuit 22 together with the output from key 14.
  • the carry signal generated by counter 23 is applied to a l2-step hour counter 24.
  • minute counter 23 and hour counter 24 are supplied to decoders 25 and 26, respectively, where they are converted into signals suitable for use in the display elements utilized in minute and hour display sections 13 and 12.
  • the outputs from decoders 25 and 26 are impressed upon minute and hour display sections 13 and 12 via drivers 27 and 28, respectively, to drive these sections to provide a visible display of the time, for example, 10 oclock 29 minutes. 1
  • the clock device operates as follows. Under the nor- 7 mal condition where the correction key or button 14 is not operated, the AND gate circuit 17 is enabled to cause counter 18 to count the number of pulses generated by the clock pulse generator 16 so as to provide carry signals to counter 21 through enabled AND gate circuit 20 at a rate of one carry signal per second. The carry signals generated by counter 21 are supplied to counter 23 at a rate of one per minute. The carry signals produced by counter 23 are hour stepping sig nals produced at a rate of one per hour so that the content of counter 24 represents hours. Consequently, when the key 14 is not operated, hour and minute display sections 12 and 13 of the'watch 11 provides a digital display of hours and minutes corresponding to the contents of counters-24 and 23, respectively.
  • the correction key 14 is operated.
  • the resulting signal not only resets counter 18 but also clears counter 21.
  • this signal is also applied to counter 23 as the minute stepping signal.
  • gate signals of AND gate circuits 17 and 20 are interrupted so that the counting operation of the counter 18 is stopped and the input to second counter 21 is also interrupted.
  • the operation of the correction key 14 is continued until the time'that has been displayed by the minutes display section 13 is reached. For example, when correction key 14 is operated at a time of oclock 29 minutes as shown in FIG. 1 the time display will be changed to 10 oclock 30 minutes and the key 14 is released when the standard time reaches 10 oclock 30 minutes. As a result, the clock pulses are applied to counter 18 to commence its counting operation at an instant when the standard time reaches 10 oclock 30 minutes.
  • the time display of the watch is matched with the standard time at an instant of IO oclock, 30 minutes and zero seconds.
  • the minute display is advanced one step by the operation of the correction key .14 whereas the counting operation of the clock pulses is commenced in response to the release of the correction key 14, so that it is possible to correct ormatch the time displayed in a unit of seconds at high accuracies by taking the commencement of the minute display as the reference.
  • FIG. 3 shows one example of a signal generating circuit which is used in combination with correction key 14 for supplying a stepping signal to the minute counter 23 when key 14 is operated.
  • the signal generating circuit comprises a delay circuit 31 for delaying the signal from key 14' by a predetermined interval, an inverter 32 to which the output of the delay circuit 31 is applied, and an AND gate circuit 33 supplied with the outputs from inverter 32 and key 14. If the key 14 is not operared, a 1 output signal from inverter 32 is applied to one input of the AND gate circuit 33 and a 0 signal is applied to theother input, so the AND gate circuit 33 will produce a 0 output.
  • the input signal to the other input of the AND gate circuit 33 will be changed to l with the result that the 1 output is applied to counter 23 as a minute stepping signal.
  • the inverter 32 provides a 0 output in response to the 1 output from delay circuit 31, thus completing the operation resulting from the operation of the correction key 14.
  • circuit shown in FIG. 3 may be interposed between a juncture 29 and one input of the OR gate circuit 22.
  • FIG. 3 shows one example of such modified circuit which can also be used in combination with the circuit shown in FIG. 2.
  • the output from key 14 is applied to one input of an AND gate circuit 35 through a delay circuit 34 while at the same time to the other input of the AND gate circuit 35 via an inverter 36.
  • AND gate circuit 35 Upon operation of key 14 as the input to inverter 36 is a 1, the one input to the AND gate circuit 35 is a 0 so that no signal is applied to counter 23. Under these conditions, when key 14 is released, AND gate circuit 35 provides a 1 output because at this time the output from delay circuit 34 is still a 1 signal, and the 1 output from the AND gate circuit 35 is applied to counter 23 as a minute stepping signal. As a predetermined interval elapses under these conditions, the output of delay circuit 34 will be changed to a 0, thus disenabling AND gate circuit 35. I
  • FIG. 5 shows an improved circuit which can obviate this inconvenience, that can reduce the time required for correcting the time display occurring as a result of the operation of key 14 to less than 10 seconds.
  • counter 21 shown in FIG. 2 is replaced by two counters 40 and 41, and an OR gate circuit 42. More specifically, the output from key 14 is applied to one input of AND gate circuit 20 to apply second signals to one input of a lO-step counter 40 at a rate of one per second.
  • Counter 40 operates to apply carry signals to a sixstep counter 41 through an OR gate circuit 42 at a rate of one signal per 10 seconds, and the counter 41 operates to send carry signals to counter 23 at a rate of one signal per minute.
  • the signal from key 14 is also applied to counter 40 as a clear signal and to counter 41 as a stepping signal.
  • AND gate circuit 20 is disabled-to terminate the counting operation of counter40 while at the same time its content is cleared to supply a stepping signal to counter 41.
  • AND gate circuit 20 is disabled-to terminate the counting operation of counter40 while at the same time its content is cleared to supply a stepping signal to counter 41.
  • by releasing key 14 at an instant when the time counted by counter 41 matches with the standard time it would be possible to reduce the interval between the operation and release of the correction key 14 to a maximum of 10 seconds.
  • the second counter was cleared and counters of keys, the first one being used to set a memory device, for example, a flip-flop circuit, to memorize the operation of the first key and the second key being used to reset the memory device.
  • a single key may be combined with a flip-flop circuit such that when the key is operated the flip-flop circuit is set, that when the key is released the flip-flop circuit is reset and that the flip-flop circuit produces orders for operating and releasing the key.
  • the invention can also be applied to analogue display clocks.
  • the electronic driving and counting circuits are incorporated into an analogue display clock the outputs from drivers may be supplied to 60 minute" display elements and 12 hour display elements which are arranged on circles on the dial plate of a watch.
  • a clock device comprising:
  • a second counter to count signals from said signal source and for generating 1 minute stepping sig nals at a rate of one per 60 seconds;
  • a minute counter to count said 1 minute stepping signals and for generating 1 hour stepping signals at a rate of one per 60 minutes;
  • a clock device comprising a time correction key, said first signal being generated when said key is operated and said second signal being generated when said key is released.
  • a clock device comprising:
  • a second counter to count signals from said signal source and for generating 1 minute stepping signals at a rate of one per 60 seconds;
  • a minute counter to count said 1 minute stepping signals for generating 1 hour stepping signals at a rate of one per 60 minutes;
  • a clock device comprising a time correction key, said first signal being generated when said key is operated and said second signal being generated when said key is released.
  • a clock device comprising a clock signal generating circuit for generating a standard high frequency signal; and a frequency dividing counter for reducing the frequency of said standard high frequency signal, said reduced frequency signal being counted by said second counter.
  • a clock device according to claim 1 wherein said first signal is coupled to said frequency dividing counter for resetting said frequency dividing counter.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Electric Clocks (AREA)
US00350201A 1972-04-13 1973-04-11 Clock devices Expired - Lifetime US3817023A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47037234A JPS5219977B2 (fr) 1972-04-13 1972-04-13

Publications (1)

Publication Number Publication Date
US3817023A true US3817023A (en) 1974-06-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
US00350201A Expired - Lifetime US3817023A (en) 1972-04-13 1973-04-11 Clock devices

Country Status (7)

Country Link
US (1) US3817023A (fr)
JP (1) JPS5219977B2 (fr)
CA (1) CA965490A (fr)
CH (2) CH567298A (fr)
DE (1) DE2318224C3 (fr)
FR (1) FR2180068B1 (fr)
GB (1) GB1399443A (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2554192A1 (de) * 1974-12-11 1976-06-24 Ebauches Sa Stelleinrichtung fuer elektronische uhren
US3983690A (en) * 1975-05-19 1976-10-05 Mcsohmer Corporation Digital timepiece having chronometric display
US4020626A (en) * 1974-05-14 1977-05-03 Kabushiki Kaisha Daini Seikosha Electronic timepiece

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50121778U (fr) * 1974-03-18 1975-10-04
JPS5146170A (fr) * 1974-10-18 1976-04-20 Hitachi Ltd
JPS581754B2 (ja) * 1975-09-16 1983-01-12 カシオケイサンキ カブシキガイシヤ 電子時計装置
JPS52129278U (fr) * 1976-03-26 1977-10-01
JPS5354685U (fr) * 1976-10-13 1978-05-10
JPS54112167U (fr) * 1978-01-26 1979-08-07
JPS54122544A (en) * 1978-03-13 1979-09-22 Hitachi Ltd Lighting equipment for elevator cage
JPS5750090U (fr) * 1980-09-05 1982-03-20
JPS57111499A (en) * 1980-12-29 1982-07-10 Seiko Epson Corp Electronic wrist watch with digital display
JPH0518805Y2 (fr) * 1986-08-29 1993-05-19

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3541779A (en) * 1968-03-19 1970-11-24 Corning Glass Works Electronic timepiece
US3576099A (en) * 1969-04-22 1971-04-27 Hamilton Watch Co Solid state timepiece having electro-optical time display
US3668859A (en) * 1969-07-03 1972-06-13 Vogel Paul Time setting device for an electronic clock
US3686880A (en) * 1970-09-04 1972-08-29 Toshihide Samejima Electronically controlled stop watch
US3699763A (en) * 1971-07-06 1972-10-24 Us Navy 24-hour digital clock

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3541779A (en) * 1968-03-19 1970-11-24 Corning Glass Works Electronic timepiece
US3576099A (en) * 1969-04-22 1971-04-27 Hamilton Watch Co Solid state timepiece having electro-optical time display
US3668859A (en) * 1969-07-03 1972-06-13 Vogel Paul Time setting device for an electronic clock
US3686880A (en) * 1970-09-04 1972-08-29 Toshihide Samejima Electronically controlled stop watch
US3699763A (en) * 1971-07-06 1972-10-24 Us Navy 24-hour digital clock

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4020626A (en) * 1974-05-14 1977-05-03 Kabushiki Kaisha Daini Seikosha Electronic timepiece
DE2554192A1 (de) * 1974-12-11 1976-06-24 Ebauches Sa Stelleinrichtung fuer elektronische uhren
US3983690A (en) * 1975-05-19 1976-10-05 Mcsohmer Corporation Digital timepiece having chronometric display

Also Published As

Publication number Publication date
DE2318224B2 (de) 1975-02-13
JPS5219977B2 (fr) 1977-05-31
CA965490A (en) 1975-04-01
CH567298A (fr) 1975-09-30
JPS48104588A (fr) 1973-12-27
FR2180068B1 (fr) 1976-11-12
DE2318224A1 (de) 1973-10-25
FR2180068A1 (fr) 1973-11-23
GB1399443A (en) 1975-07-02
CH536473A4 (fr) 1975-04-15
DE2318224C3 (de) 1975-09-25

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