US3816822A - Amplitude-space converter, more particularly for dynamic display systems on matrices - Google Patents

Abstract

A remote visual indicator of magnitudes includes an amplitudespace converter comprising at least one comparator having a first input receiving a voltage representing a magnitude, a second input receiving a stepwise varying voltage, and an output delivering, at the particular step-value at which the variable voltage attains the magnitude-representing voltage, a signal which is thus applied selectively to a line of same step-value on a display matrix.

Description

United States Patent 1191 Auchapt 1 1 AMPLITUDE-SPACE CONVERTER, MORE PARTICULARLY FOR DYNAMIC DISPLAY SYSTEMS ON MATRICES [75] Inventor: Ren Auchapt, Paris, France [73] Assignee: LEquipment Et La Construction Electrique E.C.E., Paris, France [22] Filed: Aug. 23, 1972 [2]] Appl. No.: 283,211

[30] Foreign Application Priority Data Sept. 28. 1971 France; 71.34781 [52] US. Cl. 340/324 M, 324/122 [51] Int. Cl G01! 13/02 [58] Field of Search... 340/324 M, l72, 343, 324 R; 315/167 TV; 307/235; 328/115, 116;

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EN CODER COM PAR ATOR [111 3,816,822 June 11, 1974 2,612,550 9/1952 Jacobi 340/172 2,688,441 9/1954 M66111 340/172 2,817,815 12/1957 Evans 340/324 R 6/1972 Ngo 340/324 M OTHER PUBLICATIONS LED Display with Inherent Memory by G. C. Georgallis, IBM Tech. Disc]. BulL, Vol. 13, No. 11, 4/71.

Primary ExaminerJohn W. Caldwell Assistant Examiner-Marshall M. Curtis Attorney, Agent, or Firm-McClew and Tuttle [5 7] ABSTRACT A remote visual indicator of magnitudes includes an amplitude-space converter comprising at least one comparator having a first input receiving a voltage representing a magnitude, a second input receiving a stepwise varying voltage, and an output delivering, at the particular step-valueat which the variable voltage attains the magnitude-representing voltage, a signal which is thus applied selectively to a line of same stepvalue on a display matrix.

6 Claims, 2 Drawing Figures DISPLAY umr 2 l AMPLITUDE-SPACE CONVERTER, MORE PARTICULARLY FOR DYNAMIC DISPLAY SYSTEMS ON MATRICES FIELD AND BACKGROUND OF THE INVENTION The technical field of the present invention is that of electrical engineering components, with particular reference to remote visual indicators of magnitudes.

It is possible to use a cathode-ray tube to display a variety of phenomena such as the variations, as a function of time, of some physical quantity translated into a voltage.

However, the use of a cathode-ray tube calls for bulky and heavy auxiliary apparatus, and these drawbacks become additional to those inherent in the tube itself, notably its fragility and bulk.

It is consequently difficult if not impossible to utilize available display systems of this kind on board aircraft, for instance, where the requirements of robustness, low weight and small size are imperative.

The current state of the semiconductor art includes the use of electroluminescent diodes, notably employing arsenic, phosphorus and gallium, and it has been proposed to utilize such diodes to form display matrices by arranging them in rows and columns at the intersection points of two series of conductors extending along these rows and columns.

It is a prime object of this invention to provide means whereby to energize the diodes arranged thus in a matrix, which means utilize lightweight, high-performance electronics. n

This electronic system forms an amplitude-space converter interposed between an input, to which is applied a voltage representing a variable to be displayed, and the inputs to the lines of a matrix.

In one specific form of embodiment of the invention, there is associated, to a series of lines on such a matrix, an electronic system comprising an interface and a secondary decoder, which decoder is connected to the outputs of a pair of latchable transfer storages arranged in series (hereinafter referred to as latches). The first latch is connected to an encoder, forming a binary counter having a last terminal connected to the second latch whereby to transmit a signal thereto only when the binary counter has reached its maximum counting capacity. The counter is controlled by a clock and energizes a primary decoder having an output connected to one of the inputs of a comparator whose other input receives the electrical signal translating the quantityto be displayed and whose output is connected to a control input of the first latch.

Clearly, it would be possible to 'process a second quantity correlated to the first by utilizing an identical system applied to the other family of lines of the matrix in question.

Assuming this second quantity to be time, then a clock may be used in conjunction with an interposed time-voltage translator, for instance.

It is accordingly possible with such an arrangement to effect an amplitude-space conversion since, for any given signal amplitude, there corresponds a counter position and hence a line, namely a column or a row, on the matrix.

The provision of a dual latch between the encoder and the secondary decoder allows storing, in binary form, the value of the signal to be displayed, which signal will be displayed-on the matrix only for the time needed to determine the rank of the next line, whereby the duration of excitation remains independent of the amplitude of the signal to be displayed.

Hence all displayable signals having a period equal to or greater than the conversion or response time of a variety of electronic units are usable and can be made to appear on a flat, lightweight, rugged matrix of electroluminescent diodes, irrespective of whether the matrix employs discrete diodes or diodes forming part of integrated circuits.

In an alternative embodiment, an amplitude-space converter according to the invention is devised with chains of resistors associated to dual comparators.

Applications of the invention are to be found in a wide variety of fields, including non-limitative application to aircraft flight instruments.

BRIEF DESCRIPTION OF THE DRAWING The description which follows with reference to the accompanying non-limitative exemplary drawing will give a clear understanding of how the invention can be carried into practice.

In the drawing:

' FIG. 1 is a block diagram of a display unit according to the invention; and

FIG. 2 is a schematic wiring diagram of an alternative embodiment of a converter with dual comparators.

DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1, there is provided, on a fiat panel 1, a matrix of electroluminescent diodes arranged in criss-crossing lines forming rows and columns, along parallel conductors 2, 3, the two sets of conductors being connected, substantially at each of their intersection points, to the electroluminescent diodes, each of which releases photons whenever its two electrodes are raised to the voltage required for this functional mode of the diode. The diodes have not been shown in detail, for greater clarity in the drawing. If the direction of the sets of conductors 2 and 3 are mutually perpendicular, then the matrix will determine a representation surface based on right-angled coordinates. Any number, equal or not, of rows and columns may be used.

As shown in the graph in the top left-hand comer of FIG. 1, a change in magnitude in this converter system is translated in the form of a voltage V, as a function of time t. The variable voltage V is applied to one of the inputs of a comparator K1. The second input of comparator K1 is connected to the output of an analog binary decoder D1.

A clock H delivering electric pulses in the form of square wave pulses (shown on the middle graph to the left of FIG. 1) feeds a binary encoder C1, having its binary outputs connected to the corresponding inputs of binary decoder D1. Decoder Dl delivers a stepwise voltage, shown, on the graph to the left of FIG. 1.

The binary outputs of encoder Clare further connected to the corresponding inputs of a set of bi-stable latchable flip flops, referred to as a latchable transfer storage" or latch U1 and having a triggering input connected to the output of comparator Kl.

The outputs of the first latch L11 are connected to the inputs of a similar second latch L12 having a triggering input connected to a detector of the maximum capacity of the counter C1.

The outputs of secondary latch L12 are connected to the inputs of a secondary binary/decimal decoder D11, the decimal outputs of which are applied to the companion inputs of an amplifier unit or interface 11, whose output terminals are respectively connected to the line conductors 2, which lines form rows in the example herein considered.

The system hereinbefore described functions as follows.

When the clock H operates, the binary counter C1 activates both the primary decoder D1 (the output of which is the seat of the stepwise voltage) and the primary latch L11. The comparator K1 delivers, on its output, a voltage for triggering the latch L11 when the signal issuing from decoder D1 is equal to or greater than the value of the voltage V existing on the first input of comparator K1 and corresponding tothe value to be displayed on matrix 1.

At the instant when the voltages on the two inputs of comparator K1 become equal, the content of counter vC1 is stored in primary latch L11 and appears at the same time on the outputs thereof.

The binary value stored thus is transferred into secondary latch L12 when the counter C1 reaches the maximum value of its capacity, that is to say when its ultimate triggering output is energized, which in turn corresponds to energization of the triggering input of secondary latch L12 and a reverting of the counter C1 to its original counting position.

At the same moment also, the binary value consequently appears at the output of secondary latch L12 and the appropriate row 2 is energized responsively to secondary decoder D11.

This energization lasts for at least the whole of the time during which counter C1 performs one of its counting cycles. 7

The desired amplitude-space conversion is accordingly achieved since, to a given amplitude of signal V on the first inputof comparator K1, there corresponds a determinate position of counter C1 and consequently a determinate row 2 on matrix 1.

The role of the two latches L11 and L12 is to permit storage, in binary form, of the value of the signal to be displayed. Thus, the time for which a line 2 is energized is independent of the amplitude of the signal .to be displayed.

Any change in this amplitude between two successive scans of counter C1 results in a further selection from the content of counter C1, in a different configuration of latches L11 and L12 (which is likewise stored), and in a further binary decoding in secondary decoder D11 and hence in energization of a different row 2 with a substantially equal energization time.

For the purpose of energizing the column conductors 3, a similar circuitry may be used (using the same clock, for example) to energize in parallel the counter C1 and a further binary counter C21, whose outputs are themselves connected both to a primary binary decoder D21 and a primary latch L21. A further compar' ator K2 has a first input connected to the translator of a second variable V1 to be considered, and a second input connected to the output of the corresponding primary decoder D21.

It is possible in this way to display on matrix 1 the correlation between two variables, independently of time, the interconnection channel to the inputs of conductors 3 likewise comprising a secondary latch L22, a secondary binary/decimal decoder D22 and an interface l22. I

Should it be required merely to represent a timevarying process, the circuitry can be simplified by simply connecting the input of secondary counter C21 di rectly to the output of the detector of the maximum capacity of first counter C1. in this simplified arrangement it is possible to dispense with comparator K2, decoder D21 and latches L21 and L22 and to connect the outputs of counter C21 directly to the corresponding inputs of decoder D22.

These various arrangements allow of simultaneously and synchronously energizing the selected conductors of rows 2 and columns 3 whereby to energize, in pace with the common scannings of counters C1 and C21, the diodes at the intersection points of the energized conductors in question.

Using this image scan rate, which makes use of the persistence of images impressed on the eyes retina, it is possible to provide, on matrix 1 a dynamic displayof the correlative variations of the two variables in question.

In the above-described example, any type of comparator may be used. Alternatively, a network of the type familiary designated as R2R and forming a decoder could be associated to comparators known under the designation type u A 711.

As shown in FIG. 2, such comparators are biased by two chains of identical resistors 5 and 6 in series, which chains are parallel-connected to a source of direct current at a voltage E. Each comparison cell 7 has a first input connected to interconnection means between a resistor 5 of rank n and a resistor of rank (n l), and a second input connected to a junction between a resistor 6 of rank n and a resistor of rank (n 1).

The output of this comparator cell may be connected, directly or not, to a matrix line 1a.

Apart from the ranks of the resistors and the identity of the matrix line, the electrical connections used for the other comparators is as above-described.

The third inputs 8 of these dual comparators are parallel-connected to a conductor (not shown) carrying the voltage V representing the magnitude of the variable to be displayed.

Into each chain are connected N resistors 5 (or 6) equal in number to the number of lines 1a on the matrix and to the number of comparators 7. The voltage across the terminals of each resistor is E/N, where E is the potential applied to the chain. v

Thus each comparator 7 exhibits a sensitivity window equal to EIN for a signal applied to its control electrode.

The comparator which is connected between the resistors of rank (n l) and n in the first chain and between the resistors of rank n and (n l) in the second chain consequently delivers a voltage on its output, for the purpose of energizing the matrix line In connected thereto, when the voltage v on its control electrode assumes a value lying betweenthe ratios En/N and E(n 1)/N, so that one may write:

En N V E(n l)/N Manifestly, the circuitry shown in FIG. 2-could include other interposed components of the kind shown in FIG. 1 should it be desired to enjoy the same advantages of independence between the matrix line energization and the magnitudes of the variables to be displayed, in respect of both the values of such magnitudes and the energization times.

It goes without saying that changes and substitutions could be made in the specific forms of embodiment hereinbefore described without departing from the scope of the invention.

What is claimed is:

1. An amplitude-space converter unit comprising, in combination, at least one comparator having a first input to which is applied a voltage representing the magnitude of a variable, at least one second input receiving a stepwise varying voltage, and anoutput; a display matrix constituted by electroluminescent diodes arranged in lines having respective step values; said comparator output delivering asignal to a line of said matrix having the same step value as that for which the stepwise varying voltage on said second comparator input becomes at least equal to the magnituderepresenting voltage on said first comparator input; a binary/decimal decoder having an output connected to said second comparator input; a decimal/binary encoder having outputs connected to inputs of said decoder, and having an end-of-scan output; a primary latchable storage having inputs connected to the outputs of said encoder and to the inputs of said decoder; a clock connected to the input of said encoder and delivering clock pulses thereto; a secondary latchable storage having inputs connected to corresponding outputs of said primary latchable storage; said primary latchable storage having a triggering input connected to said comparator output; said secondary latchable storage having a triggering input connected to said endof-scan output of said encoder; a secondary binary/- decimal decoder having inputs connected to corre-' sponding outputs of said secondary latchable storage; and interface means interposed between said secon dary decoder and said display matrix and having inputs connected to corresponding outputs of said secondary decoder and having outputs connected to corresponding lines of said display matrix.

2. A converter unit according to claim 1 including 6 two amplitude-space converters respectively connected to the two families of lines, to wit rows and columns, of said matrix.

3. A converter unit according to claim 2, in which said two amplitude-space converters are identical, the first comparator inputs independently receiving voltages representing magnitudes of variables, and said matrix permitting visualization of the correlation between said variables.

4. A converter unit according to claim 3, in which the same clock is used to control the two input encoders.

5. A converter unit according to claim 1, including a set of dual comparators associated to a dual chain of equal resistors provided in equal numbers in the respective chains, which chains are raised to the same reference voltage, two second inputs of each dual comparator being connected between resistors, mutually offset in rank by one unit, in the respective chains, a first input of each dual comparator being connected to a single conductor to which is applied the voltage representing the magnitude of the variable to .be displayed, the output of each comparator being connected to a line on said matrix.

6. A converter unit according to claim 1, in which, in order to represent the variations of a variable solely as a function of time, said matrix has two families of lines forming rows and columns, with one family of lines being energized by said amplitude-space converter and the other family of lines being energized by a second binary/decimal encoder; said second binary/decimal encoder having an input connected to that output of said first mentioned binary/decimal encoder detecting attainment of the maximum capacity of said firstmentioned binary/decimal encoder; a second binary/- decimal decoder having inputs connected directly to the outputs of said second binary/decimal encoder; and second interface means interposed between said second binary/decimal decoder and said display matrix and having inputs connected to corresponding outputs of said second binary/decimal decoder and having output connected to corresponding lines of said other family of lines on said display matrix.

Claims (6)

1. An amplitude-space converter unit comprising, in combination, at least one comparator having a first input to which is applied a voltage representing the magnitude of a variable, at least one second input receiving a stepwise varying voltage, and an output; a display matrix constituted by electroluminescent diodes arranged in lines having respective step values; said comparator output delivering a signal to a line of said matrix having the same step value as that for which the stepwise varying voltage on said second comparator input becomes at least equal to the magnitude-representing voltage on said first comparator input; a binary/decimal decoder having an output connected to said second comparator input; a decimal/binary encoder having outputs connected to inputs of said decoder, and having an end-of-scan output; a primary latchable storage having inputs connected to the outputs of said encoder and to the inputs of said decoder; a clock connected to the input of said encoder and delivering clock pulses thereto; a secondary latchable storage having inputs connected to corresponding outputs of said primary latchable storage; said primary latchable storage having a triggering input connected to said comparator output; said secondary latchable storage having a triggering input connEcted to said end-of-scan output of said encoder; a secondary binary/decimal decoder having inputs connected to corresponding outputs of said secondary latchable storage; and interface means interposed between said secondary decoder and said display matrix and having inputs connected to corresponding outputs of said secondary decoder and having outputs connected to corresponding lines of said display matrix.

2. A converter unit according to claim 1 including two amplitude-space converters respectively connected to the two families of lines, to wit rows and columns, of said matrix.

3. A converter unit according to claim 2, in which said two amplitude-space converters are identical, the first comparator inputs independently receiving voltages representing magnitudes of variables, and said matrix permitting visualization of the correlation between said variables.

4. A converter unit according to claim 3, in which the same clock is used to control the two input encoders.

5. A converter unit according to claim 1, including a set of dual comparators associated to a dual chain of equal resistors provided in equal numbers in the respective chains, which chains are raised to the same reference voltage, two second inputs of each dual comparator being connected between resistors, mutually offset in rank by one unit, in the respective chains, a first input of each dual comparator being connected to a single conductor to which is applied the voltage representing the magnitude of the variable to be displayed, the output of each comparator being connected to a line on said matrix.

6. A converter unit according to claim 1, in which, in order to represent the variations of a variable solely as a function of time, said matrix has two families of lines forming rows and columns, with one family of lines being energized by said amplitude-space converter and the other family of lines being energized by a second binary/decimal encoder; said second binary/decimal encoder having an input connected to that output of said first mentioned binary/decimal encoder detecting attainment of the maximum capacity of said first-mentioned binary/decimal encoder; a second binary/decimal decoder having inputs connected directly to the outputs of said second binary/decimal encoder; and second interface means interposed between said second binary/decimal decoder and said display matrix and having inputs connected to corresponding outputs of said second binary/decimal decoder and having output connected to corresponding lines of said other family of lines on said display matrix.

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