US3443081A - Cascade squarer - Google Patents

Description

May 6, 1969 A. NATHAN CASCADE SQUARER Filed Sept. 12. 1963 Sheet INVENTOR May 6, 1969 A.INATHAN I 3,443,081

CASCADE SQUARER Filed Sept. 12,- 1963 Sheet 5 of 4 FIG. l3

"I F\G |4 I30 I Z l I I III- mew I54 M I4af|so}-|s| J t f 153 4 FIGJE H4 m I R l I Y T lt S -E T RH i ,I I v t H- m R I N I INVENTOR} H ER I 1 MM. M I z s 4 5 t May6,1969 AJNIATHAN' 3,443,081.

CASCADE VSQIUAREYR med Sept. 12, 1963 Sheet I 1 r 4 ,mcsn

Henle- XHW W v INVENTOR United States Patent This invention relates to squarers, id to devices having a transfer characteristic corresponding to a square law. A transfer characteristic denotes thecurve obtained' by plotting the, values of an output. function; as ordinate against-the value ofan input variable las abscissa; I 1

Squarers are of use i. inconnection, with computing machines, for example. They are also frequently employed in electronic circuits for the shaping of wayeforms, In analog computers, the variables are-frequently represented inv the form of continuously variable electric Great Britain, Novt 13, 1962,

Patented May 6, 1969 FIGURES 17-19 are block' diagrams relating tove'xamples of digitalembodiments of the invention; and

where N is a constant .rflis restrictediojheinterval voltages, or potentials. An analog squarer produces an output voltage which is proportional totthesquare of the instantaneous .value of an input-voltage. In digital com? puters a number may be reprment-edin binary form, for example, accor'ding to one of many, representation schemes; A squarer produces a second number' which is equal to the square of the proximation thereto;

It is an object of. this invention toprovide function generators producing an output signal representing. the square of the instantaneous value of an input signal,

given number, or is an ap It is another object of the invention to provide a de;

vice, which, when used in conjunction with a squarer of given accuracy, provides, an output signal 'representing the square of'an input signal with an accuracy that is greater than the accuracy of said squarer.

- It is a further object of the invention'jto provide aItime sharing, or iterative, squarer. I I I I A yet further object of the invention is the provision of a digital squarer. I I Further objects and advantages of the invention will become apparent from the following description takenin conjunction with the accompanying drawingsin which:

FIGURES 15 are plots of functions relatedto embodiments of the invention; v v I FIGURES 6 and 7 are schematic diagrams of cascade stages used in embodiments of the inventioncj IQ 1' FIGURE 8 is a schematic diagram of an analog embodiment of the invention wherein Z ener diodes are used for the provision of signal shift;' I I v FIGURE 9, is a schematic diagram ofa'n embodiment of an analog squarervaccording' to the invention using resistive signal s hi ftme'ansi I I FIGURE 10 is a schematic diagram of an embodiment of the invention forthe provision of a square output signal and its inverse;

FIGURE 11 is a schematic diagram relating to a t wo- I stage analog squareraccording to the invention;

FIGURE 12 relates to a similar two-stage embodiment of the invention, in which .interstage impedance converters are eliminated; I l .t FIGURE 13 is a schematic diagram of an iterative, or time sharing, embodiment of. an analog squarer according to the invention; I I FIGURE 14 relates to a, time sharing embodiment. of

the invention for the production of three square functions from respective input signals; f v i I FIGURE 15 relates to the switchingtscheme o-f the embodiment of the invention corresponding to. FIGURE 13; FIGURE 16 is a plotof a voltageused in the embodiment of FIGURE 13;

analog embodiments of theinventionf' .I @a al e i 'd t r t q i ar e t i ,1 1 ea/Nu FIGURE -20 is aischematic diagram relating to. other Thus y is an approximation to s. x i-( A )N+ /2 (M: )N approximates s within an error of :(M; )N, i.e. with a maximal fractional error of i( A).

If the value of x +(-%)N is exact but s has a fractional error e, the fractional'error caused thereby in s is only A)e because, from Equations 3 and 10, the range of s is four times the range of s;'. II

s is the same function of x as s is of x. s can therefore be expanded in a similar manner.

Thus, s +c /2( A) N approximates s with a maximum fractional error of :L-( /2)(%)"; s and 1 approximate s, except for an additive constant; and if s,,' is replaced by'an expression having a fractional error e with respect to the range of .r,,', the fractional error caused thereby to s is equal to only )E.

The functions x, x, x y x y x and y are plotted as functions of x in FIGURES 1-4. They are seen to be of triangular" shape.

y Equation 18, can be produced from x by maximum selection, since Similary, y can be produced by minimum selection, since Alternatively, y; can be produced from y, by a change of sign.

It is also possible to obtain diflerent, but equivalent, expressions for y, and 2: as will now be explained in connection with FIGURE 5. Lines a-h have the following equations:

A comparison of FIGURES 2 and shows that x; and y, can be written as follows:

( y1= f) r= tc 3) Comparing FIGURES 3 and 5 it follows that (33) y =min(max(a, g), max(c, e))

and from FIGURES 4 and 5 follows ya= g),

m x( f),

It is thus a simple matter to express in similar form the functions 1:, and y, in terms of operations of maximum and minimum selection of functions of the form where m, and n assume suitable values.

The invention provides means for the production of a function representing s, Equation 20, or an approximation thereto, as given, except for an additive constant, by s,, or t,,, Equations 21 and 22, respectively.

FIGURE 6 is a schematic diagram of one example of a voltage analog stage of embodiments of the invention, wherein voltages representing x, and x are produced from an input voltage representing x. Voltage x is received at terminal 1, which is the input terminal. Sign changer 2 produces therefrom at line 4 voltage x, and voltage x is also present on line 3 which is connected with terminal 1. Diodes 5 having a common output connection at terminal 7 from which current is withdrawn through a resistor connected to negative potential means at select at terminal 7 the larger of voltages at and x which are received by the input connections of the diodes. This voltage is transferred through diode 6 to the input terminal of sign changing adder 9. Diode 6 is held perpetually conductive and is inserted in the circuit in order to have an equal number of forward and backward pointing diodes in each signal path from an input terminal to the output terminal. Such an arrangement reduces drift due to temperature changes and simultaneously cancels diode offset voltages. A second pair of diodes, of reversed polarity, selects the smaller of x and x and causes this voltage to be transferred through compensating diode 6 to an input terminal of sign changing adder 9'. In accordance with Equation 4, voltages y and y are thus present at input terminals of adders 9 and 9', respectively. Adder 9 simultaneously receives at another input terminal, 8, voltage /2N thus producing at its output terminal 10 the voltage by Equation 5. Input terminal 12 of adder 9 receives voltage /zN and voltage x is thus produced at terminal 11, the output terminal of sign changing adder 9. FIGURE 6 is not, in this form, advantageous, and is only given in order to illustrate means for the production of x and x from x as input voltage. In practice, it is simpler to produce x for example, as in FIGURE 6, and to produce x therefrom in a sign changing adder of unity gain.

FIGURE 7 is a schematic diagram of another embodiment of a stage of devices according to the invention. Voltages x and x are received by input terminals 1 and 13, respectively. Selecting diodes produce therefrom at their common output terminal 14 voltage Sign changing adder of unity gain, 15, receives y; at terminal 14 and voltage N at terminal 16 and produces at output terminal 17 the voltage y +N. Thus, terminal 14 is at the voltage x AzN=y and terminal 17 is at the voltage x +%N=-y /2N+ /2N=-y +N; i.e. except for a rise in the voltage level by /2N, voltages x and x are produced at the output terminals of this circuit.

FIGURE 8 is a schematic diagram of an example of a voltage analog squarer according to the invention. Voltage x is received at input terminal 1. Voltage x is produced therefrom in unity gain sign changer 2 at line 4. Diode selection circuits produce from x and x at lines 18 and 19 voltages y and y' respectively, in the same manner as explained in connection with FIGURE 6. Current 1 is withdrawn by current generator 23 from the series combination of Zener diode 21 and resistor 20 which is connected betwen line 18 and impedance converter 25. The latter has a high input impedance and a low output impedance and causes substantially all the current i to be withdrawn from diode 21. The voltage at line 18 is lowered by the voltage drop in the Zener diode and -by the voltage drop cause by current i in resistor 20. Resistor 20 is provided in order to adjust the voltage drop in 20, 21 to exactly its required value of /2N, in order to obtain voltage x =y -%N at line 22. Voltage x is similarly produced from y, at line 19 by adding thereto the combined voltage rise in a small resistor and a Zener diode. Impedance converter 26 transfers x =y /2N to line 28.

Diodes are used for selecting the larger of x and x; at their comomn output connection 29, where voltage max(x x )=]x |=y is thus produced, cf. Equation 11. Uomponents 30-33 are connected to form a half squarer, 1.e. a squarer adapted to receive nonnegative input voltages and to produce therefrom an output voltage corresponding with the square thereof. 30 are resistors, used for interpolation, 31 are diodes and 32 is a constant current source. Terminal 33 is connected to a constant potential source. Such a half squarer is described in detail in my paper published in IEEE Transactions on Electronic Computers, (New York), October 1963. The half squarer produces from voltage y at terminal 29 the voltage (l/N)y at its output terminal 34 whenc it is transferred through imped-ance converter 35 to one of the resistors 37. Resistors 37 have a common output connection at terminal 38 whereat the output voltage of the cascade squarer is produced. For this purpose the three resistors receive voltages (1/N)y y atline 27, and a constant voltage at terminal 36 to produce a linear combination thereof at terminal 38, such that this terminal is at a voltage proportional to in accordance with Equations 20, 22, 23, 24,v where n=1, and Equation 11.

In one example of the embodiment of the invention corresponding to FIGURE 8, N=50 volts, thevoltage shift in resistor 20 is 1 volt and 21 is a 24-volt Zener diode, so that the totalvoltage shift between lines 18.and 22 is 25 volts. The shift between lines 19 and 24 is likewise. 25 volts, but it is of opposite polarity. The impedance converters have unitygain. Terminal 33 is grounded andthus held at zero potential. 1 1

In the squarer of FIGURE 8, the device between the input terminal and up to lines 22 and 24 is called a convert ing stage, producing the converted signals x and x from x by a process of selection and signal shift operating on x and x. The circuit up to terminal 29 may be termed another converting stage, cascade connected to. the first stage. It produces y another converted signal. Finally, a squarer is cascade connected to the second converting stage. Alternatively, the device as from lines 27 and 28, i.e. the part of the circuit including the second converting stage and the half squarer, can be regarded as a full squarer, which is cascade connected to the first converting stage of the cascade squarer.

As an alternative way of producing s in a circuit similar to that of FIGURE 8 the following changes are made: The combining resistor connetced to terminal 36 is omitted. The voltage levels at terminals 27 and 34 are both raised by N/ 8 volts. This is achieved by the use of different shift Zener diodes in the first stage of the invention, so as to raise the voltages at lines 22 and 24 by N 8, simultaneously applying voltage N/ 8 to terminal 33 of the squarer. The two remaining resistors 37 thus sum the voltages x +N/8 and (1/N)y2 +N/8 and produce therefrom, provided they have equal resistance, the output voltage /2(x -I-N/8+(1/N)y --l-N/8)=%(y %N i'= as required.

Another example of the invention will be described in connection with FIGURE 9 which is a schematic diagram of a cascade squarer using resistive signal'shift and eliminating, by a special arrangement of current sources, the need for at least one of the impedance converters. Voltages y and -y are produced at lines 18 and 19, respectively, as before. Voltages x and x are produced at terminals 42 and 43, respectively, when current i flows through shifting resistors 40 and 41, respectively. For this purpose current 2i is injected into terminal 43 and current i is withdrawn from terminal 49 which is the common junction of selection diodes 45 and 46, selecting the larger of x and x and thus producing voltage y at terminal 49. If x is positive, diode 45 conducts and diode 46 does not conduct. Therefore, assuming that squarer 48 does not withdraw any current from terminal 49, current i flows through resistor 40 producing there the required voltage dropof N/2. On the other hand,

if x is negative, diode 45 is off and diode 46 conducts so that current i is withdrawn from diode 46 and the current flowing from current generator 44 into resistor 41 is equal to 2ii=i, producing the required voltage rise of N/ 2. 48 is a half squarer having infinite input resistance so as not to withdraw any current from terminal 49'. It produces a voltage proportional to y at terminal 50 from its input voltage y at terminal 49. Adder 53 combines in a linear manner voltage y at terminal 18, the square voltage proportional to 3' at terminal 50, and a constant voltage applied at terminal 52, to produce an output voltage equal to Ax -l-B where A and B are constants, depending upon the gain of adder 53 and the voltage at terminal 52. Note that, except for an additive constant, s is proportional to y +'(1/N )y as noted before.

FIGURE 10 is a schematic diagram of one embodiment of the invention for the simultaneous production of one voltage equal to Ax and another equal to its inverse, without the use of a sign changer to reverse the sign of Ax Voltages x and x are produced as in FIGURE 8 at terminals 22 and 24, respectively, except for the use of voltageshifting resistor 40 and 41 which produce the whole voltage shift of :N/ 2. x and x are transferred to terminals 27 and 28 through impedance converters 25 and 26, respectively. Squarers 60 and. 61 produce from x and x respectively, output voltages proportional to x andx where the constant of proportionality is positive, at terminals 62 and 63, respectively. Adder 66 combines in a linear manner voltages at terminals 22 and 62 and a constant voltage applied at terminal 64, to produce Ax at terminal 68. Adder 67 similarly combines the voltages at terminals 24, 63 and 65-, the latter receiving a constant potential, to produce at terminal 69 the voltage Ax FIGURE 11 is a schematic diagram of an example of a circuit according to the invention for the production of voltages y, and x and their inverses, where i=1, 2, 3, from x and x as input voltages. Linear combinations of x x and x;,, or of y y and y approximate s, except for additive constants, according to Equations 20-28. In particular, with n=3, Equations 21 and 22 become respectively and thus an adder can produce from the voltages produced in the device according to FIGURE 11 an approximation to s, provided that a suitable constant voltage is added thereto. In particular is an approximation to s having a maximum fractional error of :l/l28.

Voltages y ,y x x are produced at terminals 18, 19, 22, 24, respectively as in FIGURE 10, and voltages x and x are transferred to terminals 27 and 28 through impedance converters 25 and 26, respectively. A similar second stage produces from x and --x; at terminals 27 and 28, voltages y y x 'x at terminals 4 9, 82, 85, 86, respectively. The only difference of the second stage as compared with the first is in that the voltage shifts are only one half of thosein the first stage. Thus the resistances of resistors 83 and 84 are equal to one half those of resistors 40 and 41 and the produced voltage shifts are :(MQN. The second stage comprises selection diodes 45 and 46 having a common output connection at terminal 49, selection diodes and 81 having a common output connection at terminal 82, resistors 83 and 84 and current generators 87 and 88 which withdraw or inject, respectively, currents i from terminals or 86. Voltages x and -x are transferred to terminals 91 and 92 through impedance converters 89and 90, respectively. In the third stage, selection diodes 93 and 94 produce at terminal 97 voltage y =]x while current i is withdrawn from terminal 97 by current generator 99. Similarly, diodes 95 and 96 in conjunction with current generator produce at their common connection 98 the voltage -y FIGURE 11 is a schematic diagram of a still further embodiment of the invention for the production of voltages y y which when combined, yield an approximation to s, as explained above. This example uses a cascade 7 scheme, wherein each stage employs only one signal shifting means. The scheme is as follows: First, y and y are produced from x and x. y is next shifted to produce -y +N= x /2N. Thus there are now available the voltages y =x +V2N and x /2N, which represents x and x respectively, but are produced at a voltage level /2N volts higher. Maximum and minimum selection produces therefrom min(x /zN,x /zN)=]x l+%N=y2+%N respectively. Next y /zN is shifted to produce There are thus available voltages y2= 2+ and Maximum selection next produces therefrom the voltage and a further voltage shift produces therefrom the voltage y +(%)N(%)N=y This process can be continued in an evident manner to yield y y In the circuit of FIGURE 12, y and -y are produced by selection from x and x at terminals 18 and 19, respectively. Zener diode 110 produces a voltage shift of /2N to yield x +/zN at terminal 111 into which current generator 113 injects current 2i. Current generator 112 simultaneously withdraws current 2i from terminal 18. Selection diodes 114 and 115 produce at their common connection 118 voltage ]x l+ /2N=y /2N. Diodes 116 and 117 similarly produce at their common connection 119 voltage ---y +/2=x +(%)N. Current generator 125 injects into terminal 119 current 2i. The voltage at terminal 118 is shifted /2N volts by means of resistor 120, to yield at terminal 121 the voltage Next, maximum selection is carried out by means of diodes 123 and 124 to produce at their common terminal 126 the voltage lx |+(%)N=y +(%)N, from which,

'finally, resistor 127 in conjunction wth current generator 129 which withdraws current i from terminal 128 and thus also from resistor 127 which is connected thereto, deducts the voltage (%)N, to produce at terminal 128 the voltage y It is assumed that terminal 128 is not loaded, so that indeed all the current withdrawn from 128 by generator 129 is also withdrawn from resistor 127.

It remains to be shown that the currents in the device according to FIGURE 12 do indeed provide the required voltage shifts in the shifting resistors. Current i is withdrawn from terminal 128 by current generator 129. This current always flows through resistor 127, under the assumption of no load. Now, either diode 123 or diode 124 is conductive (on), the other being non-conductive (off). If diode 123 is on, i flows through diode 123 and resistor 120, causing therein the required voltage drop; i also fiows through either diode 114 or diode 115.

Of diodes 114-117, either 114 and 117 are on and 115 and 116 are off, or 114 and 117 are on and 115 and 116 are off. If diode 114 is on, diode 116 is off and current i, originating in current generator 129 as well as current 2i originating in current generator 112 are withdrawn from terminal 18, and a current of strength flows through one of the diodes receiving x or -x and connected to terminal 18. If diode 115 is on, diode 117 1s oif, current i originating in current generator 129 is withdrawn from terminal 111 and current 2i is simultaneously injected into terminal 111 by current generator 113. Thus current 2ii=i flows through Zener diode from cathode to anode and makes it operative, and through either of the input diodes connected to terminal 19 and receiving x and x, respectively.

On the other hand, if diode 124 is on, diode 123 is off, current i originating in current generator 129 flows through resistor 127 and diode 124 and is withdrawn from terminal 119 into which current generator injects current 2i. Thus current 2ii=i flows from anode to cathode through either diode 116 or diode 117. If diode 116 is on, diode 114 is off and current i is injected into terminal 18 by current generator 112. Thus a net total of current i is withdrawn from terminal 18 and must flow through one diode connected to 18 and receiving input voltages x and x, respectively. If diode 117 is on, diode 115 is off, and current i is injected into terminal 111 through diode 117, current 2i is injected into terminal 111 by current generator 113. Thus a net total current of strength 3i flows from cathode to anode of Zener diode 110 and through one of the input diodes connected to terminal 19.

Because the voltage drop of a diode when it is on, and of a Zener diode when traversed from cathode to anode, is substantially independent of the value of the current flowing through it, it follows that the device of FIGURE 13 is operative correctly in all possible states.

FIGURE 13 is a schematic diagram of an example of a time sharing, or iterative, embodiment of the invention. In this example, voltage x is received and voltages y /2y A )y and (M; )y., are produced successively in one converting stage according to the invention. For this purpose, voltages /2x and '/2x replace x and x, respectively, during a second. computing interval. i(%)x replace these during a third interval; and i(%)x re place them during the fourth interval. i is subsequently formed and stored after addition thereto of cf. Equations 20, 22, 24, 28, with n=4. The fractional error of the result represents s to within an error of i.e. to within a fractional error :Vz (M0 In the example of FIGURE 13, voltage x is received at terminal 130 of integrator 131. 131 is used as a sign changer, or a storage element, according to the position of its change-over switch 132, which, in fast embodiments of the invention, is implemented as an electronic switch. If switch 132 is at S, integrator 131 is a sign changer of gain 1; if it is at H, it stores its output value and maintains or holds the voltage at its output terminal 133; if at R, or reset, a new value of voltage can be established at output terminal 133. During the first computing interval, switch 132 is at S, and voltage x is produced at terminal 133. x is transferred through switch 134, at R during this first interval, to line 135. Unity gain sign changer 136 simultaneously produces from x voltage (-x)=x on line 137. Voltages x and x are received by selection diodes 138 to produce at their common terminal 139 voltage y which is transferred to line 140. Integrator 142 is connected to line 140 and to terminal 141. Terminal 141 receives, during the first interval voltage E. Integrator 142 is in state R during this interval and thus operates as a sign changing adder. It is adapted to produce from E and 1 the voltage /2x /2(-y /2N) at terminal 143.

During the second computing interval, integrator 131 is in state R and integrator 142 is in state H, while switch 134 is also in state l-l. Thus Vzx is transferred to line and /2x is produced on line 137, causing the production of y on line 140. Simultaneously, the voltage received at terminal 141 is changed to -(%)E causing integrator 131 to produce the voltage (%)x;; at terminal 133.

Similar third and fourth intervals follow, the switching sequence of integrator 131 being shown graphically by curve I, FIGURE 15, and that of both integrator 142 and switch 134 by curve II thereof, while the voltage at terminal 141 is (%)E during the third and )E during the fourth intervals, as plotted in FIGURE 16, resulting in the production of (A )y and /s)y on line 140 during the third and fourth intervals, respectively.

The switching sequence of integrators 131 and 142 as well as of switch 134 during the fifth and sixth intervals are of no consequence. FIGURES 15, I and II, show a possible sequence.

Integrator 145 receives the voltage at line 140. Its switching sequence is plotted in FIGURE 15, III. During the first four intervals it is in the I (integrate) state. Assuming intervals of equal duration, the voltage thus produced at the end of the fourth interval at output terminal 146 of integrator 145 is proportional to t.; (cf. Equation 22 with n=4). During the fifth intervalintegra tor 145 is in the H position, holding the same voltage which it assumed at the end of the fourth interval. During the sixth interval it is in the reset, R, state, being reset to zero.

Integrator 147 receives at one input terminal the voltage of terminal 146 and at terminal 148 a constant voltage. Its switching sequence is shown graphically in FIG- URE 15, IV. It holds the same voltage during the first four intervals. During the fifth interval it is in the reset position, producing from the voltage at terminals 146 and 148 at output terminal 149 an output voltage proportional to t /2-(%) Nd which, as noted above, represents s to within a small error. This voltage is held during the following five intervals.

After six intervals a new computing cycle starts, the seventh interval being identical with the first. This new cycle operates on the new value of variable x and produces a corresponding value for s at terminal 149.

In FIGURE 15 the letter t denotes the time; the unit of measurement being the computing interval.

The device can be used in an evident manner to produce the squares of two or more input voltages. For each square function a separate integrator 147 is required and switching proceeds in successive computing cycles in order to receive the associatedinput variable and to feed the result of computation into the associated integrator corresponding to 147.

FIGURE 14 is :a schematic diagram showing the switching of input voltages and of holding integrators required if three square functions, corresponding with the three input voltages x x x are to be produced in the circuit of FIGURE 13. The three holding integrators 147, 150, 152 replace 147. The corresponding output terminals are 149, 151, 153, respectively. 146 is the output terminal of integrator 145, FIGURE 13, and 130 is the input terminal of integrator 131. Switching occurs once every computing cycle. Thus x x x are received by terminal 130 in succession and the output voltage of the cascade squarer is routed through'terminal 146 and switch 154 to integrators 147, 150, 152, in succession, and in synchronism with the switching of the input voltages.

An alternative method of carrying out the invention consists in applying a constant voltage -E at terminal 141, FIGURE 13, and using computing intervals of unequal duration. The second, third and fourth intervals are, in this instance, A, /i A,; times the duration of the first. Integrators 131 and 142 have four times the gain described above, when in state R, so that voltage -2x is produced at terminal 143 from y on line 140' during the first interval, causing the production of 23 on line 140 during the second interval, followed by 4y and 8y during the third and fourth intervals, respectively.

10 Integrator produces from y 2y 4y;.,, 8%; on line 140 a voltage proportional to In fast embodiments of the invention according to FIG- URES l3 and 14, all switches are electronic switches, and no mechanical contact devices are involved.

It is by no means an essential feature of the invention that variables be represented as continuously variable voltages. Analog embodiments of the invention can use representation of variables in the form of currents or in the form of mechanical quantities, for example. Any representation permitting the implementation of the operations of maximum and/or minimum selection, signal shift and change of sign, as well as addition, can be used in order to carry out the invention. Moreover, variables need not be represented in analog form, but may be represented in digital form as will now be described in detail by way of example.

Digital devices for the performance of the operations of signal shift, signal storage, change of sign and addition are of the prior art. FIGURE 17 is a flow diagram showing the organization of a binary squarer according to the invention. The value of the quantity N, as defined in Equation 2, is taken as unity and x is limited to the interval 1 x 1. Number representation is, for example, in a twos complement manner using m bits, or digits.

The number x is received by block 161 which produces the number x and selects the larger of x and x thereby producing the number y =|x|. y, is transferred to block 162 where /2 is deducted therefrom resulting in x x is transferred to block 163 where it is stored. x is simultaneously transferred to block 161 where x is produced and y =|x is selected. y is transferred to block 162 where- /2) is deducted from it to produce x which is transferred to store 163, multiplied by /2, and the result, /zx added to the number already in store 163. Multiplication by /2 is simply carried out by a shift one digit to the right. Simultaneously x is received by block 161 and the process continues. In general, at the beginning of the ith interval, x is received by block 161, y, is produced therein and transferred to block 162 wherein /2 is deducted therefrom to produce x and x, is multiplied by /z) the result, i.e. /z) -x being subsequently added to the number already in store 163. Thus, after n intervals, the number in store 163 is equal to s,,, Equation 21. s represents s, being equal to s (c /2 to within an error i /hw ic n Thus, knowing the error that can be tolerated, the number of required intervals can be determined. If s is required, it is merely necessary to add to it which is a constant for a given n.

FIGURE 18 is a block diagram of a similar embodiment of the invention. The only difference is the transfer of 3 1': 1, 2, n; to store 163 where the quantity t Equation 22, is formed after n steps.

FIGURE 19 is a block diagram of an example of the invention operating according to the scheme of FIGURE 18, but shown in gerater detail. In this example both x and its inverse are received by block 164, which transfers the nonnegative thereof to block 165 and the other quantity to block 166. Since y =|x[, the quantity in block 165, is thus y and y is in block 166. y is received by block 167 wherein V. is deducted from it. Simultaneously, y

is received by block 168 and /2 is added to it. Thus x and x are produced in blocks 167 and 168, respectively. y is simultaneously received by store 163. During the next interval, x and x are received by block 164, y and 2 are transferred to blocks 165, 166, respectively, /zy is added to the number in store 163 and 1 1 simultaneously (/2 is deducted from y in block 167 and /2) is added to -y in block 168, to produce x and -x respectively. Thus the process continues, to yield, after 11 steps, the quantity t in store 163.

FIGURE 20 is another example of a voltage analog embodiment of the invention in which the function y is produced according to Equation 34. FIGURE 20 is a schematic diagram of a circuit for the production of functions a, b, c, d, e, f, g, h, showing in detail means for the production of function a; and also showing means for the production of y )N; from which y is readily produced by the addition of (MUN. y and y can be similarly produced, according to Equations 31 and 33, and a linear function of y y and y can be formed according to the disclosure of this invention, to approximate the square function s.

Potentiometers 170 and 171 are fed with voltages x, x and D, -D, respectively, where D is a constant voltage. Resistors 172 and 173 are connected to the adjustable contacts of said potentiometers and produce at their common connection 174 a linear combination of x and a constant, according to the equation a=x+ /2N. Voltage a is transferred through impedance converter 175, having a high input impedance and a low output impedance, to line a, FIGURE 20. Similarly, voltages b, c, d, e, f, g, h are produced on the lines with corresponding designations. Two diodes select at their common output terminal 176 the larger of the voltages on lines a and It so that the voltage of terminal 176 is max(a, h). Similar diode pairs produce voltages max(b, g), max (0, f), max(d, e), respectively. The four voltages thus produced are received by four diodes so connected as to produce at their common connection 177 a voltage equal to the smallest of the four voltages. The voltage thus produced at terminal 177 is equal to min(max(a, h),max(c, f),max(b, g),max(d,e))

which, by Equation 34, is equal to y A )N.

Although this invention has been described and illustrated in detail, it is to be clearly understood that this is by way of illustration and example only and is not to be taken by way of limitation.

What I claim is:

1. A cascade squarer for the production of an output quantity representing the square of a variable, comprising first and second input means for receiving first and second input quantities representing said variable and its inverse, respectively; a first stage connected to said input means for producing by a process of selection and shift of said input quantities a first converted quantity corresponding with a first approximation of said output quantity; means responsive to said converted quantity for producing therefrom at least one further quantity such that a linear function of said first converted quantity and said further quantity corresponds with an improved approximation of said output quantity; and linear combining means arranged to receive said first converted quantity and said further quantity for producing said output quantity.

2. The squarer as claimed in claim 1, wherein said further quantity producing means is adapted to produce said further quantity such that a linear function of said converted quantity and the square of said further quantity represents said output quantity.

3. The squarer as claimed in claim 1, wherein said further quantity producing means includes squaring means for the production of said further quantity.

4. An analog cascade squarer comprising the device as claimed in claim 1, wherein said quantities are represented in the form of analog signals.

5. The device as claimed in claim 4 and including means in the first stage thereof for producing the inverse of said first converted quantity; said further quantity being produced from said first converted quantity and its inverse.

6. The device as claimed in claim 4, wherein said analog signals are in the form of electric potentials.

7. A cascade squarer for the production of an output quantity representing the square of a variable comprising input means for receiving an input quantity representing said variable; means connected to said receiving means for producing a first converted quantity corresponding with a first approximation of said output quantity; means adapted to produce from said input quantity a further quantity which is a function of said variable, such that a linear function of said first converted quantity and said further quantity corresponds with an improved approximation of said output quantity; and linear combining means arranged to receive said first converted quantity and said further quantity for producing said output quantity.

8. The squarer as claimed in claim 7 including means for producing a plurality of converted quantities corresponding with respectively, y being said first converted quantity, wherein r=y1( -N n is an integer greater than unity and x is said variable, x being said further quantity said combining means arranged to receive said converted quantities.

9. An analog cascade squarer wherein variables are represented in the form of analog signals capable of assuming a continuous range of values, including the device as claimed in claim 8 wherein n stages are connected in cascade, the ith whereof adapted to produce a signal representing y,.

10. An analog cascade squarer including the device as claimed in claim 7 wherein said quantities are represented in the form of analog signals capable of assuming a continuous range of values, adapted to produce said output quantity to represent the square of the instantaneous value of said variable.

11. A cascade squarer for the production of an output quantity representing the square of a variable 2:, comprising input means for receiving an input quantity representing said variable x; a first stage connected to said receiving means including means adapted to shift said input quantity and selection means responsive thereto and adapted to operate upon a quantity and its inverse for selecting one thereof having a predetermined magnitude relation with respect thereto, for producing a first converted quantity corresponding with |x| /2N; wherein N is a positive quantity means adapted to produce from said input quantity :1 further quantity such that a linear function thereof and of said converted quantity is an approximation of said output quantity; and linear combining means arranged to receive said first converted quantity and said further quantity for producing said output quantity.

12. The squarer as claimed in claim 11, wherein said further quantity producing means is adapted to produce said further quantity so that it corresponds with the modulus of said first converted quantity.

13. The squarer as claimed in claim 11 including means for producing a plurality of converted quantities corresponding with respectively, where n is an integer greater than unity and x =x; said combining means arranged to receive plural said converted quantities.

14. An analog cascade squarer wherein variables are represented in the form of analog signals capable of assuming a continuous range of values, including the device as claimed in claim 13, wherein n stages are connected in cascade, the ith whereof adapted to produce a signal representing x 15. An iterative cascade squarer comprising the device as claimed in claim 13 and including means for storing said converted quantity corresponding with x, produced during a first computing interval; means adapted to replace said input quantity corresponding with x by said quantity corresponding with x to cause said first stage to produce a quantity corresponding with x means adapted to cause the repetition of said process of producing converted quantities n times to cause' the successive production of converted quantities corresponding with x x x 16. The squarer as claimed in claim 15 wherein said quantities are represented in the form of analog signals capable of assuming a continuous range of values.

17. The device as claimed in claim 16 wherein said repeated process is arranged to include a sequence of intervals of decreasing duration.

18. An analog cascade squarer for the production of an output signal representing the square of a variable, comprising input means for receiving an input signal representing said variable; a first stage connected to said input means for producing by a process of signal shift, change of sign, and signal selection a first converted quantity corresponding with a first approximation of said output signal; squaring means responsive to said converted signal for producing a further signal such that a linear function of said converted signal and said further signal corresponds with an improved approximation of said output signal; and combining means arranged to receive said converted signal and said further signal for producing said output signal.

19. The device as claimed in claim 18, wherein said signals are in the form of electric potentials.

20. A generator for the production of an output quantity corresponding with a triangular transfer characteristic represented by a repeated triangular wave, comprising input means for receiving an input variable x representing said variable; and including n+1 cascade connected circuit means the first thereof connected to said input means wherein the ith of said circuit means n+1; is adapted to produce by a process of signal shift, change of sign, and signal selection a quantity corresponding with 1= r and N; is a predetermined quantity; such that said quantity i=1,2, n+1; n is a positive integer, corresponding with y represents said output quantity.

where References Cited UNITED STATES PATENTS 3,100,839 8/1963 Nathan et al 235-197 3,120,605 2/1964 Nathan et a1 235-197 MALCOM A. MORRISON, Primary Examiner. J. F. RUGGIERO, Assistant Examiner.

U.S. Cl. X.R. 235-194; 307-229 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No 3 ,443 ,081 May 6 1969 Amos Nathan It is certified that error appears in the above identified patent and that said Letters Patent are hereby corrected as shown below:

Column 3 line 1 "y should read y line 10 should read e line 36 before "x" insert Column 4 line 15 should read line 63 comomn" should read common Column 5 line 37 "connetced" should read connected line 48, "+s{=1/2s" should read +si)=l/2s Column 7 line 6 "represents" should read represent Column 10 line 64 "gerater" should read greater line 74,

"- should read y Column 12 line 48 the semicolon should appear as a comma; line 49 "quantity" should read quantity; Column 14 line 9 cancel line 10 cancel "n+1 lines 16 and 17 "and N; is a predetermined quantity; such that said quantity i=1 ,2 n+1; n is a positive integer, corres-" should read i=1 2 n+1; n is a positive integer, and N is a predetermined quantity; such that said quantity corres- Signed and sealed this 14th day of April 1970.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. WILLIAM E. SCHUYLER, JR. Attesting Officer Commissioner of Patents

Claims (1)

1. A CASCADE SQUARER FOR THE PRODUCTION OF AN OUTPUT QUANTITY REPRESENTING THE SQUARE OF A VARIABLE, COMPRISING FIRST AND SECOND INPUT MEANS FOR RECEIVING FIRST AND SECOND INPUT QUANTITIES REPRESENTING SAID VARIABLE AND ITS INVERSE, RESPECTIVELY; A FIRST STAGE CONNECTED TO SAID INPUT MEANS FOR PRODUCING BY A PROCESS OF SELECTION AND SHIFT OF SAID INPUT QUANTITIES A FIRST CONVERTED QUANTITY CORRESPONDING WITH A FIRST APPROXIMATION OF SAID OUTPUT QUANTITY; MEANS RESPONSIVE TO SAID CONVERTED QUANTITY FOR PRO-

Images