US3812491A - Raster-scanned display devices - Google Patents

Raster-scanned display devices Download PDF

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US3812491A
US3812491A US00301090A US30109072A US3812491A US 3812491 A US3812491 A US 3812491A US 00301090 A US00301090 A US 00301090A US 30109072 A US30109072 A US 30109072A US 3812491 A US3812491 A US 3812491A
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linescan
vector
store
video
raster
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C Barraclough
J Brown
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Roadside Technology Services Ltd
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GEC Elliott Automation Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/20—Function-generator circuits, e.g. circle generators line or curve smoothing circuits

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  • PATENTEDMAY 21 I974 sum 9 0F 9 Tan 9 Store Tan Reg.
  • This invention relates to raster-scanned display devices and, more specifically, is concerned with apparatus for generating a video signal for input to. a rasterscanned display device.
  • a raster-scanned display device is a cathode ray tube arranged to be scanned in a television-type raster.
  • other forms of rasterscanned display device are known: for example, an array of light emitting diodes arranged to be scanned electronically, or a screen arranged to be scanned by a laser beam.
  • One object of the invention is to provide a novel form of apparatus for generating video signals for input to a raster-scanned display device.
  • apparatus for generating a video signal for input to a raster-scanned display device to cause the device to display at least one graphical symbol
  • the apparatus comprising: an input store for holding, in digital form, input parameters of said at least one graphical symbol; digital data-processing means for processing said parameters to produce a digital output characterising said video signal; and means for converting said digital output into said video signal.
  • Said graphical symbols may be stroke symbols (e.g., straight or curved lines) or may be symbols having an appreciable area.
  • Stroke symbols may, for example, be used to form alphanumeric characters.
  • the stroke symbols may represent other information such as, for example, an aircraftflight path, or the position of the horizon relative to an aircraft.
  • said digital data processing means comprises: a video store adapted to hold information characterising a portion of said video signal corresponding to at least one linescan of the raster; computing means for performing calculations on said parameters in respect'of each linescan of the raster in turn to produce said information for loading into said video store; and read-out means for reading said information out of said video store, on completion of said calculations in respect of a linescan, to produce the portion of said digital output corresponding to that linescan.
  • said input store is adapted to hold the parameters of a plurality of graphical symbols
  • said computing means is adapted to perform, for each linescan of the raster, said calculations on the parameters of each of said graphical symbols in turn.
  • said video store is adapted to hold information characterising a portion 'of said video signal corresponding to a single linescan of the raster, the apparatus being so arranged that, in operation, said computing means performs said calculations in respect of a linescan during the linescan flyback period immediately preceding that linescan.
  • said video store is adapted to hold information characterising a portion of said video signal corresponding to two linescans of the raster, the apparatus being so arranged that, in operation, said computing means performs said calculations in respect of a linescan while information characterising the immediately preceding linescan is being read out of the video store.
  • said data processing means comprises means for storing a number defining the position of a portion of a said symbol within a linescan of the raster, and means for performing a predetermined algorithm, according to said parameters, to up date said number to its appropriate value for a succeeding linescan of the raster.
  • a display system comprising a rasterscanned display device, and apparatus for generating a video signal for input to the device, in accordance with the first aspect of the invention.
  • FIG. 1 is a schematic block diagram of the display system
  • FIG. 2 is an enlarged schematic view of a partof the picture displayed by the system
  • FIGS. 3a and 3b when arranged as indicated in FIG.
  • FIG. 4a is a schematic diagram illustrating the manner in which the video signal shown in FIG. 4b is stored in the display system
  • FIG. 5 is a schematic block diagram of a modification of the display system
  • FIGS. 6 and 7 are schematic circuit diagrams of parts of FIG. 3.
  • FIGS. 8a, b and c are flow diagrams arranged as indicated in FIG. 8d, and representing the operating logic of the circuit of FIG. 7.
  • the display system comprises an on-line digital computer 1, from which digital output data are fed, by way of an interface 2, to a vector generator 3 and a circule generator 4. These generators 3 and 4 produce respective video output signals which are combined in a mixer 5 and fed to the brightness modulation input of a cathode ray tube 6.
  • the cathode ray tube 6 is scanned in a television-type raster by means of scanning circuits 7. Line and frame synchronisation signals from the scanning circuits 7 are also fed to the vector and circle generators 3 and 4.
  • the raster pattern on the screen of the cathode ray tube 6 comprises 625 lines on a 4:3 aspect ratio picture area, and is of the interlaced field type. Of these lines, 576 are available for definition in the vertical (Y) direction. The corresponding definition in the horizontal X direction is approximately 700 video elements per linescan, corresponding to a video frequency of 14 megahertz.
  • each frame of the picture can be considered as being composed of 700 X 576 video elements, each of approximately a 1:1 aspect ratio.
  • the spacing between adjacent lines in the same field of the raster will be taken as the unit of length in the vertical direction, and the width of one video element will be taken as the unit of length in the horizontal direction. It will be appreciated that the vertical unit is therefore twice the horizontal unit.
  • the vector generator 3 is designed to generate a video signal which produces one or more straight lines (referred to herein as vectors") on the screen of the tube 6.
  • vectors can only be positioned on a restricted vector writing area of the screen, covering only 512 of the 700 elements in each linescan and only 512 lines in the vertical direction.
  • FIG. 2 shows a small portion of one frame of the raster (both odd and even interlaced fields) on a greatly enlarged scale, containing two vectors P and Q.
  • Each vector is built up from a series of brightened up portions of the raster lines. It will be seen that the brightened-up portions of a vector such as vector P are displaced horizontally by a fixed amount 2 tan 6 (where 6 is the angle between the vector and the vertical) between one linescan and the next in the same field, (in terms of the above-defined horizontal .unit of distance).
  • the brightened up portions for a given vector are displaced horizontally by a distance of tan 6 with respect to the even
  • the video signal from the generator 3 is quantised in three discrete levels of brightness, referred to respectively as full bright-up, two-thirds bright-up, and onethird bright-up (or, for brevity, full B.U. and one-third B.U.).
  • the sequence of brightness levels in each line of the raster is as follows (in terms of the above-defined unit of distance):
  • the vector generator 3 comprises a random access memory M1 having a capacity of 16 words, each 59 bits in length, and serving as an input data store.
  • This memory is constructed from integrated circuit memory elements (e.g., Texas Instruments Limited, type no SN 7489 memory elements.)
  • Data for up to sixteen vectors can be stored in the memory Ml, each vector being allocated one word of storage space.
  • Each word of the memory M1 is subdivided into a number of data stores for the associated vector, as follows:
  • a sort logic circuit 11 compares the value of tan 6 to be written into the store S4 of the memory M1 with the other tan 6 values already in the store S4, and modifies the contents of the next address store S8 of the memory M1 in such a manner that the next address store S8 of each word contains the address of the word containing the next lowest value of tan 6. This enables the vestors in the memory M1 to be processed in order of decreasing tan 6. The reason for this will be explained below.
  • the value of X in the store 81 each word is written into the current X store S7 of the same word, via a data selector 14 and a binary adder 15.
  • the adder l5 merely adds zero to the value of X,,.
  • the adder adds i tan 6 to X, before writing the result into the current X store S7.
  • the value of the tan 6 is obtained from the tan 6 store S4 of the memory M1 by way of a data selector 16. This causes the tan 6 displacement between odd and even fields, as mentioned above in connection with FIG. 2.
  • the vector generator 3 also comprises a second random access memory M2, having a capacity of 512 words, each word having six bits Bl-B6.
  • the memory M2 serves as a video store to contain information characterising a linescan of the video signal.
  • This memory is constructed from integrated circuit memory elements (e.g., Texas Instruments Limited type No. SN 74,200 memory elements).
  • Each of the 512 words in the memory M2 corresponds to one of the 512 video elements in the vector writing area of a linescan of the raster; Initially, all the bits of the memory M2 are set to O.
  • a l occurring in any given bit position of a given word signifies that the start or finish point of one of the three brightness levels, one-third B.U., two-thirds-B.U.'and FULL B.U. occurs at the video element corresponding to that word, as follows: i
  • the memory M2 stores a complete linescan of the video signal in the form of the start and finish points of the three discrete brightness levels.
  • FIG. 4a shows schematically a portions of the memory M2 storing the video signal for the linescan portion A-A in FIG. 2, while FIG. 4b shows the corresponding video signal.
  • two or more vectors may cross each other on a linescan, in which case their brightened-up portions will overlap in that linescan. This possibility is allowed for by ensuring that, on reading out from the memory M2, a given brightness level is not switched off until an equal number-of ONs and OFFs have been read for that level, and that higher brightness levels suppress lower levels (see below).
  • the video signal for each linescan is calculated from the input parameters in the memory M1, and written into the video store memory M2, during the period between leaving the vector writing area in the immediately preceding linescan and re-entering the vector writing area on the current linescan. It will be seen that this period comprises the line flyback period (12 microseconds) between those two linescans, plus a portion of each of the two linescans.
  • the calculation of the video signal is controlled by means of a video-store-load control circuit 17, and a scan counter 19.
  • the counter 19 receives line and frame synchronisation signals from the scanning circuit 7 (FIG. 1) to produce an 8-bit binary output Y equal to the number of line sof the current field o f tlie raster which have been executed at any given moment.
  • the control circuit 17 is a conventional control logic circuit comprising conventional logic components.
  • the calculation is performed for each of the words (vectors) in the memory M1 in turn, in the order determined by the next address stores S8 of the words.
  • the control circuit 17 reads the in vector bit from store S9 of the word, and at the same time compares the value of Y from the scan counter 19 with the values of Y and Y, in the memory Ml. If the in vector" bit is l, the calculation proceeds with stage (2). If the in vector bit is 0, but Y Y,,., the calculation still proceeds with stage (2), and at the same time the in vector. bit is set to 1. If Y Y,, the calculation still proceeds, but the in vector" bit is reset to 0.
  • STAGE (2) a The contents of the current.
  • X store S7 of the word are read into a 9-bit accumulator A2, by way of a data selector 21.
  • the contents of the current X store S7 are also fed by way of the selector 21 to a 10-bit digital adder 22, where they are added to T/2, and the result is read into a 10-bit accumulator A1.
  • T is the output of the selector 13).
  • the division of T by four is performed in a data selector 23, which can be alternatively operated to divide T by two.
  • accumulator A2 contains X, which is the video position of start of the first one-third B.U. period (see FIG. 4b), and Al contains X T/2, the video position of the end of the first one-third B.U. period.
  • the contents of the accumulator A2 are used to address the ON part (bits B1, B2, B3) of the video store M2, via data selectors 24 and 25.
  • the contents of the accumulatorAl are used to address the OFF part (bits B4, B5, B6) of the video store M2, via data selectors 26 and 27.
  • the contents of the accomulators A1 and A2 are calculated to an accuracy better than one half of a unit of distance (i.e., better than one video element) and are rounded up or down to the nearest half unit (i.e., to the nearest video element) before being used to address the memory M2.
  • bits B1 or B4 so addressed already contains a l which may be the case if a previously calculated vector intersects the present vector in the current linescan. If neither bit position contains a l, a 1 is now written into both bit positions. If, on the other hand there is a 1 already present in either bit, writing into the memory M2 is inhibited for both bits.
  • the horizontal width of the current vector will always be equal to or smaller than that of the previously calculated vector. Therefore, when writing into the memory M2 is inhibited in this way, the effect is merelyto eliminate a brightened-up portion which lies completely within a previously calculated brightened-up portion of the same level.
  • accumulators A2 and A1 respectively contain X +T/2 and X T, the start and finish positions of the first two-thirds B.U.period.
  • accumulators A2 and A1 are used to address the memory M2, as in stage (2), and a l is written into the bits B2 and B so addressed, if both are empty.
  • accumulators A2 and Al respectively contain X T and X +2T, the start and finish points of the full B.U. period.
  • accumulators A2 and Al respectively contain X 5T/2 and X 3T, the start and finish points of the second one-third B.U. period.
  • accumulators A2 and Al are used to address the memory M2 as in stage (2), and a l is written into the bits B1 and B4 so addressed, if both are empty.
  • the memory M2 now contains complete information characterising the video brightness pattern corresponding to the relevant vector for the current linescan.
  • the contents of the current X store S7 are fed to one input of adder 15, via selector l4, and added to 2tan 6, which is applied to the adder 15 via selector 16.
  • the re sult is read back into the current X store S7 to serve as the value of X for the next line of the raster.
  • stage (7) tan 0 is subtracted from the contents of the current X store S7 by the adder 15.
  • the output T from the data selector 13 will be equal to l, and therefore the values of the quantities X, X T/2, X T, X +2T, X 5T/2 and X 3T will, when rounded up or down to the nearest video element, overlap to some extent. As mentioned, it is arranged that where such an overlap occurs the higher brightness level overrides the lower one. The result is as shown in FIG. 2.
  • the pattern of brightness is as indicated in linescan B, i.e., it comprises one viseo element of two-thirds B.U., followed by full B.U.
  • linescan C the pattern of brightness is as indicated in linescan C, i.e., it comprises one-third B.U. for one video elements, followed by full B.U. for another video element and two-thirds B.U. for a further video element.
  • this progressive increase and decrease in brightness ensures that the vector has a substantially unstepped appearance to the eye.
  • the memory M2 is read out in synchronism with the execution of the linescan by the cathode ray tube.
  • Read-out of the memory M2 is controlled by a clock 28 running at 14 megahertz (the frequency corresponding to the division of the vector writing area of a linescan into 512 elements). Output pulses from the clock 28 are counted by an address counter 29, which is reset to zero at the point of reentry into the vector writing area on the linescan.
  • the memory M2 is read out by addressing it with the contents of the address counter 29, via the data selectors 25 and 27. Thus, each of the 512 words in the memory M2 is addressed at the, instant at which the corresponding element of the vector writing area on the screen is scanned.
  • the output from the memory M2 is fed to three up/- down counters 30, 31, and 32 which correspond re spectively to the three video levels one-third B.U., twothirds B.U., and full B.U. These counters are all initially set to zero. 1
  • a word addressed in the memory M2 contains a l at any one of its ON bit positions B1, B2or B3, the corresponding up/down counter is incremented by one. Similarly, if a word addressed in the memory M2 contains a l at any one of its OFF bit positions B4, B5, or B6, the corresponding up/down counter is decremented by one. Thus, if the contents of one of the counters 30, 31 and 32 are zero, this indicates that the corresponding video level should be off, since an equal number of ON and OFF signals have been read from the counters 30, 31 and 32 is non-zero, this indicates that the corresponding video level should be on, since more ON signals than OFF signals have been read from the memory M2.
  • the digital output from the upldown counters 30, 31 and 32 is converted by a video output circuit 33 into a video output signal having one of the three discrete lev 'els one-third B.U., two-thirds B.U. and full B.U., ac-
  • the video output signal from the output circuit 33 is fed via output lead 34 to the cathode ray tube 6 via the mixer 5 (FIG. 1).
  • the video store M2 may be divided into two halves, each containing 256 words of 6 bits in length.
  • the two halves of the memory are addressed alternately, so that adjacent video elements are stored in different halves of the memory.
  • the two halves are addressed alternately. This enables faster read out speeds to be achieved than would be possible with an undivided memory.
  • the video store M2 may be replaced by two stores, each of which is capable of storing a complete liescan of video. In operation, while the contents of one of these stores are being read out, the vector generator performs calculations to update the contents of the other store for the next linescan. In the alternate Iinescans, the roles of the two stores are interchanged. It will be seen that with this arrangement the time available for calculation is greatly increased, comprising a whole line-scanning period (64 microseconds) of the raster in addition to the flyback period. Therefore, many more vectors can be the memory M2. Conversely, if the contents of one of In another modification of the vector generator 3, the video store M2 may be replaced by an associative (i.e., contents-addressable)memory.
  • an associative i.e., contents-addressable
  • the video store M2 in this modification comprises an associative memory divided into six stores, two for each level of bright-up. In the drawing, only the two stores 40, 41 for the one-third B.U. level are shown.
  • Each store contains a number of words, each eight bits in length.
  • the contents of each word in the store 40 represent the X-coordinates of the starting point of a given one-third B.U. level, while the contents at the same address in the store 41 represent the X- coordinates of the end points .of that one-third B.U. level.
  • an address counter 43 (corresponding to the counter 29 in FIG. 3) is applied to the associate" inputs 48 of the stores 40 and 41.
  • an output signal appears at the associate" output corresponding to that word, indicating that a one third B.U. level starts or finishes at that instant.
  • the output from each word of the store 40 is fed to one side of a corresponding bistable circuit 44, while the output from the corresponding word in the store 41 is fed to theother side of the same bistable circuit 44.
  • the bistable circuits 44 are clocked at the read-out rate (14 megahertz) of the system by means of a clock 46.
  • the state of a given bistable circuit 44 at any instant signifies whether the corresponding one-third B.U. level is ON or OFF at that instant.
  • the outputs of all the bistable circuits 44 are combined in an OR gate 45.
  • An output of l from the OR gate 45 indicates that the video element which is currently being scanned is at the one-third B.U. level.
  • an associative memory for the video store M2 hasthe advantage that it is not necessary, as in the arrangement of FIG. 3, to sort the input data into order of decreasing tan 6, since overlapping vectors do not present any special problem in this case, each vector being stored in a separate word of the video store. In addition, it is not necessary to use up/down counters for the output of the video store.
  • the two shading bits in store S10 of the input memory Ml are used to allow a one-third B.U. shading between two selected vectors.
  • the two bits provide four different codes: one code is used to signify which vector turns the shading on, another to signify which vector turns the shading off.
  • a third code signifies that there is no shading associated with the relevantvector.
  • the vector generator 3 can be used to generate curves, by stringing a series of vectors together i.e.,
  • the input memory Ml may be enlarged.
  • the strung vectors do not double back on themselves they only take up approximately the calculation time required for a single vector.
  • Stringing of a large number of vectors can alternatively be achieved, without enlarging the input memory, by adjusting the value of tan of a vector during the course of a frame of the raster.
  • this is only possible where data can be read in from the computer 1 during line scanning periods as well as during frame flyback.
  • the circle generator 4 (FIG. 1) is similar in principle to the vector generator 3, and comprises an input data store, into which parameters of one or more (up to three) circles can be written from the interface 2 during frame flyback periods, a video store in which a line of video can be stored, and digital calculating circuitry which calculates, during line flyback, from the input parameters of each circle, the video signal required to display that circle, the result being used to update the video store.
  • the input parameters for each circle comprise:
  • each circle For each circle, calculations commence at linescan Y and terminate at linescan Y,, 2R.
  • Each linescan containing the circle comprises two brighted-up portions, corresponding respectively to the left and right sides of the circle.
  • the X-coordinates of these brighted up portions are equal to X,,offset and X offset respectively.
  • the value of the offset is stored in a register, and is modified by the digital calculating circuitry between linescans.
  • R be the radius of the circle, measured in units of the distance between adjacent lines in the same (odd or even) field.
  • N be the number of the current linescan, counting from the linescan Y,,.
  • the initial value of the offset in linescan Y is taken as being equal to R.
  • the circle generator may be modified so that the video store can hold two linescans of video at a time. Calculations can then be performed to update one linescan while the previous linescan is being read from the video store. Therefore, the whole line scanning period is available for calculation, which increases the capacity of the generator from three to twelve circles.
  • FIG. 6 shows a possible circuit configuration for the video output circuit 34 of FIG. 3.
  • Each of the up/down counters 30, 31 and 32 is arranged to produce a 1 output when its count is nonzero (i.e., when the corresponding level is ON) and a 0 output when its count is zero (i.e., when the cone sponding level is OFF).
  • the three output signals from the up/down counters are fed to respective potentiometers 60, 61 and 62 which produce respective output voltages proportional to the one-third, two-thirds and FULL B.U. brightness levels.
  • the voltages across these potentiometers are added together by way of resistors 6366 and applied to an amplifier 67, the output of which is connected to the video output lead 34.
  • the presence of a l at the output of the two-thirds B.U. counter 31 is arranged to suppress any l from the one-third B.U. counter 30, by means of an inhibiting 0 from an inverter 68 applied to AND gate 69.
  • the presence of ,a l at the output of the FULL B.U. counter 32 is arranged to suppress any l from the one-third B.U. counter 30 or the two-thirds B.U. counter 31, by means of an inhibiting 0 from an inverter 70, applied to AND gate 69 and AND gate 71.
  • FIG. 7 shows the next address store 58 and the tan 6 store S4 of the data store M1, which have already been described.
  • up to sixteen vectors are stored in the sixteen words of the data store M1, these vectors being arranged in a sequence in order of decreasing tan 0, by virtue of the next address portion of each word which gives the address of the following vector in the sequence.
  • One bit S8 of the next address store is designated the next address valid (NAV) bit, and is set to 1 for each vector in the store, except the last vector in the sequence, thus enabling that last vector to be readily identified.
  • NAV next address valid
  • Data can be applied to the address input line 100, by way of a data selector 108, from either register 1 10 (referred to as the address register), or from the N register 104.
  • the logic circuit 11 also contains the following registers, each of which has storage space for a vector address:
  • Register 112 (referred to as the A register), which is used to hold the address of the vector in the store Ml that has the largest tan 6 value, thus enabling the start of sequence of vectors to be readily identified.
  • the contents of N register 104 can be written into it, as will be described.
  • Register 114 (referred to as the S register), which can be written into from. either the address register 110 or the N register 104.
  • Register 116 (referred to as the P register) which can be written into from either the address register 110 or the S register 114 d.
  • Register 118 (referred to as the T register) which can be written into from address register 110.
  • Register 120 (referred to as the L register) which can be written into either from the T register 118 or from the next address store S8 of the vector that is currently addressed over line 100.
  • the contents of the address register 110 and N register 104 can be compared in address comparator 122, the output of which can be used to set bistable circuit G or H.
  • address comparator 122 the contents of which can be used to set bistable circuit G or H.
  • tan 6 register 106 and the tan value of the currently addressed vector in the store M1 can be compared in tan 6 comparator 124, the output of which can be used to set bistable circuit J or K.
  • the address register 110 can be written into by way of data selector 126 from either P register 116 or from the next address store of the currently addressed vector in M1. This next address store can, in turn, be written into, via data selector 128, either from L register 120 or from N register 104.
  • the NAV bit of the currently addressed vector can be used to set bistable Z.
  • control logic circuit 130 which is a conventional control logic circuit comprising conventional logic components (AND gates, OR gates, bistable circuits etc).
  • FIGS. 8a, b and 0 show a flow diagram characterising the control logic circuit 130, showing in detail each step of the operation of the tan 6 sort logic circuit.
  • the symbol has its usual meaning thus, for example, the statement P REG. S REG.
  • Box 200 (FIG. 8a) reads this address from the data highway into the N register 104, and box 202 then reads the tan 9 value from the highway into the tan 6 register 106. Box 204 then writes the contents of the A register 112 (i.e.,v the address of the vector currently having the largest tan 0 in the memory Ml) into the address register 110. Box 206 resets all the'bistables G, H, J, K and Z.
  • the sort logic circuit has determined the exact point in the sequence of vectors at which the new tan 0 value'in tan 0 register 106 should be placed.
  • the S register 114 contains the address of the vector in the sequence having the next highest value of tan 0, and the T register 118 contains the address of the vector having the next lowest value of tan 6. If bistable J is not set, this indicates that the new tan 0 is smaller than all the existing tan 0 values, while if bistable K is not set, this indicates that the new tan 6 is larger than all the existing tan 0 values.
  • a second loop is performed, as follows: Box 222 examines bistable G. Initially, this bistable is reset, so that control passes to box 224 which operates address comparator 122 causing the contents of the N register 104 to be compared with the contents of the address register 110.
  • box 226 writes the contents of the address register 110 into the P register 116, and sets bistable H. If, on the other hand, the two addresses are equal (indicating that the new parameters are intended to update the parameters of the vector currently addressed vector) control passes to box 228.
  • This box checks whether the NAV bit of the currently addressed vector is zero, and if this is the case, bistable Z is set by box 230, indicating that the new parameters are intended to update the parameters of the vector which is currently the last in the sequence. Generally, however, the box 228 will detect that the NAV bit is non-zero, whereupon control will pass to box 232, which sets the bistable G and writes the next address bits of the currently addressed vector into the L register 120.
  • This second loop is repeated, in synchronism with the first-mentioned loop, so that the address in the N register 104 is compared with the address of each vector in the sequence in turn until either (a) a match is found, whereupon bistable G is set and. the second loop is short-circuited by box 222, or (b) the end of the sequence is reached.
  • the P register 116 contains the address of the vector immediately preceding the vector which is to be updated, while the L register 120 contains the address of the vector which immediately follows the vector to be updated. If bistableZ is set, the vector to be updated is the last in the sequence, while if bistable H is not set,
  • box 234 loads the contents of the P register 116 into the address register 110 via data selector 126, and box 236 then loads the contents of the S register 114 into the P register 116, and the contents of the N register 104 into the S register 114.
  • Box 238 then examines bistable H. If this bistable is not set, indicating the special case where the first vector in the sequence is to be updated, control passes directly to box 240. Generally, however, bistable H will have been set, and control will pass to box 242, which examines bistable G.
  • bistable G is set, indicating that one of the vectors is to be updated (other than the first or the last vector) control passes to box 244, which causes the contents of the L register 120 to be written into the next address store of the currently addressed vector, via data selector 128. It will be recalled that the address memory 110 was loaded, by box 234 above, with the address of the 'vector immediately preceding the vector to be updated.
  • box 244 effectively removes the vector to be updated from the sequence, and closes up the gap left by it, by writing the address of the following vector into the next address store of the preceding vector. Control then passes to box 240.
  • bistable G If, on the other hand, bistable G is not set, control passes to box 246 which ecamines bistable Z. Bistable Z being set indicates the special case where the last vector in the sequence is to be updated, and control therefore passes to box 248, which acts to reset bistable Z and to set the NAV bit of the vector which is currently addressed to zero. This effectively removes the last vector from the sequence, and terminates the sequence on the preceding vector, by setting the NAV bit of the preceding vector to zero. Control then passes to box 240, as it does if box 246 finds that bistable Z has not been set. i
  • the following part of the operation deals with placing (or replacing, as the case may be) the new or updated vector into the sequence of vectors, at the appropriate point as determined by its new tan 6 value.
  • Box 240 is operative to write the contents of the P register 116 into the address register 110, via data selector 126, and to write the contents of the S register 114 into the P-register 116.
  • the register 116 now contains the address which was originally in the N register 104 (i.e., the address of the vector whose parameters are to be entered into the memory M1, or updated) and the address register 110 now contains the address which was originally in the S register 114 (i.e., the address of the vector having the next largest tan 6 value to the new tan 6 value).
  • Box 250 examines bistable K.
  • bistable K is set, and control therefore passes to box 252, which acts to write the contents of the N register 104 into the next address store 58 of the currently addressed vector via data selector 128.
  • the address of the new (or updated) vector is written into the next address store of the vector with the next largest tan 6 value, thus effectively breaking the sequence of vectors at the appropriate point, to insert the new vector.
  • the NAV bit of the currently addressed vector is set to Y 16 .1 (although, in general, this bit will already be 1). Control then passes from box 252 to box 254.
  • box 250 finds that bistable K is not set (signifying the special case where the new tan 6 value is larger than all the tan 6 values currently in the tan 6 store S4) control passes from box 250 to box 256, which acts to write the contents of N register 104 into A register 112, thereby updating the record of the address of the vector having the largest tan 6 value. Box 256 also acts to set the NAV bit of this vector to 1" and to reset bistable G. Control then passes to box 254.
  • new vector is to be placed at the end of the sequence. This is performed as follows.
  • Box 254 acts to write the contents of the T register (i.e., the address of the vector having the next lowest tan 6 value to the new tan 6 value) into the L register, provided the bistable G is not set (in which case the L register will already have been written into by box 232).
  • Box 254 also writes the contents of the P register (containing the address of the new or updated vector) into the address register 110, via data selector 126.
  • Box 258 (FIG. 8c) then tests whether bistable J is set. If this bistable is not set (indicating that the new tan 6 value is smaller than all the values currently in the memory M1) control passes to box 260, which acts to write the new tan 6 value from tan 6 register 106 into the tan 6 store of the currently addressed vector, and to set the NAV bit of that vector to zero. This completes the operation of the tan 6 logic circuit for this special case.
  • bistable J If the bistable J is set, control passes from box 258 to box 262, which tests bistable Z. If bistable Z is set (indicating that the new tan 6 value is updating the last vector in the sequence) control again passes to box 26 0, as above.
  • bistable Z If bistable Z is not set, control passes to box 264, which tests the bistable G. If bistable G is set (indicating that the new tan 6 value is updating one of the vectors already in the store, other than the first or last) control passes to box 266, which acts to write the new tan 6 value from tan 6 register 106 into the tan 6 store of the currently addressed vactor, and sets the NAV bit of this vector to l. The next address store of this vector has, in this case, already been written into by box 244 above.
  • Apparatus for generating a video signal for input to a raster-scanned display device to cause the device to display at least one graphical symbol comprising: an input store for holding, in digital form, input parameters of said at least one graphical symbol; digital data-processing means comprising means for calculating start and finish time positions of at least one video brightness level, for processing said parameters to produce a digital output characterizing said video signal; and at least one up/down counter for counting up when said digital output indicates a start of said video brightness level, and counting down when said digital output indicates an end of said level, together with means for producing a video signal having that brightness level only when the count of the counter is greater than zero, for converting said digital output into saie video signal. 7
  • said digital data processing means comprises: a video store adapted to hold information characterising a portion of said video signal corresponding to at least one linescan of the raster; computing means for performing calculations on said parameters in respect of each linescan of the raster in turn to produce said information for loading into said video store; and read-out means for read ing said infonnation out of said video store, on completion of said calculations in respect of a linescan, to produce the portion of said digital output corresponding to that linescan.
  • Apparatus according to claim 2 wherein said input store comprises a plurality of storage locations for respectively holding parameters of a plurality of graphical symbols, and said computing means comprises 5.
  • Apparatus according to claim 4 wherein said computing means comprises means for calculating in which of said segments of the linescan start and finish time positions of at least one video brightness level and means for loading digital codes signifying start and finish into the words of said video store corresponding to those segments.
  • said input store comprises a plurality of storage locations for respectively holding parameters of a plurality of graphical symbols
  • said computing means comprises means for addressing each of said locations in turn, in order of decreasing extent of the symbol in the direction of the linescan.
  • said data processing means comprises means responsive to synchronisation signals from said raster scanned display device, for initiating the processing of said parameters, in connection with a linescan of the raster, during the linescan flyback period immediately preceding that linescan.
  • said data processing means comprises means for storing a number defining the position of a portion of said symbol within a linescan of the raster, and] means for performing a predetermined algorithm, according to said parameters, to update said number to its appropriate value for a succeeding linescan of the raster.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Generation (AREA)
US00301090A 1971-10-27 1972-10-25 Raster-scanned display devices Expired - Lifetime US3812491A (en)

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JP (1) JPS4852335A (enrdf_load_stackoverflow)
DE (1) DE2252556C2 (enrdf_load_stackoverflow)
FR (1) FR2166929A5 (enrdf_load_stackoverflow)
GB (1) GB1405884A (enrdf_load_stackoverflow)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902476A (en) * 1974-04-02 1975-09-02 Unirad Corp Scanning display for sampled data
US3918039A (en) * 1974-11-07 1975-11-04 Rca Corp High-resolution digital generator of graphic symbols with edging
US3969716A (en) * 1974-06-07 1976-07-13 British Broadcasting Corporation Generation of dot matrix characters on a television display
FR2347844A1 (fr) * 1976-04-08 1977-11-04 Hughes Aircraft Co Dispositif d'affichage par lignes a resolution elevee
DE2738534A1 (de) * 1976-09-03 1978-03-09 Smiths Industries Ltd Anzeigesystem
FR2371031A1 (fr) * 1976-11-15 1978-06-09 Elliott Brothers London Ltd Procede et appareil d'affichage de symboles
US4095216A (en) * 1975-08-07 1978-06-13 Texas Instruments Incorporated Method and apparatus for displaying alphanumeric data
US4119956A (en) * 1975-06-30 1978-10-10 Redifon Flight Simulation Limited Raster-scan display apparatus for computer-generated images
US4127850A (en) * 1974-10-03 1978-11-28 Smiths Industries Limited Scanning display apparatus
US4158200A (en) * 1977-09-26 1979-06-12 Burroughs Corporation Digital video display system with a plurality of gray-scale levels
US4231032A (en) * 1977-09-09 1980-10-28 Hitachi, Ltd. Variable accuracy trend graph display apparatus
US4241341A (en) * 1979-03-05 1980-12-23 Thorson Mark R Apparatus for scan conversion
US4262290A (en) * 1978-05-12 1981-04-14 Smiths Industries Limited Display systems
US4298867A (en) * 1979-07-06 1981-11-03 System Concepts, Inc. Cathode ray tube character smoother
US4300136A (en) * 1979-05-10 1981-11-10 Nippon Electric Co., Ltd. Display pattern preparing system
US4307393A (en) * 1977-11-11 1981-12-22 Hitachi, Ltd. Trend graph display system
US4318097A (en) * 1978-03-15 1982-03-02 Nippon Electric Co., Ltd. Display apparatus for displaying a pattern having a slant portion
US4458330A (en) * 1981-05-13 1984-07-03 Intergraph Corporation Banded vector to raster converter
US4679039A (en) * 1983-11-14 1987-07-07 Hewlett-Packard Company Smoothing discontinuities in the display of serial parallel line segments
US5216756A (en) * 1989-09-29 1993-06-01 Nihon Kohden Corporation Luminance interspersion type waveform display apparatus
US20090245674A1 (en) * 2008-03-27 2009-10-01 Megachips Corporation Image processor

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3987284A (en) * 1974-12-03 1976-10-19 International Business Machines Corporation Conic generator for on-the-fly digital television display
US4145754A (en) * 1976-06-11 1979-03-20 James Utzerath Line segment video display apparatus
JPS5399728A (en) * 1977-02-12 1978-08-31 Nippon Telegr & Teleph Corp <Ntt> Straight line drawing method
JPS53121424A (en) * 1977-03-31 1978-10-23 Nippon Telegr & Teleph Corp <Ntt> Straight line drawing method
JPS5453833A (en) * 1977-10-07 1979-04-27 Nippon Telegr & Teleph Corp <Ntt> Arc description method
US4280186A (en) * 1978-07-07 1981-07-21 Tokyo Shibaura Denki Kabushiki Kaisha Exposure apparatus using electron beams
FR2479622B1 (fr) * 1980-03-28 1985-08-23 Sfena Procede de lissage des courbes generees par balayage de television

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE339580B (enrdf_load_stackoverflow) * 1967-12-06 1971-10-11 Standard Radio & Telefon

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3902476A (en) * 1974-04-02 1975-09-02 Unirad Corp Scanning display for sampled data
US3969716A (en) * 1974-06-07 1976-07-13 British Broadcasting Corporation Generation of dot matrix characters on a television display
US4127850A (en) * 1974-10-03 1978-11-28 Smiths Industries Limited Scanning display apparatus
US3918039A (en) * 1974-11-07 1975-11-04 Rca Corp High-resolution digital generator of graphic symbols with edging
US4119956A (en) * 1975-06-30 1978-10-10 Redifon Flight Simulation Limited Raster-scan display apparatus for computer-generated images
US4095216A (en) * 1975-08-07 1978-06-13 Texas Instruments Incorporated Method and apparatus for displaying alphanumeric data
FR2347844A1 (fr) * 1976-04-08 1977-11-04 Hughes Aircraft Co Dispositif d'affichage par lignes a resolution elevee
DE2738534A1 (de) * 1976-09-03 1978-03-09 Smiths Industries Ltd Anzeigesystem
FR2371031A1 (fr) * 1976-11-15 1978-06-09 Elliott Brothers London Ltd Procede et appareil d'affichage de symboles
US4237457A (en) * 1976-11-15 1980-12-02 Elliott Brothers (London) Limited Display apparatus
US4231032A (en) * 1977-09-09 1980-10-28 Hitachi, Ltd. Variable accuracy trend graph display apparatus
US4158200A (en) * 1977-09-26 1979-06-12 Burroughs Corporation Digital video display system with a plurality of gray-scale levels
US4307393A (en) * 1977-11-11 1981-12-22 Hitachi, Ltd. Trend graph display system
US4318097A (en) * 1978-03-15 1982-03-02 Nippon Electric Co., Ltd. Display apparatus for displaying a pattern having a slant portion
US4262290A (en) * 1978-05-12 1981-04-14 Smiths Industries Limited Display systems
US4241341A (en) * 1979-03-05 1980-12-23 Thorson Mark R Apparatus for scan conversion
US4300136A (en) * 1979-05-10 1981-11-10 Nippon Electric Co., Ltd. Display pattern preparing system
US4298867A (en) * 1979-07-06 1981-11-03 System Concepts, Inc. Cathode ray tube character smoother
US4458330A (en) * 1981-05-13 1984-07-03 Intergraph Corporation Banded vector to raster converter
US4679039A (en) * 1983-11-14 1987-07-07 Hewlett-Packard Company Smoothing discontinuities in the display of serial parallel line segments
US5216756A (en) * 1989-09-29 1993-06-01 Nihon Kohden Corporation Luminance interspersion type waveform display apparatus
US20090245674A1 (en) * 2008-03-27 2009-10-01 Megachips Corporation Image processor
US8229239B2 (en) * 2008-03-27 2012-07-24 Megachips Corporation Image processor

Also Published As

Publication number Publication date
DE2252556A1 (de) 1973-05-03
JPS4852335A (enrdf_load_stackoverflow) 1973-07-23
GB1405884A (en) 1975-09-10
FR2166929A5 (enrdf_load_stackoverflow) 1973-08-17
DE2252556C2 (de) 1982-05-06

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