US3810160A - Switching matrix - Google Patents

Switching matrix Download PDF

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US3810160A
US3810160A US00305061A US30506172A US3810160A US 3810160 A US3810160 A US 3810160A US 00305061 A US00305061 A US 00305061A US 30506172 A US30506172 A US 30506172A US 3810160 A US3810160 A US 3810160A
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circuit
input
circuits
matrix
output
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J Hedde
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Emhart Enterprises Corp
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Assigned to EMHART ENTERPRISES CORP. reassignment EMHART ENTERPRISES CORP. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). EFFECTIVE DATE: MAY 8, 1987 Assignors: USM CORPORATION
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/1778—Structural details for adapting physical parameters

Definitions

  • Inventor. Jean Hedde 1 rue des Platenes 9l delay between different binary variables comprises an Orsay array of identical switching circuits disposed in the form of a matrix table having n lines and m columns.
  • Each circuit comprises an input terminal C, an input Appl. No.: 305,061
  • Ziems ABSTRACT A switching matrix for realizing at least one or more terminal E of said applied binary variable, an output terminal L and an auxiliary output terminal S which supplies the complemented value of the value which appears at the output terminal L.
  • Each succeeding circuit on a line has an input C coupled to the output L of the preceeding circuit which is located on the same line and each preceeding circuit on a line has an output L coupled to the input C of the following circuit which is located on the same line.
  • the inputs C of the circuits of the first column are all connected to ground.
  • Means for provide selected connections between different circuits through the intermediary of the terminals L, E and S and means are provided for applying said binary variables to said terminals E.
  • each circuit is such as to have the following relations between the input and output values .
  • a switching matrix is a device in which the components are each equivalent to a switch and disposed in the form ofa matrix; this device serves to realize a transcoding function, that is to say to produce at the output binary values which are dependent on input binary variables applied in each case at one of the inputs of the matrix.
  • This matrix can advantageously be employed for the automation of industrial processes such as the control and regulation of physical quantities (temperature, pressure, flow rate and the like), opening and closure of valves, switching-on of apparatus, and so forth.
  • the binary switching matrices of the prior art make use of Boolean algebra.
  • These devices are logic circuits formed from elementary circuits which arise from the application of Boolean algebra (for example AND and OR circuits) and a single device which usually serves to realize a single transcoding function.
  • the different elements are connected to a printed circuit which is specially designed for the realization of said transcoding function.
  • the realization of another function by means of this apparatus entails the need to modify the printed circuit and it is more advantageous in that case to provide a new device.
  • the replacement of one elementary circuit by another calls for a further study of the connections between elements and complete rewiring is therefore necessary.
  • Boolean algebra is written in a linear manner and the study of the location of the different elementary circuits in order to form a logic circuit does not readily lend itself to this type of linear writing.
  • the simplifications which can be made in the realization of logical functions are not evident.
  • the present invention proposes a switching matrix and a switching circuit which corresponds to practical requirements more effectively than those of the prior art, especially insofar as the matrix permits a simpler design of the logic circuits, ready modification of these circuits and the use of a single elementary circuit, this being achieved by employing a formalism of writing of a binary analysis which is different from Boolean algebra.
  • the invention proposes a switching matrix for realizing at least one transcoding function having a constant switching time-delay between different binary variables, characterized in that it comprises an array of switching circuits which are all identical and disposed in a matrix table having n lines and m columns, each circuit comprising an input terminal C proper of said circuit and an input terminal E of said applied binary variable, an output terminal L proper of said circuit and an auxiliary output terminal S which supplies the complemented value of the value which appears at said output terminal L proper, a circuit having an input C proper coupled to the output L proper of the aforesaid circuit which is located on the same line and an output L proper coupled to the input C proper of the following circuit which is located on the same line, the inputs C proper of the circuits of the first column being all connected to ground, means for providing connections between different circuits through the intermediary of the terminals L, E and S and means for applying said binary variables to said terminals E, the structure of each circuit being such as to have the following relations between the input and output values 5 BAND-C and
  • a second transistor having a grounded emitter, a collector which is coupled to the auxiliary output S and a base which is connected through a Zener diode to the collector of said first transistor, and by a second biasing resistor connected between said voltage source and the collector of said first transistor.
  • FIG. 1 is an electrical diagram of said switching circuit
  • FIG. 2 shows diagrammatically one form of construc tion of the switching matrix
  • FIGS. 3 to 7 show by way of example the realization of different transcoding functions by means of said matrix.
  • This function which is designated by the author of this binary analysis as Produel and usually known as the OR" function at the time ofits applications is zero when all all its terms a, [2,0, are simultaneously zero and equal to unity if only one of these terms is equal to unity. It is said that the terms a, b, c, are in dual factor.
  • Produel 7T function by grouping together the terms which compose this latter in a vertical column by analogy with the horizontal writing ofthe product P and in order to represent in this new symbolism the property of duality the main properties which are common to the product P and to the produel rrarc commutativity, associativity, idempotence (or in other words a" a) and reciprocal distributivity.
  • the circuit A comprises a first transistor 2, the base of which is coupled to the input E through a Zener diode 4.
  • the emitter of said transistor is coupled directly and solely to the input C and its collector is connector to the output terminal L without any load resistance connected to the potential V, the resistor 9 being solely intended to apply a bias voltage to the base ofa second transistor 7.
  • a bias resistor 6 is connected between the input E of the binary variable and the source of bias voltage V.
  • the base of the second transistor 7 is connected to the collector of the transistor 2 through a Zener diode 8.
  • the collector of the transistor 7 is connected directly to the auxiliary output S and the emitter of said transistor is connected to ground.
  • a bias resistor 9 is connected between said voltage source V and the collector of the transistor 2.
  • Each base of the two transistors 2 and 7 can be connected to ground through a bias resistor which is not shown in the drawings, but this resistor is not essential.
  • the transistor 2 operates in the same manner as a contact having a non-zero residual resistance which is compensated by the Zenerdiode 4.
  • the Zener voltage of the diode 8 must be considerably higher than the collector-emitter saturation voltage of the transistor 2.
  • the transistor 7 complements and regenerates the signal which is applied to its base. This transistor can be chosen so as to permit, if necessary, the passage of a saturation current of sufficiently high value to drive directly an external element of medium power.
  • the switching circuit can advantageously be employed for the construction of a switching matrix which utilizes the formalism of the binary analysis as explained in the foregoing.
  • This matrix is shown diagrammatically in FIG. 2. It comprises an array of elementary circuits A as shown in FIG. 1, these circuits being arranged in the form ofa matrix table having m lines and n columns. The connections between the emitters of the transistors 7 and ground as well as the connections between the resistors 6 and 9 and the source of bias voltage V are not shown.
  • the circuits A of any one line are connected in series; in other words, the input terminal C of each circuit A is connected to the terminal L of the preceding circuit and the terminal L of the circuit considered is connected to the input terminal C of the following circuit.
  • the inputs C of-all the circuits A of the first column are connected to ground.
  • the Zener voltage of each diode 4 and 8 must be higher than the sum of the collector-emitter saturation voltages of the series-connected transistors 2.
  • the transistor 2 of said circuit remains in the cut-off or non-conducting state as long as the voltage of its base is lower than the Zener voltage of the diode 4, namely as long as said resistance remains lower than a fairly substantial predetermined value (a few kilohms): this resistance corresponds to the sum of residual resistances of a large number of series-connected transistors 2 in the saturated state.
  • each circuit A can be compared with an open or closed contact and each line of the matrix can be considered as a se ries of unidirectional contacts each controlled by its input E.
  • Two series-connected elementary circuits A with the input C of the first circuit being connected to ground, deliver at the output S of the second circuit the logical AND function between the binary .variables which are each applied to the two inputs E of the two circuits in series.
  • the matrix comprises means for establishing vertical and oblique connections corresponding to connections of the elementary circuits in parallel. Said vertical and oblique connections can be established between the terminals L, E and S of the different circuits.
  • the two circuits 11 and 12 realize the AND function between the two binary variables a and b. The function ab is therefore obtained at the output L of the circuit 12.
  • the realization of the function F 1 abcd is obtained simply by applying the binary variables a, b, c, and d to the input terminals E of the circuits respectively 11, 12, 13 and 14, the series connection of the four circuits ll, 12, 13 and 14 being already performed since all the elementary circuits of any one line of the matrix are connected in series.
  • the transcoding function F is obtained at the output S of the circuit 14.
  • the logical OR function between the two binary variables e and fis obtained by placing the outputs L of the two circuits 23 and 33 in parallel, the binary variables e and f being applied to the input terminals E of said circuits.
  • the logi cal AND operation between the two binary variables g and h is carried out by the circuits 24 and 25 which are placed in series tfe same applies to the i l operation performed by the circuits 34 and 35.
  • a circuit whose input E is at the logical level 1 (and isolated from ground) serves as a connection from the left-hand side towards the right-hand side between two circuits (circuit 35 in FIG. 3).
  • the logical OR operation between g, h, and i' is obtained by connecting the outputs L of the two circuits 25 and 35 in parallel.
  • the transcoding function F is thus obtained at the terminal S of the switching circuit 35.
  • the input E of the two circuits 22 and 32 is placed at the logical level 0 (by connecting to ground).
  • the transcoding function F is obtained in accordance with the same wiring process by connecting in parallel the outputs L of the circuits 21, 31 and 41 to which are applied respectively the binary variables i; k, l, and also by applying the binary variables m, n and p to the inputs E of the circuits 42, 43 and 44 respectively, the three circuits just mentioned being pre-wired in series.
  • the function F is obtained at the output S of the elementary circuit 44.
  • FIG. 4 shows the realization of the exclusive-OR" function having two variables a and b.
  • This function F (a, b,) entails the need to obtain the variables 5 and 5; these latter designate the complemented values of the variables a and b.
  • the complemented values are obtained directly at the outputs L of the elementary circuits.
  • the inputs E of the circuits 12 and 22 therefore receive the complemented variables 1'1 and 1
  • the function F (a, b) is realized by connecting the outputs L of the circuits 12 and 22 in parallel, the
  • FIG. shows the realization of the transcoding function F (abcd), namely the exclusive-OR" function with four variables.
  • This function is a generalization of the preceding function F (uh).
  • the writing of this function having four variables by means of the formalism of the binary analysis is shown in FIG. 5.
  • attention is drawn to the manner in which the complemented variables are obtained.
  • the function F (a,h,c,d,) is obtained at the terminal S of theelementary circuit 33 or 23.
  • FIGS. 4 and 5 clearly show the manner in which the complemented variables are obtained from direct variables by means of connections L,- E,- between the terminals L and E of two circuits 1' and j.
  • any terminal L,- which is connected to an input E,- transmits to this latter the binary value S this being the complemented value ofthe binary value which appears at the output S,- whereas, in the case of any other connection L,--+L no complementation need be taken into consideration.
  • a connection between an output S,- and an output L,- is equivalent to a vertical connection between L; and L,- after complementation of the value S; of the elementary circuit 1'. This lastmentioned characteristic is brought out by means of the example given in FIG. 6.
  • connection S-L is not essential for the purpose of realizing transcoding functions, these connections being simply very practical insofar as they permit a reduction in the number of connections necessary and increase the performance potentialities of the matrix but at the expense of the total switching time.
  • connections L- E ensure the complementation of the variables, the connections L- L (parallel connection of circuits) serve to write OR functions and the series connections L- C which are pre-wired in the matrix in the case of any one line serve to write the AND function; the two last-mentioned types of connections are an accurate reproduction of the symbolism of writing of the binary analysis already mentioned and ensure a total switching time which is independent of the function to be realized.
  • FIG. 7 shows by way of example the realization of the transcoding functions of wherein S has priority These functions are known as memory functions.
  • the realization of these memory functions by means of the matrix in accordance with the invention shows that this latter permits the realization of so-called reflex" functions and the construction of sequential systems.
  • the elementary circuits A can be constructed in different ways: by means of discrete elements, printed circuits or integrated circuits. For example, it is possible to construct a module in an integrated circuit in which a plurality of series-connected elementary switching circuits are grouped together.
  • the matrix location of elementary switching circuits provides total freedom to modify a completed project at any moment, this flexibility being obtained neither at the expense of rapidity nor at the expense of reliability of operation. Furthermore, the dimensions of matrix are always adaptable to the users requirements by extension or subdivision. its use is not limited to the combinatorial system (transcoding function) and its constructional design serves to carry out sequential operations while taking transient information into account; it also serves to produce time-delays whenever these latter prove necessary for a correct arrangement of sequences.
  • the overall cost price and the time of construction of an assembly can be accurately determined at the actual design stage since there is no expenditure or additional studying time to be added to the conditions of supply of the elementary switching circuits employed. Moreover, the simplicity of the matrix structure is a guarantee both of economy and reliability of operation.
  • a switching matrix for realizing at least one transcoding function having a constant switching time-delay between different binary variables comprising an array of switching circuits which are all identical and disposed in the form of a matrix table having n lines and m columns, each circuit comprising an input terminal C proper of said circuit and an input terminal E of said applied binary variable, an output terminal L proper of said circuit and an auxiliary output terminal S which supplies the complemented value of the value which appears at said output terminal L proper, each succeeding circuit on a line of said matrix having an input C proper coupled to the output L proper of the preceeding circuit which is located on the same line and each preceeding circuit on a line of said matrix having an output L proper coupled to the input C proper of the succeeding circuit which is located on the same line, the inputs C proper of the circuits of the first column of said matrix being all connected to ground, means for providing selected connections between the different circuits through the intermediary of the terminals L, E and S, and means for applying said binary variables to said terminals E, the structure of each circuit being such
  • each circuit is constituted by a first transistor having a base coupled to the input E of the binary variable through a Zener diode, an emitter coupled to the output L proper, a first biasing resistor connected between said binary variable input E and a bias voltage source, a second transistor having a grounded emitter, a collector coupled to the auxiliary output S and a base connected through a Zener diode to the collector of said first transistor, and a second biasing resistor connected between said voltage source and the collector of said first transistor.

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  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Logic Circuits (AREA)
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US00305061A 1971-11-16 1972-11-09 Switching matrix Expired - Lifetime US3810160A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3996560A (en) * 1974-05-16 1976-12-07 Case Western Reserve University Sequencing unit
US4821258A (en) * 1986-08-06 1989-04-11 American Telephone And Telegraph Company At&T Bell Laboratories Crosspoint circuitry for data packet space division switches

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3609546A (en) * 1968-04-10 1971-09-28 Ericsson Telefon Ab L M Arrangement for indicating leak currents in a diode matrix by means of current sensors in the conductors of the matrix

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3609546A (en) * 1968-04-10 1971-09-28 Ericsson Telefon Ab L M Arrangement for indicating leak currents in a diode matrix by means of current sensors in the conductors of the matrix

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3996560A (en) * 1974-05-16 1976-12-07 Case Western Reserve University Sequencing unit
US4821258A (en) * 1986-08-06 1989-04-11 American Telephone And Telegraph Company At&T Bell Laboratories Crosspoint circuitry for data packet space division switches

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FR2161159A5 (https=) 1973-07-06
JPS4863654A (https=) 1973-09-04
DE2256295A1 (de) 1973-05-24
GB1390659A (en) 1975-04-16
DE2256295C3 (https=) 1975-04-03
DE2256295B2 (de) 1974-08-08

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